IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 7. J U L Y 1993 1231

Integrated Electronic Shutter for Back-Illuminated Charge-Coupled Devices

Robert K. Reich, Member, IEEE, Robert W . Mountain, William H. McGonagle, Member, IEEE, Jammy Chin-Ming Huang, Jonathan C . Twichell, Bernard B. Kosicki, Senior Member, IEEE,

and Eugene D. Savoye

Abstract-A novel electronic shutter has been integrated into the structure of a back-illuminated frame-transfer charge-cou- pled device (CCD) to permit short optical exposure times and to reduce the smear that occurs during the transfer of an image from the CCD detection area. The shutter consists of an n+ shutter drain placed in the vertical channel stop regions and stepped p-type buried layers formed by a high-energy implan- tation (1.0-1.5 MeV) located between CCD n-type buried chan- nel and p- substrate. These structures create electric fields that direct the photqelectrons to either the CCD detection region or the n+ shutter drain. The ratio of photons detected with the shutter open to phptons detected with the shutter closed has been measured to be greater than 75 000 for wavelengths below 540 nm. The corresponding shutter rise and fall times are less than 55 ns.

I. INTRODUCTION IGH-SPEED shuttering in photodetector arrays has H been used to eliminate image degradation caused by

smear and also to resolve optical pulses that are closely spaced in time. Image smear can be an important factor in high-frame-rate applications, where the time to transfer the image from the detection area into the frame-store area is comparable to or greater than the image stare or inte- gration time. Applications that require shuttering include high-speed photography, target tracking, range gating, and real-time adaptive optics.

Previously, a fast shutter was often external to solid state devices. Gated intensifiers, Kerr cells, and Pockels cells have been used, but these approaches result in de- graded image quality or are very complex and unreliable in operation. The most common example of attempts to integrate the shutter with solid-state charge-transfer de- vices are frame-transfer and frame-interline-transfer charge-coupled device (CCD) architectures. Most frame- transfer CCD's are operated such that the image-integra- tion time is substantially longer than the image-transfer time [l], and therefore they do not address high-frame- rate or short-exposure-time applications. Other solid-state image sensors that include the shutter function often do

Manuscript received July 27, 1992; revised December 15, 1992. This work was sponsored by the Department of the Air Force and SDI0 under Air Force Contract 19628-90-C-0002. The views expressed are those of the authors and do not reflect the official policy or position of the U.S. Government. The review of this paper was arranged by Associate Editor W. F. Kosanocky.

The authors are with Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA 02173-9108.

IEEE Log Number 9208923.

so at the expense of pixel fill factor [2]-[4], sensitivity [5], [6], or complexity [7], [8]. The frame-interline-trans- fer CCD accomplishes fast shuttering by transferring in- tegrated signal charge either into a light-shielded CCD to open the shutter or into a lateral or vertical overflow drain to close the shutter. The lateral overflow drain and the light-shielded CCD reduce pixel fill factor, while the ver- tical overflow drain decreases the visible long-wavelength sensitivity of the photosensor site.

In this paper, we describe an electronic shutter incor- porated into a back-illuminated frame-transfer CCD so that 100% fill factor, flexible integration times, low-noise operation, and near-reflection-limited quantum efficien- cies over the visible spectrum are obtained simulta- neously. The structure of the electronic shutter and its in- tegration into a conventional frame-transfer CCD pixel are explained, followed by a description of the shutter oper- ation and an experimental characterization.

11. DEVICE STRUCTURE The electronic shutter has been integrated into an ex-

isting process for a back-illuminated buried-channel CCD [9] by the inclusion of two extra masking and implanta- tion steps. Fig. l(a) shows a top view of the frame-trans- fer CCD with electronic shutter, and Fig. l(b) provides top and cross-sectional views of a single back-illuminated pixel. Two structures differentiate the electronically shut- tered from the unshuttered frame-transfer CCD: an nf dopant (shutter drain) placed between the vertical transfer channels in the imaging array, and stepped p buried layers extending across the width of the pixel. The peak concen- trations of the p buried layers are located approximately 1.4 pm (shallow layer) and 2.0 pm (deep layer) below the silicon-silicon dioxide interface. The n+ shutter drain and p buried layers are formed in the first two masking steps before the start of the conventional CCD process sequence.

The electronically shuttered imagers are fabricated using high-resistivity (greater than 3000 a cm) silicon starting material. First, the n+ shutter drain is formed by a dual implantation of arsenic and phosphorus. A rela- tively high-dose arsenic implantation produces shutter drain regions with low sheet resistivities, while a lower- dose phosphorus implantation reduces capacitance and in- creases breakdown voltages above values that would be obtained from a single arsenic implantation. As will be

0018-9383/93$03 .OO 0 1993 IEEE

1232 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. NO. 7. JULY 1993

TOP VIEW

CHANNEL STOP n+SHUlTER DRAIN n+ SHUTTER DRAIN INPUT DIODE

IMAGING ARRAY

DEEP p BURIED LAYER

p BURIEDLAYER

CROSS-SECTIONAL VIEW

n BURIED CHANNE FIELD OXIDE n'SHUlTER DRAIN

OUTPUT STEPPED p BURIED

OUTPUT REGISTER

(a) (h)

Fig 1 (a) Top view of a frame-transfer CCD with electronic shutter and (h) top and cross-sectional views of a single back- illuminated pixel showing the locations of the stepped p buried layers and nt shutter drains

a 121 I I I I I I I 5 0 0 5 1 0 1 5 2 0 2 5 3 0

DISTANCE (pm)

Fig. 2. Simulated impurity concentration versus vertical distance through the n + shutter drain and adjacent shallow p buried layer.

described later, the shutter is opened and closed by simul- taneously changing the voltage values on the shutter-drain and imaging-array gate electrodes. The charging rate of the shutter drain is, in part, determined by the shutter- drain capacitance. Both the area and sidewall capacitance are reduced by the outdiffusion of the low-dose phospho- rous implant from the arsenic. The low sheet resistance and capacitance values result in faster electronic shutter switching times.

Both p buried layers are formed by a boron implanta- tion at a single energy in the range 1 .O-1.5 MeV through a single stepped oxide mask. As will be described later, the shallow p buried layer centered beneath the buried channel forms the collection portion of the pixel during image capture, while the deep p layer creates a storage region. The collection region of the pixel thus has an as- sociated depletion region which is independent of the electrans that accumulate in the storage region up to a significant fraction of the pixel full well. Figs. 2 and 3 show the calculated impurity concentration versus vertical distance through the nf shutter drain and n buried chan- nel, respectively, for devices that have finished fabrica-

IL

0 0 0 5 1 0 1 5 2 0 2 5 3 0

DISTANCE (pm)

Fig. 3 . Simulated vertical doping profile showing the location of the shal- low p buried layer with respect to the n buried channel.

tion. Both regions in Figs. 2 and 3 include the shallow p buried layer.

111. SHUTTER OPERATION The process simulation tool SUPREM was used to de-

termine physical parameters associated with the electronic shutter, such as doping concentration and location of the p buried layers. The device simulators PISCES and CANDE were used to predict shutter performance. Fig. 4 shows typical depletion regions, as generated by CANDE, in a back-illuminated pixel for the two elec- tronic shutter operating conditions, shutter open and shut- ter closed. To open the shutter and capture an image, a voltage is applied to the imaging-array clock electrode VIA such that the depletion region extends from the gate di- electric through the n buried channel and shallow p buried layer into the lightly doped p- substrate. A voltage is ap- plied to the shutter drain to reverse-bias the junction, but is kept small enough that there is no depletion through the shallow p buried layer. Photoelectrons created by the op-

REICH et al . : INTEGRATED ELECTRONIC SHUTTER

’ 1 I‘t 1.1 t f n + SHUTTER DRAIN DLPLETION REGION

SHUlTER OPEN

(a) a\? n BURIED

DEPLETION REGION

VSD CHANNEL

f f I I I l l SHUrrER CLOSED

(b) Fig. 4. Single back-illuminated pixel in a CCD with electronic shutter showing the depletion regions associated with the n+ shutter drain and n buried channel with (a) shutter open and (b) shutter closed.

tical signal in the p- substrate are attracted by the electric field to the n buried channel detection area where the charges are stored. The undepleted shallow p buried layer creates a potential barrier [lo] that repels the photoelec- trons away from the n+ shutter drain. An expression for the barrier voltage, assuming a Maxwellian distribution for the hole carriers, is

kT N B v = - x log, - 4 NSUB

where k is Boltzmann’s constant, T is the temperature in Kelvins, q is the electronic charge, NB is the peak con- centration of the p buried layers, and N s u B is the substrate concentration. With the insertion of values used in the device simulator CANDE, the barrier voltage calculated from (1) is approximately 0.2 V, or about 7.5 times greater than the room-temperature thermal energy of an electron in the lattice.

Photoelectrons enter the n buried channel from the p- substrate through the region of the shallow p buried layer near the center of the pixel (see Fig. 4). A potential bar- rier, similar to that for the n+ shutter drain, stops photo-

25 - 1.4 pm p BURIED LAYER

COLLECTION REGION

‘ I - I 2OpmpBURlEDLAYER

STORAGE REGION

0 0 5 1 0 1 5 2 0 2 5 3 0 DISTANCE (pm)

(a)

25

lvsD=18, ;m - 0 4 3’

9 1.0 1 5 2.0

1233

0 0.5 1.0 1.5 2.0 2.5

DISTANCE (pm)

(b) Fig. 5 . Vertical potential profiles through the (a) n buried channel and

(b) n + shutter drain as a function of V,” and V,,, respectively.

electrons from directly entering the n buried channel re- gion above the deep p buried layer. The potential well in the buried channel adjacent to the deep p buried layer is more positive than that in the channel adjacent to the shal- low p buried layer. As a result, the electrons that enter through the shallow p buried layer are transferred to the buried channel region above the deep p buried layer. The depletion region under the central, collection part of the pixel is insensitive to the number of photoelectrons that have been captured up to some maximum amount. Addi- tional photoelectrons beyond this maximum are shared between the collection and storage regions of the pixel, causing a gradual collapse of the depletion region.

When the electronic shutter is closed, voltages applied to the imaging-array clock electrodes are not sufficient to deplete through the p buried layers, but are adequate for transfer of charge from pixel to pixel. A large voltage is applied to the n + shutter drain to cause the depletion re- gion to spread beyond the shallow p buried layer deep into the p- substrate, as shown in Fig. 4. Photoelectrons are attracted by the electric field to the shutter drain, and as a result are not detected at the CCD buried channel. Fig. 5(a) and (b) presents simulated results for typical shutter process conditions, showing the variation of potential with vertical position as a function of V,A and VsD. The poten- tial profiles illustrate the voltage conditions under which

1234 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 7. JULY 1993

SHUlTER-- SHUlTER _.,SHUllER OPEN CLOSED OPEN

1 4 T 0 1 8 V 1

f iTO1PV

1 5 T 0 1 8 V

62 7 .m- -6TOOV J- 6 T 0 1 2 V

4TOOV n m- n 4 T O O V $3

Fig. 6. Timing diagram and typical voltage levels required for image cap- ture and output for a CCD sensor using the electronic shutter. For these calculations the shallow and deep p+ buried layers were 1.4 and 2.0 pm below the silicon surface, respectively.

the shallow p buried layer is depleted for the n buried channel and n+ shutter drain regions, respectively.

Typical voltage levels and timing for the devicl: are shown in Fig. 6. During image integration the electronic shutter is open. After the image charge has been captured the shutter is closed, and this charge is then transferred to the frame-store array where it is protected from light by an aluminum shield. While this image charge is being clocked out of the chip the shutter is again opened, and image integration can begin again for the next frame. A restriction on all applied voltages is that the magnitude be less than that necessary for avalanche breakdown. Tri- level clocking is required on the imaging-array electrode that is used in collection of the photoelectrons during im- age capture. The second clock phase in the imaging array (42 in Fig. 6) is used to collect the photoelectrons when the shutter is open. The voltage applied to 42 to open the shutter is in the range of 15 to 18 V. The simulation tools were used to determine the location and concentration of the p buried layer so that the device electric fields were much less than would cause carriers to avalanche but were still high enough to efficiently collect photoelectrons.

IV . SHUTTER CHARACTERIZATION Measurements demonstrating the capability of the in-

tegrated electronic shutter were done on a 64 X 64 back- illuminated frame-transfer CCD [ 113 with a 27 X 27 pm pixel size (each clock phase was 9 pm wide), a substrate thickness of 17 pm, and a silicon substrate resistivity of about 6000 0 cm. Fig. 7 shows the typical locations and dimensions of the electronic shutter structures within the pixel for the devices measured.

The measured and calculated extinction ratios (ratio of photons detected shutter open to photons detected shutter closed) are shown in Fig. 8 for wavelengths between 450 and 750 nm. For wavelengths less than 540 nm the ex-

p- SUBSTRATE

Fig. 7. Cross section of a shuttered pixel viewed perpendicularly from the transfer channel. The locations and dimensions in micrometers of the elec- tronic shutter structures are shown. All measurements were done on a 64 x @-pixel back-illuminated CCD imager with 27 X 27 pm pixels.

0 l o 4 t i a

103

z : z -

O r

x - w lo2

10' I 1 I 1 I I

450 500 550 600 650 700 750 800

WAVELENGTH (nm)

Fig. 8. Measured and calculated extinction ratios versus wavelength for an electronically shuttered CCD.

tinction ratio is greater than 75 000, the highest value that could be reliably measured with the experimental setup. The extinction ratio is observed to decrease with increas- ing wavelength, in agreement with a sample model of ex- ponential dependence of phototi absorption on the absorp- tion length (e-"). The extihction ratio for a given wavelength remained constant up to photoelectron flux densities as high as 2.5 X 1Ol2 cmP2

In the devices measured, tlii: electronic shutter was de- signed for use in a wavefront sensor that was operated at approximately 500 nm. The device fabrication process can be modified to optimize the shutter for a particular light wavelength range. Operation of the shutter at longer wavelengths, where the absorption length increases, re- quires a thicker substrate to ensure that all the photoelec- trons are created under the p buried layer. As the silicon thickness is increased the substrate resistivity must be in- creased to ensure that the depletion tegions extend to the back surface of the device, for good collection efficiency and isolation. For instance, increasing the silicon thick- ness from 17 to 25 pm increases the extinction ratio by a factor of 8 at 700 nm, and even larger increases are found at shorter wavelengths, as shown by the calculated curve in Fig. 8.

Shutter rise and fall times were measured by stepping in time a pulse of light through the shutter transition re- gions (closed to opened and opened to closed) and re- cording the CCD output response versus the time steps. A shutter function S( t ) is defined as [D( t ) - D , ] / [ G ( t ) - D,] , where D ( t ) is the number of photoelectrons de-

s-I.

REICH et al.: INTEGRATED ELECTRONIC SHUTTER 1235

tected out of the total number G(t) generated by a unit light pulse at time t, and D, is the number of photoelec- trons detected from a similar pulse of light with the shut- ter fully closed. Defined in this way, the shutter function can be modeled as a linear shift-invariant system for sig- nals below the CCD full well. Thus the CCD output re- sponse can be written as the convolution of the shutter function with a light pulse input,

O(t) = S(t)*Z(r) (2)

where O ( t ) and Z ( t ) are the CCD output and the rate of photoelectrons generated by the light pulse, respectively, in our experiments. Since both the CCD output response and light signal input are known, the shutter function can be found by taking the Fourier transform of ( 2 ) , dividing the CCD output by the light signal function, and taking the inverse Fourier transform.

The measured CCD output signal for shutter rise and fall regions, shown in Fig. 9, demonstrates that the switching times are less than 55 ns taken between the 10% and 90% values. The response in Fig. 9 is typical of all locations within the imaging array, indicating that the re- sponse time of the electronic shutter for this size array is not dominated by transmission-line time delays of volt- ages propagating along the shutter drain and imaging-ar- ray gate electrodes. Since the input light pulse used in the measurement had a duration of approximately 6-8 ns, the CCD output signal gives a reasonable measure of the shutter switching times. The rise and fall time of the ex- temal shutter drive circuitry was about 35 ns, while the time to establish the depletion regions and then for the photoelectrons to reach either the storage or shutter drain regions after being generated by the light pulse is esti- mated to be a few nanoseconds. Most of the measured switching time for this size array is attributed to the ex- temal drive circuitry.

As discussed in Section 11, the stepped or dual p buried layers provide a depletion region that is independent of the signal accumulated in the well up to some maximum amount. Fig. 10 shows the pixel response versus integra- tion time for both single and dual p buried layers where the pixels are illuminated by a constant-intensity light source. The shutter drain was biased so the depletion re- gion went through and slightly beyond the layers. As long as the depletion region associated with the detection area remains constant, the pixel response should have a linear dependence on integration time with the photoelectrons dividing in some constant proportion between the shutter drain and the n buried channel detection area. The results in Fig. 10 show that the pixel response for the dual p bur- ied layers remains linear up to about 2 / 3 of the pixel full well, while the single p buried layer goes sublinear at rel- atively low signal levels. The nonlinear pixel response of the dual p buried layers at high signal levels helps main- tain some image contrast under conditions that would sat- urate a conventional detector pixel. Thus the nonlinear response effectively increases the pixel dynamic range.

The electronic shutter can also be used to attenuate con-

-0 10 20 30 40 50 60 70

TIME (ns)

Fig. 9 . Shutter rise and fall times of a typical electronically shuttered pixel

LINEAR PIXEL RESPONSE

TYPICAL FULL

ijj 100

E 1 1 8

p BURIED LAYER

A DUAL LEVEL

0 SINGLE LEVEL

0 0 I I I I I I 0 0 100 200 300 400 500 600

INTEGRATION TIME (mS)

Fig. 10. Pixel response of single and dual p buried layers as a function of integration time. The linear pixel response is given for reference.

tinuously the detected signal between shutter-open (max- imum light detected) and shutter-closed (minimum light detected) conditions. This is done, starting from the shut- ter-open operating condition, by steadily increasing the shutter drain voltage beyond that for the shutter-open con- dition. As the shutter drain voltage is increased, more photoelectrons flow out through the drain and are not de- tected, which results in a gradual decrease in signal out- put.

Substantial smear occurs in a frame-transfer CCD when the integration period becomes comparable to the image- transfer time. Fig. 11 shows photographs of a bar pattern image projected onto the CCD imaging array for devices fabricated with and without the electronic shutter. The CCD is being illuminated by a constant-intensity light source with the light having passed through a bandpass

1236 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 40, NO. 7, JULY 1993

4 4

POSlTlON POSITION t - (a) (b)

Fig. 11. Photographs of a bar pattern image projected onto the CCD im- aging array of a device (a) with the electronic shutter and (b) without the shutter. The integration time is approximately 400 ps while the transfer time is approximately 8 ms.

filter. The bandpass region of the filter is centered at ap- proximately 530 nm and is 100 nm wide. The integration time for this example is approximately 400 ps while the transfer time is approximately 8 ms. The image charge is transferred to the left in these photographs. In the un- shuttered device the three upper vertical bars smear and appear to be one wide horizontal stripe, and the three hor- izontal bars smear into three horizontal stripes. The pho- tograph of the image for the shuttered device shows a dis- tinct bar pattern, indicating that the smear has been significantly reduced by closing the shutter during the frame-transfer time.

V. SUMMARY An electronic shutter has been successfully integrated

into the architecture of a back-illuminated frame-transfer CCD imager. The shutter has been added to the pixel structure while maintaining the high quantum efficiency and pixel fill factor associated with back-illuminated frame-transfer CCD detectors. The electronic shutter has measured extinction ratios greater than 75 000 for wave- lengths shorter than 540 nm and can be switched in times less than 55 ns. The extinction ratio performance of the electronic shutter can be improved at longer visible wave- lengths by increasing the silicon substrate thickness and resistivity. A stepped p buried layer component of the shutter has resulted in a linear pixel response up to a sub- stantial fraction of the full well by creating a pixel that has separate collection and storage regions. The stepped p layer devices have shown increased pixel dynamic range by providing a sublinear response of the pixel at high sig- nal levels.

[31

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tions,” in ISSCC Dig. Tech. Papers (New York: IEEE), 1989, pp

N. Teranishi and Y. Ishihara, “Smear reduction in the interline CCD image sensor,” IEEE Trans. Electron Devices, vol. ED-34, no. 5 pp. 1052-1056, 1987. Y. Ishihara, E. Ods, H. Tanigawa. N. Teranishi, E. Takeuchi, I. Akiyama, K. Arai. M. Nishimura, and T. Kamata, “Interline CCD image sensor with an anti blooming structure,” in ISSCC Dig. Tech. Papers (New York: IEEE), 1982, pp. 168-169. T . Kuroda, T . Kuriyama, Y . Matsuda, T . Kozono, S. Matsumoto, Y . Hiroshima, and K. Horii. “A smear suppressing CCD imager,” in ISSCC Dig. Tech. Papers (New York: IEEE), 1986, pp. 94-95. T. Ozaki, H. Kinugasa, and T. Nishida, “A low-noise line-amplified MOS imaging device,“ IEEE Trans. Electron Devices, vol. 38 , no.

P. A. Levine, “Transfer smear reduction in line transfer CCD im- agers,” U.S. Patent 4 594 612, 1986. C. M . Huang, B. E. Burke, B. B. Kosicki, R. W. Mountain, P. J . Daniels, D. C. Harrison, G. A . Lincoln, N. Usiak, M. A. Kaplan, and A. R. Forte. “A new process for thinned back-illuminated CCD imager devices,“ in Proc. I989 Int. Symp. on VLSI Technology, Sys- tems, and Applications (New York: IEEE), 1989, p. 98. J . R. Hauser and P. M. Dunbar, “Minority carrier reflecting prop- erties of semiconductor high-low junctions,” Solid-Stare Electron., vol. 18, no 718, pp. 715-716, 1975. J . C. Twichell, B. E. Burke. R. K. Reich, W. H. McGonagle, C. M. Huang. M. W . Bautz, J . P. Doty, G. R. Ricker, R. W. Mountain, and V. S. Dolat, “Advanced CCD imager technology for use from 1 to 10 000 A ,” Rev. Sci. Instrum., vol. 61, no. IO, pp. 2744-2746, 1990.

90-9 I .

5, pp. 969-975, 1991.

Robert K. Reich (M’83) received the B.S. degree in electrical engineering from the Illinois Institute of Technology, Chicago, in 1978, and the M.S. and Ph.D degrees in electrical engineering from Colorado State University, Fort Collins, in 1980 and 1982, respectively.

He joined the Fairchild linear Division, Mt. View, CA, in 1982 where he worked on the de- velopment of a 4-pm analog CMOS process. In 1984, he joined the Solid State Electronics Divi- sion, Honeywell Inc., Plymouth, MN. While

there, he worked on device characterization, modeling, and reliability of near-micrometer CMOS technologies. Later he was involved with process development of a I-pm CMOS technology. In 1987, he joined the Solid State Division, MIT Lincoln Laboratory, Lexington, MA, as a member of the technical staff. He is currently working on the design of high-frame- rate and low-nose charge-coupled devices.

Robert W. Mountain received the B.I.T. degree in electronic engineering from Northeastern Uni- versity, Boston, MA, in 1972.

He joined Lincoln Laboratory, Lexington, MA, in 1968 and presently manages the microelec- tronics silicon device fabrication facility. He has been involved with all aspects of silicon fabrica- tion such as bipolar, NMOS, and CMOS devices. For several years now he has been instrumental in the fabrication of large-area CCD imagers. as well as signal processing and infrared CCD’s.

RElCH er al.: INTEGRATED ELECTRONIC SHUTTER 1237

William H. McGonagle (M’89) received the B.S.E.E. degree from Northeastem University, Boston, MA.

He has been at Lincoln Laboratory, Lexington, MA for thirty years. He is now an associate staff member in the Microelectronics Group.

Jammy Chin-Ming Huang was born in Taiwan, ROC, in 1950. He received the B.S. and M.S. de- grees in physics and the Ph.D. degree in electrical engineering from the National Taiwan Normal University, National Tsin-Hua University, and the University of Michigan, Ann Arbor, in 1973, 1976, and 1983, respectively.

From 1979 to 1982 he worked for the Bendix Research Laboratory where he set up a prototype Silicon Micromachining Laboratory. He also de- veloped and demonstrated the first silicon-based

integration sensor system in his Ph.D. dissertation. From 1983 to 1992 he was with MIT Lincoln Laboratory, Lexington, MA, first working on the CMOS double metal and shallow junction processes for Wafer Scale Inte- gration, then he was responsible for CCD process yield improvement, and developed a back-illuminated CCD imager process. He is now with Indus- trial Technology Research Institute. His research interests include Inte- grated Sensor Systems and Vacuum Microelectronics.

Jonathan C. Twichell received the A.B. degree in physics from Earlham College, Richmond, IN, in 1974. He received masters and Ph.D. degrees in nuclear engineering from the university of Wis- consin-Madison, in 1978 and 1984, respectively.

His research interests have included plasma- surface interactions in fusion devices, computa- tionally efficient phase reconstruction techniques, detector and instrumentation development for adaptive optics, and, recently, diamond semicon- ductor and field emission devices. He is presently

a staff member in the Submicrometer Technology group at the MIT Lincoln Laboratory, Lexington, MA.

Bernard B. Kosicki (M’73-SM’82) received the B.A. degree in physics (with Distinction) from Wesleyan University, Middletown, CT, in 1961. and the degrees of Master of Arts (1962) and Doc- tor of Philosophy (1967) from Harvard Univer- sity, Cambridge, MA, both in solid state physics.

For the next six years, he was a Member of Technical Staff at Bell Telephone Laboratories at Murray Hill, NJ, where he conducted research on growth, structure, and dielectric and electrolumi- nescent properties of various thin film materials

and structures. He then became involved in CCD device and process tech- nology shortly after these devices were invented. He then spent the next ten years in managerial positions at Sperry Research Center, General MNOS device development and pilot production, and then in process and product engineering for microprocessor production, and finally in advanced silicon technology development. In 1983 he joined MIT Lincoln Laboratory, Lex- ington, MA, with responsibility for CCD technology development and yield improvement. He now serves as Assistant Leader of the Microelectronics Group, where he is responsible for silicon process and device technology. He is an author or co-author of twenty technical publications and five pat- ents.

Dr. Kosicki is a member of Phi Beta Kappa and Sigma Xi.

Eugene D. Savoye received the Ph.D. degree from the University of Minnesota, Minneapolis.

He joined RCA’s David Sarnoff Research Lab- oratories, in 1966. In 1970 he became Manager, Advanced Technology, at RCA Lancaster, PA, where he initiated RCA’s early engineering work on Charge Coupled Devices (CCD’s). In 1983, as Director, CCD and Silicon Target Technology, he initiated and directed RCA’s corporate program to develop high-performance CCD imagers for tele- vision, which resulted in the world’s first all solid

state studio quality TV cameras and the reception of the 1985 “Emmy” Award for Outstanding Technical Achievement. He joined MIT Lincoln Laboratory, Lexington, MA, in 1987, and in 1990 he assumed his present position as Group Leader, Group 87, with responsibility for the develop- ment of advanced Si integrated circuits, including CCD imagers and CCD signal processing devices.