Integrated power management circuit for piezoelectronic generator in wireless monitoring system of...

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Published in IET Circuits, Devices & SystemsReceived on 9th November 2007Revised on 21st July 2008doi: 10.1049/iet-cds:20070342

ISSN 1751-858X

Integrated power management circuit forpiezoelectronic generator in wirelessmonitoring system of orthopaedic implantsC. Jia H. Chen M. Liu C. Zhang Z. WangTsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University,Beijing 100084, People’s Republic of ChinaE-mail: [email protected]

Abstract: Piezoelectric (PZT) materials are capable of converting the mechanical energy of compression intoelectrical energy. With the recent advent of extremely low-power electrical devices, PZT generators havebecome attractive in many kinds of applications, especially for biomedical applications. Piezoelectronicgenerators are used in a wireless monitoring system of orthopaedic implants. Due to their poor sourcecharacteristics, the efficiency of PZT generator is low. A hybrid direct current (DC)–DC, comprising a switchedcapacitor (SC) DC – DC converter and a low dropout (LDO) linear voltage regulator, is presented to improveconversion efficiency. A bandgap reference (BGR) circuit which works in sub-threshold region is alsopresented. Because SC DC – DC converter works in the highest voltage region in this system, small powersupply current, including supply current through BGR and other auxiliary modules, means low powerconsumption. BGR’s power supply voltage can be varied from 3 to 16 V. Its supply current is only 3.2 mA at125 8C and its temperature coefficient is 46 ppm. Stacked switches technique is proposed to reduce leakagecurrent in switching process of SC converter. Simulation results show that the efficiency of SC’s converter canreach 88%, that of LDO can reach 80% and that of the overall system can reach 66%, including powerconsumption of all auxiliary components, which is far higher than previous work.

1 IntroductionMechanical stresses applied to piezoelectric (PZT) materialsdistort internal dipole moments and generate electricalpotentials in proportion to the applied forces. Theproperties are used not only to realise PZT sensors, butalso to generate electricity [1]. Due to their poorsource characteristics (high voltage, low current, highimpedance), it is not widely used in the electronics systemas a generator before. With the recent advent of extremelylow-power electrical devices, PZT generators have becomeattractive.

In modern medical systems, the most important trends arelow power consumption and integration. First, low powersystems are becoming more and more popular because suchsystems not only reduce the consumption of electricity

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energy, but also make them portable, even being implantedin human beings’ body. Secondly, the system on a chip ofmedical instruments make more functions be integrated ina single chip. These techniques can further reduceinstruments volume and power consumption. In this paper,we use PZT generator in vivo, in which the PZTgenerator not only supplies the electric system, but alsodetects the defects of artificial joint through signalvariations generated by PZT sensors, which is a wirelessmonitoring system of the orthopaedic implants(WMSoOI). Reference [2] shows the details of this system.The whole WMSoOI will achieve the following functions:(a) periodically save data obtained by sensors in vivo; (b)wirelessly transmit the data from the memory in vivo to theremote circuit; (c) wirelessly transmit the controlinformation to the embedded chip when necessary; (d)transmit data to the computer for analysis and diagnosis.

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The proposed system architecture shown in Fig. 1 consists oftwo parts: one embedded in the orthopedic implants and theother outside the body, both of which are analogue, digitaland mixed-mode circuits.

Generally, PZT devices used in these kinds ofapplication have high output voltage, so the efficiency ofrectifier is very high, more than 98%. Reference [1, 3, 4]adopt a big capacitor as a storage capacitor to collectelectrical energy, and then make full use of thoseenergies. Conversion efficiency is a very importantparameter in this kind of systems. Reference [1, 3] uselinear voltage regulator to make the electrical energy inthe stored capacitor as usable power supply, whoseefficiencies are 8.8 and 19%, respectively. Shenck andParadiso [4] use forward-switching to regulate theelectrical energy on the storage capacitor, whose efficiencyis 17.6%. All of these papers use commercial devices tofulfil functions, and higher efficiency are expected. Inorder to make full use of the electricity generated by thePZT, which has been stored on a big capacitor, a hybriddirect current (DC)–DC converter circuit is proposed.Our system is easy to be integrated in to a single chip,which will reduce the cost and area, and its efficiency canreach 66%.

This paper is organised as follows. Section 2 will discussthe electrical circuit model of PZT material in this system.Experiment results of multiple PZT devices at differentconditions are introduced. And then the method of makingfull use of PZT energy is introduced. In Section 3, ahybrid DC–DC converter using switched capacitor (SC)DC–DC converter and low dropout (LDO) linear voltageregulator is proposed to improve the converter efficiency.And other related circuits are described in this section.Section 4 will show detailed circuit design issues in everypart. Simulation results will be shown in Section 5, andSection 6 is the summary.

Figure 1 Wireless monitoring system of the orthopaedicimplants

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2 Electrical circuit model for PZTgeneratorElectrical circuit model for PZT generators is typicallyrepresented by capacitors, resistors and inductance, asshown in Fig. 2 [1, 5]. Fin and Vin represent the inputforce and input voltage, respectively and f the ratio ofelectrical output to mechanical input (V/N ). Re, Le, Ce

and Cp0 are equivalent electrical circuit element parameters

to reflect the mechanical element parameters. R at the rightpart of Fig. 2 is the load of the power generator.

A lot of experiments have been done to obtain enough datato perform a nonlinear least-square fitting method, in orderto achieve the parameters in the equivalent electrical circuitin PZT [6]. Because one PZT device harvests limitedmechanical energy, about 1 mW, three or four PZT deviceswill be placed at different locations at the test environmentin parallel, as described in [1, 6]. Converter efficiencies aretested when these devices cooperate together. These PZTdevices had been put at different locations to obtain themaximum output power. And different load resistor R, asshown in Fig. 2, is selected to match the outputcharacteristics of PZT device. Commercial PZT devices areused in our system and their resonant frequency is at80 k Hz. When PZT devices work at 1 Hz frequency,which is the typical frequency of men’s walking frequency,their electrical output is proportional to mechanical forceinput and can output enough energy for the subsequentsystem. In the future, special PZT devices suitable for thesekinds of applications in our system are expected.

Usually, PZT materials only provide very limited electricalpower, for example, about 4 mW. Obviously, it is not enoughfor a complicated signal process system and communicationsystem, including AD converter to detect sensor signal,EEPROM to read and write data and RF to communicatewith host PC. A method similar to that in [3, 4] is used tosolve this problem in this paper.

3 Power converter systemarchitectureFig. 3 shows the power converter system diagram for PZTgenerator. After applying a large capacitor (Cstore) to storePZT electrical energy after rectifier, the proposed powerconverter is used to regulate the electronic power; 5 V is setto be the threshold of this power converter system. Whenthe voltage across Cstore is lower than 5 V, the power

Figure 2 Electrical circuit model of PZT

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Figure 3 Power converter system for PZT generator

converter will stay in a standby mode until the PZT generatorcharges Cstore above the threshold voltage. Otherwise, whenthe output voltage across Cstore is higher than 5 V, powerconverter begins to work. Considering output voltage rippleand conversion efficiency, test results described in [6] showthat a 10 mF capacitor is a better trade-off as the value ofCstore.

Rectifier is used to convert alternative current (AC) powerinto DC power. Several papers have done a lot of work infully integrated rectifier. Triet et al. [7] realise half-waverectifier of PZT material, which is used for low inputvoltage applications. Ghovanloo and Najafi [8] introducefully integrated rectifiers working at high frequencies incommercial CMOS technology.

Voltage ratio controller is used to monitor the inputvoltage and output control signals to set step-downconversion ratio. Output voltage monitor serves as avoltage detector to send a signal to enable or disable clocksignal.

In previous designs, linear voltage regulators, such asMAX666 and so on, are widely used in many systems toregulate the output voltage of the storage capacitor [1, 3, 4].From the working principles of linear voltage regulator,the efficiency of a linear voltage regulator is equal tothe product of the ratio of output voltage to input voltageand the ratio of output current (load current) to inputcurrent. As mentioned before, in PZT generator system,the input voltage is usually much higher than the outputvoltage. For example, the input voltage is from 10 to15 V and the output voltage is usually 3.3, 1.8 and even 1 V,as the standard power supply for current integratedcircuits. So, using a single linear voltage regulator meanspoor efficiency. If current efficiency (ratio of output currentto input current) can reach 98% and output voltage is

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1.8 V, supposing input voltage is 10 V, linear voltageregulator efficiency is about 17.6%; supposing inputvoltage is 15 V, the efficiency is only about 11.8%, which ismuch lower. These data show that the higher the inputvoltage, the lower the converter efficiency of linear voltageregulator.

In this paper, a hybrid DC–DC converter is presentedto improve the converter efficiency. As shown in Fig. 3, aSC DC–DC converter and an LDO linear voltageregulator are combined together to regulate outputsupply voltage. Those circuit modules in dashed block,including bandgap reference (BGR), SC converter,voltage ratio controller, oscillator, clock generation andcontroller and output voltage monitor, work in thehighest voltage region, supplied by VDD, which is thevoltage across the storage capacitor. The dotted blockshows SC converter circuit and its auxiliary circuits.BGR is used to provide voltage reference and currentreference for these circuit modules. In Fig. 3, detailedconnections of the outputs of BGR are not shown.LDO is powered by the output voltage of SC converter,which is represented by VDD_LDO in the dasheddotted block.

The SC converter is used to regulate the charged capacitorsupply from 5–15 to 2 V, and the LDO is used to regulatethe 2 V output voltage to 1.8 V, as illustrated in Fig. 3.The SC converter can perform several ratios of step-downfunctions, such as 1, 2/3, 1/2 and 1/3. All of thesedifferent functions use a same capacitors’ topology, whichwill be set to different topologies according to differentstep-down voltage ratios, as will be illustrated in detail inSection 4.3.

As mentioned before, the SC converter is working underthe highest voltage region, so a BGR which provides

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precise bias current and reference voltage is really necessary inorder to make the oscillator of SC work correctly. Comparedwith devices working in low-voltage region, same supplycurrent consumes more power. So an ultra-low supplycurrent of BGR is preferred. Detailed design issues will bediscussed in the next section.

4 Circuit design issues4.1 Rectifier

The rectifier is a full-wave rectifier composed of four diodes,as shown in Fig. 4. Its function is to convert AC electricalenergy into DC electrical energy. Diodes can be easilyfabricated in commercial CMOS process, although theyhave larger threshold voltage comparing with CMOSdevices.

When voltage on side A of the PZT material is higherthan that of side B, D1 and D4 are shutoff while D2 andD3 are forward turned on. This ties the low voltage side ofthe PZT material to ground while passing the high voltage.Situation is reversed when the voltage of side B is higherthan side A.

When input frequency of rectifier is high and inputvoltage amplitude is low, keeping charging or dischargingparasitic capacitance will greatly degrade the conversionefficiency. In our design, the input voltage will reach15 V, which is far higher than the threshold voltage ofthe diode. And the working frequency is very low, about0.8–1 Hz. So the power consumed on parasiticcapacitance can be ignored. Diode area is set to be30 � 30 mm2, to reduce the parasitic resistor when thediode is ‘ON’ and thus to improve conversion efficiency.Storage capacitor also has the ability to filter outputvoltage ripple. Because the transistor gate breakdownvoltage is 18 V, which is enough for the storage capacitorto be charged into 15 V. Higher voltage across thestorage capacitor will provide more energy for subsequentcircuits.

Figure 4 Rectifier circuit


4.2 BGR circuit

BGR circuit is a basic and very important component inanalogue and mixed signal circuit. It not only providesprecise voltage reference, but also provides precise biascurrents. Mok and Leung [9] summarise BGR circuits forlow-voltage operation, where the current mode is oftenused to keep the output voltage stable under conditionswhen supply changes. It is true in low power supply, wherethe variations of supply are small. As far as large supplyranges are concerned, circuit topology including a voltageoperational amplifier is a good solution.

In order to reduce the power dissipation of BGR,transistors working in sub-threshold regions are used toreduce the supply current. And at the same time, severalhigh performance parameters of BGR must be kept underdifferent conditions such as supply voltage variations,temperature variations and different technology corners andso on.

Fig. 5 [10] shows the concrete circuit of BGR. M1–M5consist of an op-amp to keep the same voltage value of Va

and Vb. M6 and M7 provide the bias current for the op-amp. The output of op-amp is connected to the gate ofM8 and M9. In order to reduce power consumption, all ofthese transistors are biased in the sub-threshold to lowerthe current consumption. Start-up circuits are not shown inFig. 5.

Determining transistors’ sizes is an important step forcircuit design; in this process, gm=Id is a very importantdesign parameter and it represents the ratio oftransconductance gm to drain current Id. In order to obtainhigh ratio of gm=Id to reduce power consumption [11],many people have already done a lot of work. Enz andVittoz [12] presented an EKV model for MOS transistorsand this model can represent the MOS characteristics indifferent working regions using one equation, wherever thepossible regions MOS transistors may work. In [13],researchers proposed another MOSFET model, which hasthe common property that tries to use a unified model forMOS transistors in all regions and corresponding design

Figure 5 Concrete circuit of BGR


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methods. According to these papers, there are severalequations available to design low power circuits

ID ¼ 2p �GBW � CL � n � ft

1þffiffiffiffiffiffiffiffiffiffiffiffi1þ if

p2

!(1)

W

L¼

2p �GBW � CL

mCoxft

1ffiffiffiffiffiffiffiffiffiffiffiffi1þ if

p� 1

!(2)

VDS(sat) ffiffiffiffiffiffiffiffiffiffiffiffiffi1þ if

p� 1

� �þ 4

� �ft (3)

ft ffimft

pL2

ffiffiffiffiffiffiffiffiffiffiffiffi1þ if

p� 1

� �(4)

where ID is the current of MOS transistor from the drain tothe source, GBW the unity-gain bandwidth, CL the loadcapacitance, n the slope factor, ft is thermal voltage, if theinversion level, Cox the oxide capacitance per area, ft thecut-off frequency of MOS transistor, W the width of MOStransistor, L the length of MOS transistor, m the mobilityof electron or hole and VDS the drain to source voltage ofMOS transistor.

Low current was assigned to every branch in Fig. 5. Everybranch of the op-amp is less than 70 nA and the bias currentshould be less than 140 nA at 1258C, and the currentthrough the resistors is less than 1.5 mA. Because thissystem is not very stringent on circuit speed, its GBW isset to be 2.5 KHz. So the if parameter of transistor M1and M2 can be obtained according to (1). Consequently,the W/Ls of transistors are obtained according to (2). Atthe same time, checking ft parameters of transistors isnecessary. If MOS transistors’ parameters satisfy therequirement that unity gain frequency is greater than atleast three times the GBW, the design space will avoid theparasitic diffusion and overlap capacitance to be of thesame order of the load capacitance.

4.3 Charge pump DC–DC circuit

Circuit topology is shown in Fig. 6, which is illustrated indetail in [14]. A and B are used to select different step-down conversion ratios. P1, P2 and P3 are logiccombinations of A, B, ck1 and ck2, as illustrated in Table 1.

Figure 6 SC converter circuit topology

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Equation (5) depicts the relationship between P1, P2, P3

and other signals

P1 ¼ (ck1) �A þ (ck2) �B

P2 ¼ (ck1)A

P3 ¼ (ck2)B

(5)

Integrated capacitors are used to perform the DC–DCconversion functions [15]. For integrated charge pumpDC–DC circuits, there are three kinds of flying capacitors:MOS capacitors, PIP poly-insulator-poly (PIP) capacitorand metal–insulator-poly (MIM) capacitor. Every capacitorhas its own characteristics. MIM capacitors have a goodlinear characteristic, but usually small unit capacitance andbig parasitic capacitance; PIP capacitors do not have a goodlinear characteristic but they have bigger unit capacitancethan MIM capacitance and equal or smaller parasiticcapacitance compared with MOS transistor; MOScapacitors have the biggest unit capacitance in CMOStechnology because the distance between MOSFET gateand substrate is the smallest in the whole process. Favratet al. [16] compare parasitic capacitance among differentkinds of integrated capacitance. After careful considerationand trade-off on unit capacitance and parasitic capacitance,MOS capacitance is preferred in this design.

One of the most important considerations of charge pumpcircuit design is to suppress the leakage current in theswitching process. If PMOS’s drain voltage or source voltageis 0.7 V higher than supply voltage, the PN junction (drainor source of PMOS is regarded as p-terminal, n- well isregarded as n-terminal) will be forward biased, which willlead to generation of leakage current.

There are two approaches to avoid leakage currentgeneration. One is to properly set capacitors’ values; secondis to apply careful clock sequence. When it comes toselection of capacitors’ values, there are severalconsiderations. The larger the value of the output capacitor,the smaller the output ripple of the system. At the sametime, the ratio of output capacitor to flying capacitordetermines the leakage current. If the ratio is large, thenthe voltage variation of flying capacitor will be large. Thiswill add to the possibility of leakage current.

Another approach to suppress leakage current is to useproper clock sequences. 1/2 step-down conversion ratio isconsidered as a typical case, as shown in Fig. 7. Aftercharge is delivered into C1 and C2, M1 and M3 are

Table 1 Relations between control signals and step-downconversion ratio

VDD/Vout 1/3 1/2 2/3

A 0 1 1

B 1 1 0

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turned on, while M2 and M4 are turned off at this time.Then M1 is turned off to implement the chargeredistribution between C1 and C2. If C1 is much smallerthan C2, then the voltage across C1 is much larger thanC2. If M2 and M4 are turned on simultaneously, thevoltage at node 2 is lower than ground. So during theselection of capacitor, C1 is not allowed to be muchsmaller than C2, although this will generate bigger outputvoltage ripple. In this case, C2 is set to be 10 nF and C1 isset to be 1 nF. In addition, if M4 is first turned on, andafter several nanoseconds, M2 is then turned on. Thismethod is named as stacked switches technique (thoseswitches operate like stack), which will reduce thepossibility of leakage current. But stacked switchestechnique needs complex clock sequence; Fig. 8 shows anoscillator circuit to perform such a function.

Fig. 8 shows the concrete circuit of the oscillator. Fourcomparators are used to implement the above-mentionedclock scheme. The four input levels of those four

Figure 7 1/2 step-down conversion SC circuit


comparators are generated directly or indirectly by theoutput of BGR. 1.2 V is generated by BGR directly, while0.2, 0.6 and 0.8 V are generated by resistance voltagedivider on the output of BGR. Several logic operations ofcomparators’ outputs are used to implement the clockscheme. TF, which is generated by clock output signals(ck1 and ck2) and the outputs of comparators after severalspecific logic operations, is the signal to control turning onor off of M1 and M2, changing the charge stored incapacitor C and forming an oscillator. One of theadvantages of this oscillator is that this schemeautomatically realises the controlled clock. When theoutput voltage of SC is lower than the settled value,through the control of TF signal, it will be convenient toachieve the enablement of clock, and then restart the SCconverter. On the contrary, when the output of SC ishigher than the settled value, clock will be disabled throughthe control of TF signal.

Comparators fabricated in CMOS technology have biggerDC offset. In addition, comparators working in SC are oftenaffected by disturbance and noise. So hysteresis comparatorsare applied to reduce the above affections. Fig. 9 shows thedetailed circuit of hysteresis comparator.

The hysteresis comparator uses two-stage structure. In thefirst stage, M1–M7 consists of differential input stage, whereM1 is the tail current, M2 and M3 are source-coupleddifferential input pair, M4, M7 and M5, M6 are cross-coupled bi-stable current sources as load [17, 18]. Theratios of width to length of M5 and M6 are larger thanthat of M4 and M7. M8–M11 consists of the secondstage, which acts as two inverters to increase drive capacity.The comparator consumes 1 mA supply current when it isoperating, which is a low-power design, suitable for thissystem.

In voltage ratio controller and output voltage monitor,same hysteresis comparators are used to detect differentvoltages. Three comparators are used to detect three

Figure 8 Concrete circuit of oscillator


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different voltages in voltage ratio controller and twocomparators are used to detect two different voltages inoutput voltage monitor.

4.4 LDO circuit

Traditional LDO circuit structure consists of threecomponents: an error amplifier, a power transistor and aresistive voltage divider. The positive input of erroramplifier is connected to the reference voltage and thenegative one is connected to the resistive voltage divider ofoutput voltage. The output voltage of error amplifier is tocontrol the gate voltage of power transistor.

Because the subsequent signal circuit includes analoguecomponents, such as AD converters and RF modules,power-supply rejection ratio (PSRR) of LDO is a veryimportant characteristic, which is a measure of the ability ofan output voltage to prevent noise coupled with powersupply. On the one hand, high gain of error amplifier willlead to high PSRR; on the other hand, using PMOStransistor as power transistor will reduce power supply noiseby offsetting it through power transistor and error amplifier[19].

In this case, error amplifier DC gain is more than 70 dBand PMOS transistor is used as the power transistor. Inorder to suppress the supply noise from PMOS transistor,the error amplifier uses NMOS input differential pair andPMOS current-mirror load connected to the supply, asshown in Fig. 10.

5 Simulation resultsAll circuit modules are designed in 0.35 mm CMOS processwith 18 V high-voltage CMOS technology, provided byChartered Corporation.

Figure 9 Hysteresis comparator circuit

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Table 2 shows BGR circuit’s performances. Power supplyregulation measures the variation of the output voltage ofBGR when power supply changes from low power supplyvoltage to high power supply voltage. The variation of theoutput of BGR under different temperature and consumedsupply current are also important parameters for BGRdesign. Another important parameter of BGR is noisevoltage. In saturation region, transistors working in weakinversion always have smaller noise than working in stronginversion, supposing both transistors are at same currentbias. In this design, in order to reduce power consumption,drain current is set to 1 mA, the transistor’s size is farsmaller than those working in strong inversion. At thesame time, several measures are taken to lower noise at theoutput of BGR. First, transistors working in sub-thresholdgenerally have bigger active region, which reduces noise tosome extent. Second, for each noise source, there is apartial cancellation, due to opposing contributions to noiseat the output of BGR. Third, despite the above twomethods, large capacitor is still needed at the output ofBGR to further reduce noise. In this design, when a 1nFcapacitor is added to the BGR output, the noise voltage is109.2 mVRMS from 1 Hz to 10 kHz; when using a 1 mFexternal capacitor at BGR output, the noise voltage is1.964 mVRMS from 1 Hz to 10 kHz.

Table 3 shows SC converter’s performances, whichincludes two components, clock generator and controller.When voltage across Cstore is decreasing with the dischargeof Cstore, voltage ratio controller automatically selectsdifferent step-down ratios. Converter efficiency is calculatedby output power divided by input power. Because SCconverter’s principle is using capacitor to transfer charge,the output of SC converter unavoidably has voltage ripples.Table 3 summarises the simulation results of SC converterunder different input voltage conditions.

Table 4 shows the LDO circuit’s performances. Lineregulation, load regulation and PSRR are importantparameters for LDO design. LDO is expected to outputa constant voltage even if input voltage changes a lot.Line regulation is such a measure of the ability of thepower supply to maintain its output voltage given changesin the input line voltage. Usually, it is simulated by

Figure 10 Concrete LDO circuit

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Table 2 Summary of the BGR circuit results

Parameters Conditions Simulation results

Power supply regulation 3 V , Power supply,16 V

2.770 mV

Temperature 2408C, temperature

,1258C

46 ppm

Supply current

power supply ¼ 3 V Supply current, mA

temperature,8C 25 2.271

125 3.099

power supply ¼ 9 V Supply current, mA


125 3.083

power supply ¼ 16V Supply current


125 3.111

Table 3 Summary of the SC converter results (when load current is 1 mA)

Input voltage, V Step-down ratio Converter efficiency, % Ripple voltage, mV

4.5 2/3 75.15 236.73

6 2/3 82.78 372.93

6 1/2 85.51 198.20

9 1/2 88.25 300.76

9 1/3 79.36 307.15

12 1/3 81.61 449.15

Table 4 Summary of the LDO circuit results

Condition Typical ff ss

line regulation 2 V , inputvoltage , 3 V

122.99 mV 144.99 mV 99.16 mV

load regulation 1 mA , loadcurrent , 5 mA

180.99 mV 170.73 mV 207.30 mV

PSRR input voltage ¼ 2 V 41.96 dB at 1 MHz 71 dBat 10 kHz

43.05 dB at 1 MHz 73 dBat 10 kHz

43.06 dB at 1 MHz 72 dBat 10 kHz

T

changing input voltage at the range from low power supplyto high power supply using DC analysis method. In thesame way, LDO is expected to output a constant voltageeven if load current changes a lot. Load regulation is ameasure of the ability of an output voltage to remainconstant given changes in the load. And it is simulatedby sweeping load current from small load current to highload current using DC analysis method. PSRR shows the

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ability of an output voltage to prevent noise from powersupply noise. It has become an important parameterbecause digital and analogue circuits have been integratedinto a single chip. Switching noise from digital circuitswill greatly affect the performance of analogue circuitsthrough power supply. For example, in this design, SCconverter will bring much supply noise, so PSRR is avery important parameter.


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Fig. 11a shows the dynamic response of LDO when inputvoltage changes between 2 and 3 V in 1 ms. Fig. 11b showsthe dynamic response of LDO when load current changesbetween 1 and 5 mA in 1 ms.

As discussed in Section 3, the efficiency of LDO is givenby the product of output voltage and output current dividedby the product of input voltage and input current. In thisdesign, the output voltage is 1.8 V and the input voltageranges from 2 to 3 V; output current is 1 mA and inputcurrent is the sum of output current and the quiescentcurrent of error amplifier, which is about 20 mA. So, theefficiency of LDO ranges from 58.8 to 88.2%. If the inputvoltage is settled less than 2.2 V, then the efficiency can belarger than 80.2%.

The efficiency of whole system can be achieved by theproduct of the SC’s efficiency and the LDO’s efficiency.Consumed supply current of auxiliary components(including oscillator, voltage ratio controller, output voltagemonitor and BGR) is about 18 mA. These components(including SC converter and auxiliary components) areworking in high voltage region. According to the efficiencyof the SC converter ranges 75–88%, the efficiency of thoseparts working in high voltage region ranges from 73 to82.5%. Assuming that the efficiency of the LDO is 80%,the efficiency of the whole system is ranged from 58 to66%, which is much higher than 8.8 [3], 17.6 [4] and19% [1].

Figure 11 Dynamic response of input voltage and loadcurrent

a Dynamic response of input voltageb Dynamic response of load current

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6 ConclusionBased on the electrical circuit model, this paper chooses aproper storage capacitor for PZT generator. To improveconverter efficiency of whole system, a hybrid DC-DCconverter is presented. A BGR circuit working in sub-threshold region is also presented in order to reduce thepower consumption of auxiliary circuits in this powersystem. Its supply current is only 3.2 mA at 1258C and itstemperature coefficient is 46 ppm. Stacked switchestechnique is used to reduce leakage current in switchingprocess of SC converter. Maximum converter efficiency ofSC converter is 88% and efficiency of LDO can reach80%. The whole hybrid converter’s efficiency can reach66% including all auxiliary components’ powerconsumption, which is far higher than previous work.

7 AcknowledgmentThis research was supported by the National Natural ScienceFoundation of China (No. 60475018).

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[6] CHEN H., JIA C., LIU M., WANG Z.: ‘On power harvesting usingpzt ceramics in orthopaedic implants and circuit design’,J. Tsinghua University (Sci. and Technolo.), 2008, 48, (1),pp. 128–131 (Chinese version)

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