Integrated RF and mmWave CMOS Voltage Controlled
Oscillators
Andrea Mazzanti Dipartimento di Ingegneria Industriale e dell’Informazione,
Università di Pavia - ITALY
ESSCIRC – 2013, Bucharest - Romania
2
Outline
Phase Noise - LTI vs LTV analysis - Comparison between Colpitts and LC-Tank oscillators - The Class-C oscillator
Frequency Tuning - Capacitors tuning and design trade-offs - Issues at mmWaves - Wide tuning range 40GHz VCO in 32nm CMOS
3
Spectral Purity of oscillators
Phase Noise (PN) is defined as:
( ) ( ))(cos 0 ttAtV nφω +⋅=
Assuming negligible amplitude noise:
Tight requirements of wireless systems make VCOs very power hungry, typically burn more than 50% of the synthesizer power
𝐿(∆𝜔)𝑑𝑑 = 10𝑙𝑙𝑙𝑃𝑠𝑠𝑑𝑠𝑠𝑠𝑠𝑑 𝜔0 + ∆𝜔, 1𝐻𝐻
𝑃𝑠
𝐿(∆𝜔) = 12 𝑆𝜙𝑠(∆𝜔)
4
Leeson Model DB.Leeson, "A Simple Model of Oscillator Noise Spectrum " Proc. IEEE 1966. Semi empirical approach to find an analytic expression
Important insights: −maximize resonator Q (technology) and Ps (power dissipation) −L(∆ω) rises with ω0
2 (intrinsically worst phase noise at higher oscillation frequency)
in the ∆ω-2 region:
𝐿(∆𝜔)𝑑𝑑 = 10𝑙𝑙𝑙2𝐹𝑘𝑑𝑇𝑃𝑠
𝜔0
2𝑄∆𝜔
2
noise factor, F, as a fitting parameter
5
Phase Noise Figure of Merit Phase Noise FoM normalizes L(∆ω) to carrier frequency, offset frequency and
power dissipation. The higher the FoM the better is spectral purity for given power dissipation
Assuming Ps=η PDC and replacing the Leeson phase noise equation:
𝐹𝑙𝐹 = −10𝑙𝑙𝑙 𝐿(∆𝜔) ∙∆𝜔𝜔0
2
∙ 𝑃𝐷𝐷,𝑚𝑚
Oscillators design and/or different topologies may improve FoM by: (1) minimizing the noise factor (F) (2) maximizing DC-to-RF power conversion efficiency (η).
𝐹𝑙𝐹 = −10𝑙𝑙𝑙 103𝐹 𝑘𝑑 𝑇2 𝜂 𝑄2
6
LTI analysis of Phase Noise
𝑃𝑆 =𝐼𝜔0𝑉𝜔0
2=𝑉𝜔0
2
2𝑅
Active devices compensate, on average, the tank loss
𝑣𝑠2 = 𝑖𝑠,𝑅𝑇2 + 𝑖𝑠,𝑔𝑚
2 𝑍 𝜔𝑜 + ∆𝜔 2 =4𝑘𝑑𝑇𝑅
1 + 𝛾𝑙𝑚𝑅𝑅𝜔𝑜
2𝑄∆𝜔
2
𝐿𝑡𝑜𝑡𝑠𝑡(𝐴𝐴+𝑃𝐴) = 10𝑙𝑙𝑙𝑣𝑠2
𝑉𝜔02 2⁄
= 10𝑙𝑙𝑙4𝑘𝑑𝑇𝑃𝑠
1 + 𝛾𝑙𝑚𝑅𝜔𝑜
2𝑄∆𝜔
2
7
Limitations of the LTI analysis
𝑃𝑆 =𝐼𝜔0𝑉𝜔0
2=𝑉𝜔0
2
2𝑅
Does not distinguish Amplitude to Phase Noise. Usually ½ is assumed as a correction factor:
𝐹 = 1 + 𝛾𝑙𝑚𝑅 = 1 + 𝑁𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡
𝑁𝑡𝑡𝑡𝑡
The WRONG conclusion is that larger gm (i.e. larger loop gain) deteriorates phase noise
𝐿(∆𝜔) = 𝐿𝑡𝑜𝑡𝑠𝑡(𝐴𝐴+𝑃𝐴) − 3𝑑𝑑 = 10𝑙𝑙𝑙2𝑘𝑑𝑇𝑃𝑠
1 + 𝛾𝑙𝑚𝑅𝑇𝜔𝑜
2𝑄∆𝜔
2
8
Impulse Sensitivity Function
Noise to phase noise conversion is a LTV process (Hajimiri & Lee, JSSC98)
𝜑(𝑡) =
1𝐶𝑉𝑝𝑝
Γ(𝜏) ∙ 𝐼 𝜏 𝑑𝜏𝑡
−∞
Impulse Sensitivity Function (Γ(τ)) encodes time-dependent sensitivity of ϕ to I(t)
For sinusoidal harmonic oscillators, Γ is a sinusoid in quadrature with Vout(t)
9
LTV analysis of Phase Noise
𝑁𝐿𝑡 =1𝑇0 Γ 𝑡 2 ∙𝑇0
0𝑖𝑠,𝑠(𝑡)2𝑑𝑡
, straightforward calculation because PSD is stationary ( 𝑖𝑠,𝑅2 = 4𝑝𝐵𝑇
𝑅 )
𝑁𝐿,𝑅 =
2𝑘𝑑𝑇𝑅
Calculation of NL,gm very complex because gm= gm(t) varies with time.
Noise is cyclo-stationary: 𝑖𝑠,𝑔𝑚2 = 4𝑘𝑑𝑇𝛾𝒈𝒎(𝒕)
Effective noise, generating phase noise:
𝒊𝒏,𝑹𝑹𝟐 𝒊𝒏,𝒈𝒎
𝟐
𝐿 ∆𝜔 = 10𝑙𝑙𝑙𝑅∑ 𝑁𝐿𝑡𝑠
𝑃𝑆𝜔0
2𝑄∆𝜔
2
Transistor effective noise: a general property 1) ISF sinusoidal and in quadrature with voltage, and 2) Devices work as transistors (active region), and 3) Transistor current noise is proportional to gm Transistor effective noise depends only on topology
k
C1
C2L R
VOUTmVOUT
eff,tank eff,dev: 1: mN Nk
γ=
𝐹 = 1 + 𝛾 𝑚𝑝
can be estimated by inspection
Independent of (1) transistor type (MOS, BJT, …), (2) sizing, (3) shape of the current
J. Bank, PhD thesis, Gothenburg, Sweden, 2006.
Mazzanti & Andreani, JSSC 2008. 10
Colpitts oscillator
Transistors operate in Class C. Very efficient DC-to-RF current conversion
𝐼𝜔0 ≈ 𝐼𝑠𝑠𝑠𝑠
𝑉𝜔0 ≈ 1 − 𝑛 ∙ 𝑅 ∙ 𝐼𝑠𝑠𝑠𝑠
𝐿(∆𝜔) = 10𝑙𝑙𝑙2𝑘𝑑𝑇
𝑉𝜔02 2𝑅⁄
1 + γ1 − 𝑛𝑛
𝜔𝑜2𝑄∆𝜔
2
Andreani et al., JSSC 2005.
𝑛 =𝐶1
𝐶1 + 𝐶2 𝐶 =
12
𝐶1𝐶2𝐶1 + 𝐶2
+ 𝐶𝑉
11 𝑃𝑆 𝐹
Colpitts oscillator L=2nH, C=0.5pF, R=1kΩ, Ibias=2mA
Trade-off between F and Carrier Power (Ps).
With γ=2/3, nopt=0.3
Same result also for the Colpitts with Common-Drain transistors
Ps decreases F increases
12
Differential-Pair LC-Tank oscillator
𝐼𝜔0 ≈2𝜋𝐼𝑠𝑠𝑠𝑠
𝑉𝜔0 ≈2𝜋𝑅𝐼𝑠𝑠𝑠𝑠
𝐿(∆𝜔) = 10𝑙𝑙𝑙2𝑘𝑑𝑇
𝑉𝜔02 2𝑅⁄
1 + γ𝜔𝑜
2𝑄∆𝜔
2
𝑃𝑆 𝐹
Transistors operate in Class B.
Compared with Colpitts, poorer DC-to-RF current conversion efficiency, better noise factor (F).
For same Ibias and tank, phase noise ≈2dB better than Colpitts (Andreani et al., JSSC2005) 13
Differential-Pair LC-Tank oscillator: biasing
Significant contribution to phase noise from Mb:
thermal noise @ 2ω0 generates 1/f2 phase noise, (≈30% of the total)
1/f noise up-converted to 1/f3 phase noise
cpar + core devices in triode large contribution of core devices to phase noise.
Mb can be replaced by (programmable) resistors but need more voltage headroom penalty on maximum voltage swing.
14
Diff.-Pair LC-Tank osc. + Noise Filter
Lf resonates with cpar at 2ω0
Very large Cb to behave as a short circuit
Cb shorts to ground high freq. noise of Mb
Cb may absorb drain parasitic of Mb: large W and non-minimum L to limit 1/f noise
Popular technique. Could be applied to other oscillator topologies
Drawbacks: area (additional inductor and large cap), narrow – band.
15
Hegazi et al., JSSC2001
Diff.-Pair LC-Tank osc. + Noise Filter
16
Hegazi et al., JSSC2001 0.35µmCMOS
1.2GHz, 3.7mA from 2.5V Lf 10nH, Cb =40pF
7dB phase noise difference w. / w.o. filter Record FoM of 196 dBc/Hz Measurements vs. T.R. not reported
Modified Colpitts oscillator
17
𝐿(∆𝜔) = 10𝑙𝑙𝑙2𝑘𝑑𝑇
𝑉𝜔02 2𝑅⁄
1 + γ1 − 𝑛𝒌 + 𝑛
𝜔𝑜2𝑄∆𝜔
2
Additional feedback from drain to gate breaks the trade-off of the Colpitts oscillator. Optimum performance now with n=0. (Mazzanti & Andreani, JSSC 2008)
Evolution toward the Class-C oscillator
18
𝐿(∆𝜔) = 10𝑙𝑙𝑙2𝑘𝑑𝑇
𝑉𝜔02 2𝑅⁄
1 +γ𝒌
𝜔𝑜2𝑄∆𝜔
2
k=1 same effective MOS noise as in diff. pair LC oscillator
Not really Colpitts any more Class-C oscillator
High current conversion efficiency thanks to transistors working in Class-C
𝐼𝜔0 ≈ 𝐼𝑠𝑠𝑠𝑠; 𝑉𝜔0≈ 𝑅𝐼𝑠𝑠𝑠𝑠
For same Ibias and tank, ideally 3.9dB better phase noise than diff. pair. LC-Tank osc.
Final Class-C oscillator
19
MOS must not leave saturation Shift of MOS DC gate voltage necessary RC bias should not load tank k=1 Ctail filters also noise of the current source Large biasing MOS with L>Lmin (Cpar absorbed by
Ctail) low 1/f noise
Ripple on C2 is very small, and MOS current waveforms do not overlap
We may join the sources of the two MOS Large Ctail to keep transistors working in
Class-C (pulsed drain current)
Alternative Class-C oscillator design
20
Transformer primary for tank inductor Secondary easy DC shift Voltage (not power) feedback secondary
may be quite lossy If k>1 lower transistors effective noise
Importance of MOS in saturation
21
Why this huge phase noise deterioration?
MOS in deep triode
MOS in sat.
Tank current with MOS in triode
22
• No Class-C any more Current conversion efficiency is lost
π 2π 3π ω0t2 Φ
biasI≈
π 2π 3π ω0t
0.0
1.0
2.0
3.0
0.0
1.0
2.0 bias0 62 I.≈ ⋅
0
0
0Iω
0Iω
active MOS
triode MOS
drain biasI I
MOS2IMOS1I
• 4.2 dB of phase noise penalty due to loss of conversion efficiency • The wider current conduction angle rises also the Effective Noise
Effective noise with MOS in triode
23 -10.0
-8.0
-6.0
-4.0
-2.0
0.0
2.0
4.0
π/2 π 3π/2 2π0
,n MOSiΓ ⋅
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
π/2 π 3π/2 2π0
active MOS
triode MOS
Γ
, 1.4eff RN → ×
, 5eff MOSN → ×
MOS triode:
• 8.2 dB of total phase noise penalty
• 4 dB of phase noise penalty due to higher Effective Noise
Figure of Merit
24
Maximum amplitude to avoid MOS in triode 𝑉𝜔0_𝑚𝑠𝑚 < 2𝑉𝐷𝐷 − 𝑉𝑠𝑠𝑠𝑠 + 𝑉𝑇𝑇
1 + 𝑘
k=1, Vbias≈ Vth 𝑉𝜔0_𝑚𝑠𝑚 ≈ 𝑉𝐷𝐷
𝐹𝑙𝐹𝐷𝑡𝑠𝑠𝑠−𝐷 = −10𝑙𝑙𝑙 103 𝑘𝑑 𝑇 𝑄2
(1 + 𝛾)
𝑃𝑠_𝑚𝑠𝑚=𝑉𝜔0_𝑚𝑡𝑚∙𝐼𝜔0
2=𝑉𝐷𝐷∙𝐼𝑏𝑡𝑡𝑡
2= 𝑃𝐷𝐷
2 η=50%
Assuming Q= 15, FoMClass-C = 195dBc/Hz
Class-C VCO design
25
• VDD= 1V, Ibias=1.4 mA • 6M (Cu) + AluCap 0.13 µm CMOS
process • 2.0 nH inductor, A-MOS varactors,
tank-Q ≈ 16 • FOM 193.5 – 195.5 dBc/Hz
Class-C VCO design with transformer
26
• VDD= 1.1V, Ibias=1.3 mA • Same footprint as single coil • Lp = 2.0 nH, Ls = 4.4 nH, M = 2.5 nH • FOM 193.8 – 196 dBc/Hz
Measurements with MOS in triode
27
Phase noise penalty only if transistors enter deeply into the triode region
Push Pull Class-C oscillator
28
RC bias + level shifter (M5) to have larger swing without M3-M4 in triode
Compared with nMOS-only Class-C: Voltage swing within the supply Larger loop gain: gm=gmn+gmp
Double voltage swing for same tank and Ibias: 𝑉𝜔0 ≈ 2𝑅𝐼𝑠𝑠𝑠𝑠
6dB lower phase noise for same tank and Ibias
Half the maximum allowed voltage swing
Same peak FoM with optimum design Mazzanti & Andreani, JSSC 2013
Push-Pull Class-C design
29
0.18µm CMOS. 1.2mA from 1.8V 1nH inductor, AMOS varactors. Tank-Q≈9-10 6.09-7.5GHz in 16 sub-bands 189-191 dBc/Hz Phase Noise FoM Theoretical peak FoM, with Q=10 is 191.5dBc/Hz
30
Outline
Phase Noise - LTI vs LTV models - Comparison between Colpitts and LC-Tank oscillators - The Class-C oscillator
Frequency Tuning - Capacitors tuning and design trade-offs - Issues at mmWaves - Wide tuning range 40GHz VCO in 32nm CMOS
31
Frequency tuning with capacitors
Low tuning gain desirable • Fine tuning with a small varactor • Coarse steps with digitally switched caps
More than one octave T.R. possible at RF
Several research attempts to alternative tuning methods (sw. inductors, sw. transformers, magnetic tuning…) but problematic (complexity, phase noise penalty, area)
𝑇.𝑅. =∆𝑓𝑓≈
12∆𝐶𝐶
Mostly adopted frequency tuning technique
32
Switched capacitor design
on
off 𝑐𝑠𝑠 ∝ 𝑊 𝑟𝑠𝑠 ∝ 𝐿/𝑊
L Maximum Q with L=Lmin
W trade-off between Q and csw (T.R.)
33
Issues at wide Tuning Range
rs,L rs,C
𝑄𝐿 =𝜔𝐿𝑟𝑠,𝐿
𝑄𝐷 =1
𝜔𝐶𝑟𝑠,𝐷
𝑄 =𝑄𝐿𝑄𝐷𝑄𝐿 +𝑄𝐷
𝑅 = 𝜔0𝐿𝑄
Inductor losses dominates the tank Q at RF (QL=10-20, QC > 40)
Wide T.R. large variation of R & Q : 𝜔0 → 2𝜔0
𝑄 → 1.5 ÷ 2 𝑄 R → 3 ÷ 4 𝑅
Large Phase Noise / Power variation
Difficult to have optimized performance over the full band
Calibrations/ALC required
34
Design example
0.18µm CMOS 1.14 – 2.56 GHz
FOM variation w.o. cal. 12dB
FOM variation w. cal. 3dB
Berny et al., JSSC 2005
35
LC-Tank at mmWaves
J.Long et al. CICC-2010 Skin effect and substrate loss limit QL to 20-30
Varactors Cmax/Cmin ≈ 2, Qmin ≈ 5. Similar performance of MOM+MOS switch
Q of the Tank 3÷5 , limited by capacitors Low tank impedance ( loop gain)
Compared to RF, huge Phase Noise penalty and severe trade-off with T.R.
Inductors @ 60GHz Varactors @ 60GHz
05
101520253035
20 30 40 50 60
Tunin
g Ran
ge [%
]
Center frequency [GHz]
36
mmWave VCOs
Tuning Range reduces dramatically
Phase Noise FoM 10-15dB lower than at RF
Achieving state of the art FoM and wide T.R. is challenging
Improvement with technology scaling?
37
0.13 um 6 layers
IEDM 2010, S. Francisco
Continuous scaling driven by complex Systems on Chip
~ 20-30% fT improvement only per generation
aggressive scaling of BEOL: • large impact of routing parasitic (layout) • passive components penalty
CMOS 65nm vs 32nm: BEOL
38
• 32nm H.L.M closer to
substrate (~85%) but same thickness
• 32nm L.L.M. closer to
substrate and thinner (~50% )
• 2x resistivity of 32nm VIAs
CMOS65nm CMOS32nm
Low Level Metals
High Level Metals
Top Level Metal
Low Level Vias
High Level Vias
Performance of switches
39
1SW
M
rg
∝SW GSc C∝
1SW SW SW
T
FOM c rf
= ⋅ ∝
Switch On Switch Off
rSW csw
550
500
400
300
450
350
2030405060
FOM
[fs]
Gate Length [nm]70
600
650
post-layout
pre-layout
Considering post-layout, mild advantage beyond 45nm
40
30
10
20
0
Qua
lity
Fact
or
20 30 40 50 60Frequency [GHz]
CMOS32nm
CMOS65nm
C=250fF
30
20
10
0
Qua
lity
Fact
or
0 20 40 60 80Frequency [GHz]
CMOS32nm
CMOS65nm
L=100pH
65nm vs 32nm: Inductors & Capacitors
40
Slightly lower dielectric constant in 32nm compensates lower metal distance to substrate
MOM Q in 32nm ~70% than 65nm due to half thickness of LLM and 2x via resistance
Q of switched MOM
41
10
9
7
5
8
6
1.5 1.6 1.7 1.8 1.9 2.0
Quali
ty Fa
ctor
Cmax/Cmin
CMOS32nm
CMOS65nm
@40GHz
32nm switched MOM slightly worse than 65nm
Review of switched capacitor tuning
42
• CFIX: parasitic cap of buffer and core devices
• CFIX equal or greater than CT at mmWave
( )
12π
=+
MINT FIX T
fL C C
1 12
2π
π
<<= →
+ +
,SW T FIXMAX
T FIXT SWT FIX
T SW
c C CfL CC cL C
C c
• SW OFF: fMAX determined by CFIX
• SW ON:
-rCFIX
CT LT
csw
Proposed switched capacitor tuning
43
• cSW in series with CT+CFIX
• Much higher frequency jump
( )1 1
22
ππ
<<= →+
+ +
,SW T FIXMAX
T SWT FIX SWT
T FIX SW
c C CfL cC C c
LC C c
-rCFIX CT
LT
csw
• SW OFF: CFIX no more limiting fMAX
• SW ON: fMIN as in switched cap. oscillator
Mammei et al., ISSCC 2013
Comparison with same frequency jump
44
rSW=11Ω, Q=8 rSW=1.37Ω, Q=16
rSWrSW
-rCFIX
CT LT
-rCFIX CT
LT
Assuming: CFIX=CT=100fF, LT=100pH, FOMSW=550fs fMIN=35.6GHz, fMAX/fMIN=1.2
-rCFIX
CT LT
-rCFIX CT
LT
csw csw
Wsw=41µm, cSW=50fF Wsw=330µm,cSW=400fF
Switch off
Switch on
Q vs fmax/fmin with finite components Q
45
Advantage increase for higher frequency step and/or larger Cfix
Traditional switched capacitor
Proposed tank
VCO Design
46
Inductor splitting with MSW for the largest tuning step
Variable tank capacitance (CT) with switched digital MOMs and varactor
LT=100pH, CT=140fF, CFIX≈120fF
Tank Q ranges from 4 to 5.5
Transformer feedback avoids latching when MSW is off
Rb instead of current mirrors lowers 1/f noise
Test Chip
47
CMOS 32nm LP from
STMicroelectronics Core Area 70um x 120um 40GHz center frequency
Phase Noise measured
after divider by 4 in X-Band (8-12GHz)
9.8mW from 1V supply
Phase Noise & FoM over Tuning Range
48
10 MHz offset
Summary and Comparison
49
REF FREQ [GHz]
TR [%]
POWER [mW]
PN @10MHz [dBc/Hz]
FOM [dBc/Hz] TECH
CICC12 57.5/90.1 44.2 8.4/10.8 -104.6/-112.2 172/180 65nm
RFIC11 11.5/22 59 20/29 -107/-127* 158.6/177.4 130nm
RFIC10 34.3/39.9 15 14.4 -118/-121* 178.4/180.1 65nm
JSSCC11 43.2/51.8 22.9 16 -117/-119* 179/180 65nm
ISSCC11 21.7/27.8 24.8 12.2 -121 177.5 45nm
This Work 33.6/46.2 31.6 9.8 -115.2/-118 177.5/180 32nm * estimated from the reported phase noise at 1MHz
Conclusions
50
Noise to phase noise conversion is a LTV process
Phase Noise FoM may be increased by improving power efficiency and noise factor
Class-C oscillator exploits high current efficiency of Colpitts and low noise factor of differential pair LC-Tank oscillator
High tuning range possible at RF with switched tank capacitors. Need amplitude control / calibrations to compensate large variation of tank impedance
At mmWave, low tank Q, limited by capacitor. Severe trade-off between T.R. and phase noise.
Proposed a switched tank capacitor topology enabling large T.R. with state of the art FoM.
References
51
D.B.Leeson, "A Simple Model of Oscillator Noise Spectrum“, Proc. IEEE, vol. 54, no.2, Feb. 1966. A.Hajimiri, T.H.Lee, "A General Theory of Phase Noise in Electrical Oscillators“, IEEE
J. of Solid State Circuits, vol.33, no.2, Feb. 1998. A.Hajimiri, T.H.Lee, "Oscillator Phase Noise: A Tutorial“, IEEE J. of Solid State
Circuits, vol.35, no.3, March 2000. P.Andreani, et al., "A Study of Phase Noise in Colpitts and LC-Tank CMOS
Oscillators", IEEE J. of Solid State Circuits, vol.40, no.5, May 2005. P.Andreani, A.Fard, "More on the 1=f2 Phase Noise Performance of CMOS
Differential-Pair LC-Tank Oscillators", IEEE J. of Solid State Circuits, vol.41, no.12, Dec. 2006. E. Hegazi et al., "A Filtering Technique to Lower LC Oscillator Phase Noise“, IEEE J.
of Solid State Circuits, vol.36, no.12, Dec. 2001. A.Mazzanti, P.Andreani, "Class C Harmonic CMOS VCOs, with a General Result on
Phase Noise”, IEEE J. of Solid State Circuits, vol.43, no.12, Dec. 2008. A.Mazzanti, P.Andreani "A Push–Pull Class-C CMOS VCO", IEEE J. of Solid State
Circuits, vol.48, no.3, March 2008.
References
52
A.D.Berni et al., “A 1.8-GHz LC-VCO With 1.3-GHz Tuning Range and Digital Amplitude Calibration”, IEEE J. of Solid State Circuits, vol.40, no.4, April 2005. H. Sjöland, "Improved Switched Tuning of Differential CMOS VCOs", IEEE T. on Circ.
and Systems-II, vol 49, no.5, May 2002. B.Sadhu, R.Harjani, "Capacitor Bank Design for Wide Tuning Range LC VCOs:
850MHz−7.1GHz (157%) ", Proc. ISCAS 2010. S.Dal Toso et al., "A Thorough Analysis of the Tank Quality Factor in LC Oscillators
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