GROUP: 17NAME:SHAUN PRAKASH (1061107216)JAI PRAKASH (1061105253)RAJENDRAN (1061105607)

Integrated VLSI SystemsEEN4196

Title: 4-bit Parallel Full Adder

CONTENTS

Introduction Design Methodology Schematic Diagram Simulated Result Layout Conclusion

INTRODUCTION

4-bit Parallel Full Adder

INTRODUCTION

4-bit Parallel Full Adder Binary Addition and Operation

DESIGN METHODOLOGY

TRANSISTOR SIZING

In our full adder design, we are using the 0.35 µm CMOS technology. So the length of the transistor we fixed to 0.35 µm.

 L = 0.35 µm

 The default ratio of W to L

W/L = 3 

So, we design the width of the NMOS 2.5 times its length 

WN = 0.35 µm x 3 = 1.05 µm 

As the width of the PMOS is 2 times the width of NMOS, hence 

WP = 1.05 µm x 2 = 2.1 µm 

SCHEMATIC DIAGRAM

Schematic Diagram of Full Adder

SCHEMATIC DIAGRAM

Schematic Diagram of 4-bit Parallel Full Adder

SIMULATION RESULT

Output for First Block

SIMULATION RESULT

Output for Second Block

SIMULATED RESULT

Output for Third Block

SIMULATED RESULT

Output for Fourth Block

SIMULATED RESULT

Power Dissipation

•As temperature increases, power dissipation increases

Temperature, oC Power Dissipation, W

0 3.7083m

27 5.0536m

95 12.081m

SIMULATED RESULT

Propagation Delay

Proportional As the temperature increases, the

propagation delay increases Due to degradation of carrier mobilities when the temperature is increased.

Temperature

(°C)

Rising edge delay

(ps)

Falling edge delay

(ps)

0 -13.232 -4.3647

95 27.8300 10.8075

LAYOUT

Layout of One Full-Adder Block

LAYOUT TECHNIQUE

Same transistor types are grouped together less complex design.

To reduce the total size occupied. reduce power consumption.

The rule of thumb technique reduce the collision between metal routings and to reduce the complexity during top-level design.

CONCLUSION

Transistor count: 112 (28 per full adder circuit)

Layout area: 163.4µm x 227.1µm Power dissipation (27 oC): 5.0536mW

CONCLUSION

In conclusion, the schematic designed in this project is acceptable, at which the performance and delay is under reasonable range. The design can be considered as successful, due to the adequate precision and low power consumption. Future improvement on the current design is possible to achieve higher performance.