Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)DatasheetJune 2012

Order Number: 326776-003

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Contents1 Introduction ............................................................................................................ 43 1.1 About This Manual ............................................................................................. 43 1.2 Overview ......................................................................................................... 46 1.2.1 Capability Overview ................................................................................ 47 1.3 Intel 7 Series / C216 Chipset Family SKU Definition ............................................. 54 Signal Description ................................................................................................... 57 2.1 Direct Media Interface (DMI) to Host Controller ..................................................... 59 2.2 PCI Express* .................................................................................................... 59 2.3 PCI Interface .................................................................................................... 60 2.4 Serial ATA Interface........................................................................................... 63 2.5 LPC Interface.................................................................................................... 66 2.6 Interrupt Interface ............................................................................................ 66 2.7 USB Interface ................................................................................................... 67 2.8 Power Management Interface.............................................................................. 69 2.9 Processor Interface............................................................................................ 73 2.10 SMBus Interface................................................................................................ 73 2.11 System Management Interface............................................................................ 74 2.12 Real Time Clock Interface ................................................................................... 74 2.13 Miscellaneous Signals ........................................................................................ 75 2.14 Intel High Definition Audio Link ......................................................................... 76 2.15 Controller Link .................................................................................................. 77 2.16 Serial Peripheral Interface (SPI) .......................................................................... 77 2.17 Thermal Signals ................................................................................................ 78 2.18 Testability Signals ............................................................................................. 78 2.19 Clock Signals .................................................................................................... 79 2.20 LVDS Signals .................................................................................................... 81 2.21 Analog Display /VGA DAC Signals ........................................................................ 82 2.22 Intel Flexible Display Interface (Intel FDI) ........................................................ 82 2.23 Digital Display Signals........................................................................................ 83 2.24 General Purpose I/O Signals ............................................................................... 85 2.25 Manageability Signals ........................................................................................ 90 2.26 Power and Ground Signals .................................................................................. 90 2.27 Pin Straps ........................................................................................................ 93 2.28 External RTC Circuitry ........................................................................................ 97 PCH Pin States......................................................................................................... 99 3.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 99 3.2 Output and I/O Signals Planes and States........................................................... 101 3.3 Power Planes for Input Signals .......................................................................... 113 PCH and System Clocks ......................................................................................... 119 4.1 Platform Clocking Requirements ........................................................................ 119 4.2 Functional Blocks ............................................................................................ 122 4.3 Clock Configuration Access Overview ................................................................. 123 4.4 Straps Related to Clock Configuration ................................................................ 123 Functional Description ........................................................................................... 125 5.1 PCI-to-PCI Bridge (D30:F0) .............................................................................. 125 5.1.1 PCI Bus Interface ................................................................................. 125 5.1.2 PCI Bridge As an Initiator ...................................................................... 126 5.1.2.1 Memory Reads and Writes........................................................ 126 5.1.2.2 I/O Reads and Writes .............................................................. 126 5.1.2.3 Configuration Reads and Writes ................................................ 126 5.1.2.4 Locked Cycles ........................................................................ 126 5.1.2.5 Target / Master Aborts............................................................. 126 5.1.2.6 Secondary Master Latency Timer............................................... 126 5.1.2.7 Dual Address Cycle (DAC) ........................................................ 127 5.1.2.8 Memory and I/O Decode to PCI................................................. 127 5.1.3 Parity Error Detection and Generation ..................................................... 127 5.1.4 PCIRST# ............................................................................................. 128 5.1.5 Peer Cycles ......................................................................................... 128

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5.2

5.3

5.4

5.5

5.6

5.7

5.1.6 PCI-to-PCI Bridge Model ........................................................................ 128 5.1.7 IDSEL to Device Number Mapping ........................................................... 129 5.1.8 Standard PCI Bus Configuration Mechanism.............................................. 129 5.1.9 PCI Legacy Mode .................................................................................. 129 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) ..................................... 129 5.2.1 Interrupt Generation ............................................................................. 130 5.2.2 Power Management............................................................................... 130 5.2.2.1 S3/S4/S5 Support ................................................................... 130 5.2.2.2 Resuming from Suspended State ............................................... 131 5.2.2.3 Device Initiated PM_PME Message ............................................. 131 5.2.2.4 SMI/SCI Generation................................................................. 131 5.2.3 SERR# Generation ................................................................................ 132 5.2.4 Hot-Plug .............................................................................................. 132 5.2.4.1 Presence Detection .................................................................. 132 5.2.4.2 Message Generation ................................................................ 132 5.2.4.3 Attention Button Detection ....................................................... 133 5.2.4.4 SMI/SCI Generation................................................................. 133 Gigabit Ethernet Controller (B0:D25:F0) ............................................................. 134 5.3.1 GbE PCI Express* Bus Interface.............................................................. 135 5.3.1.1 Transaction Layer.................................................................... 135 5.3.1.2 Data Alignment ....................................................................... 135 5.3.1.3 Configuration Request Retry Status ........................................... 136 5.3.2 Error Events and Error Reporting ............................................................ 136 5.3.2.1 Data Parity Error ..................................................................... 136 5.3.2.2 Completion with Unsuccessful Completion Status ......................... 136 5.3.3 Ethernet Interface ................................................................................ 136 5.3.3.1 82579 LAN PHY Interface ......................................................... 136 5.3.4 PCI Power Management ......................................................................... 137 5.3.4.1 Wake Up ................................................................................ 137 5.3.5 Configurable LEDs................................................................................. 139 5.3.6 Function Level Reset Support (FLR) ......................................................... 140 5.3.6.1 FLR Steps............................................................................... 140 LPC Bridge (with System and Management Functions) (D31:F0)............................. 140 5.4.1 LPC Interface ....................................................................................... 140 5.4.1.1 LPC Cycle Types ...................................................................... 141 5.4.1.2 Start Field Definition ................................................................ 142 5.4.1.3 Cycle Type / Direction (CYCTYPE + DIR)..................................... 142 5.4.1.4 Size....................................................................................... 142 5.4.1.5 SYNC..................................................................................... 143 5.4.1.6 SYNC Time-Out ....................................................................... 143 5.4.1.7 SYNC Error Indication .............................................................. 143 5.4.1.8 LFRAME# Usage...................................................................... 143 5.4.1.9 I/O Cycles .............................................................................. 144 5.4.1.10 Bus Master Cycles ................................................................... 144 5.4.1.11 LPC Power Management ........................................................... 144 5.4.1.12 Configuration and PCH Implications ........................................... 144 DMA Operation (D31:F0) .................................................................................. 145 5.5.1 Channel Priority.................................................................................... 145 5.5.1.1 Fixed Priority .......................................................................... 145 5.5.1.2 Rotating Priority ...................................................................... 146 5.5.2 Address Compatibility Mode ................................................................... 146 5.5.3 Summary of DMA Transfer Sizes ............................................................. 146 5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words 146 5.5.4 Autoinitialize ........................................................................................ 147 5.5.5 Software Commands ............................................................................. 147 LPC DMA ........................................................................................................ 147 5.6.1 Asserting DMA Requests ........................................................................ 147 5.6.2 Abandoning DMA Requests..................................................................... 148 5.6.3 General Flow of DMA Transfers ............................................................... 149 5.6.4 Terminal Count..................................................................................... 149 5.6.5 Verify Mode ......................................................................................... 149 5.6.6 DMA Request Deassertion ...................................................................... 149 5.6.7 SYNC Field / LDRQ# Rules ..................................................................... 150 8254 Timers (D31:F0) ...................................................................................... 151 5.7.1 Timer Programming .............................................................................. 151 5.7.2 Reading from the Interval Timer ............................................................. 152 5.7.2.1 Simple Read ........................................................................... 152

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5.8

5.9

5.10

5.11

5.12

5.13

5.7.2.2 Counter Latch Command.......................................................... 153 5.7.2.3 Read Back Command .............................................................. 153 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 154 5.8.1 Interrupt Handling................................................................................ 155 5.8.1.1 Generating Interrupts.............................................................. 155 5.8.1.2 Acknowledging Interrupts ........................................................ 155 5.8.1.3 Hardware/Software Interrupt Sequence ..................................... 156 5.8.2 Initialization Command Words (ICWx) ..................................................... 156 5.8.2.1 ICW1 .................................................................................... 156 5.8.2.2 ICW2 .................................................................................... 157 5.8.2.3 ICW3 .................................................................................... 157 5.8.2.4 ICW4 .................................................................................... 157 5.8.3 Operation Command Words (OCW) ......................................................... 157 5.8.4 Modes of Operation .............................................................................. 157 5.8.4.1 Fully Nested Mode................................................................... 157 5.8.4.2 Special Fully-Nested Mode........................................................ 158 5.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 158 5.8.4.4 Specific Rotation Mode (Specific Priority).................................... 158 5.8.4.5 Poll Mode............................................................................... 158 5.8.4.6 Edge and Level Triggered Mode ................................................ 159 5.8.4.7 End of Interrupt (EOI) Operations ............................................. 159 5.8.4.8 Normal End of Interrupt........................................................... 159 5.8.4.9 Automatic End of Interrupt Mode .............................................. 159 5.8.5 Masking Interrupts ............................................................................... 159 5.8.5.1 Masking on an Individual Interrupt Request................................ 159 5.8.5.2 Special Mask Mode.................................................................. 160 5.8.6 Steering PCI Interrupts ......................................................................... 160 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 160 5.9.1 Interrupt Handling................................................................................ 160 5.9.2 Interrupt Mapping ................................................................................ 161 5.9.3 PCI/PCI Express* Message-Based Interrupts ............................................ 162 5.9.4 IOxAPIC Address Remapping ................................................................. 162 5.9.5 External Interrupt Controller Support ...................................................... 162 Serial Interrupt (D31:F0) ................................................................................. 162 5.10.1 Start Frame......................................................................................... 163 5.10.2 Data Frames........................................................................................ 163 5.10.3 Stop Frame ......................................................................................... 163 5.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 164 5.10.5 Data Frame Format .............................................................................. 164 Real Time Clock (D31:F0)................................................................................. 165 5.11.1 Update Cycles...................................................................................... 165 5.11.2 Interrupts ........................................................................................... 166 5.11.3 Lockable RAM Ranges ........................................................................... 166 5.11.4 Century Rollover .................................................................................. 166 5.11.5 Clearing Battery-Backed RTC RAM .......................................................... 166 Processor Interface (D31:F0) ............................................................................ 168 5.12.1 Processor Interface Signals and VLW Messages ........................................ 168 5.12.1.1 INIT (Initialization) ................................................................. 168 5.12.1.2 FERR# (Numeric Coprocessor Error) .......................................... 169 5.12.1.3 NMI (Non-Maskable Interrupt) .................................................. 169 5.12.1.4 Processor Power Good (PROCPWRGD) ....................................... 169 5.12.2 Dual-Processor Issues........................................................................... 169 5.12.2.1 Usage Differences ................................................................... 169 5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 170 Power Management ......................................................................................... 170 5.13.1 Features ............................................................................................. 170 5.13.2 PCH and System Power States ............................................................... 171 5.13.3 System Power Planes ............................................................................ 173 5.13.4 SMI#/SCI Generation ........................................................................... 173 5.13.4.1 PCI Express* SCI.................................................................... 175 5.13.4.2 PCI Express* Hot-Plug............................................................. 175 5.13.5 C-States ............................................................................................. 176 5.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 176 5.13.6.1 Conditions for Checking the PCI Clock........................................ 176 5.13.6.2 Conditions for Maintaining the PCI Clock .................................... 176 5.13.6.3 Conditions for Stopping the PCI Clock ........................................ 176 5.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 177

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5.14

5.15

5.16

5.13.6.5 LPC Devices and CLKRUN# ....................................................... 177 5.13.7 Sleep States ........................................................................................ 177 5.13.7.1 Sleep State Overview............................................................... 177 5.13.7.2 Initiating Sleep State ............................................................... 177 5.13.7.3 Exiting Sleep States................................................................. 178 5.13.7.4 PCI Express* WAKE# Signal and PME Event Message ................... 180 5.13.7.5 Sx-G3-Sx, Handling Power Failures ............................................ 180 5.13.7.6 Deep Sx................................................................................. 181 5.13.8 Event Input Signals and Their Usage ....................................................... 182 5.13.8.1 PWRBTN# (Power Button) ........................................................ 182 5.13.8.2 RI# (Ring Indicator) ................................................................ 184 5.13.8.3 PME# (PCI Power Management Event) ....................................... 184 5.13.8.4 SYS_RESET# Signal ................................................................ 184 5.13.8.5 THRMTRIP# Signal .................................................................. 184 5.13.9 ALT Access Mode .................................................................................. 185 5.13.9.1 Write Only Registers with Read Paths in ALT Access Mode............. 186 5.13.9.2 PIC Reserved Bits.................................................................... 188 5.13.9.3 Read Only Registers with Write Paths in ALT Access Mode............. 188 5.13.10System Power Supplies, Planes, and Signals............................................. 188 5.13.10.1Power Plane Control with SLP_S3#, SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#............................... 188 5.13.10.2SLP_S4# and Suspend-To-RAM Sequencing ................................ 189 5.13.10.3PWROK Signal ........................................................................ 189 5.13.10.4BATLOW# (Battery Low) (Mobile Only)....................................... 189 5.13.10.5SLP_LAN# Pin Behavior............................................................ 190 5.13.10.6RTCRST# and SRTCRST# ......................................................... 190 5.13.10.7SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior ...................... 191 5.13.11Legacy Power Management Theory of Operation ....................................... 191 5.13.11.1APM Power Management (Desktop Only) .................................... 191 5.13.11.2Mobile APM Power Management (Mobile Only) ............................. 192 5.13.12Reset Behavior ..................................................................................... 192 System Management (D31:F0) .......................................................................... 194 5.14.1 Theory of Operation .............................................................................. 194 5.14.1.1 Detecting a System Lockup....................................................... 194 5.14.1.2 Handling an Intruder ............................................................... 194 5.14.1.3 Detecting Improper Flash Programming...................................... 195 5.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus.................... 195 5.14.2 TCO Modes .......................................................................................... 196 5.14.2.1 TCO Legacy/Compatible Mode ................................................... 196 5.14.2.2 Advanced TCO Mode ................................................................ 197 General Purpose I/O (D31:F0) ........................................................................... 198 5.15.1 Power Wells ......................................................................................... 198 5.15.2 SMI# SCI and NMI Routing .................................................................... 198 5.15.3 Triggering............................................................................................ 198 5.15.4 GPIO Registers Lockdown ...................................................................... 198 5.15.5 Serial POST Codes over GPIO ................................................................. 199 5.15.5.1 Theory of Operation................................................................. 199 5.15.5.2 Serial Message Format ............................................................. 200 SATA Host Controller (D31:F2, F5)..................................................................... 201 5.16.1 SATA 6 Gb/s Support ............................................................................ 202 5.16.2 SATA Feature Support ........................................................................... 202 5.16.3 Theory of Operation .............................................................................. 203 5.16.3.1 Standard ATA Emulation........................................................... 203 5.16.3.2 48-Bit LBA Operation ............................................................... 203 5.16.4 SATA Swap Bay Support ........................................................................ 203 5.16.5 Hot Plug Operation................................................................................ 203 5.16.6 Function Level Reset Support (FLR) ......................................................... 204 5.16.6.1 FLR Steps............................................................................... 204 5.16.7 Intel Rapid Storage Technology Configuration......................................... 204 5.16.7.1 Intel Rapid Storage Technology RAID Option ROM ..................... 205 5.16.8 Intel Smart Response Technology ......................................................... 205 5.16.9 Power Management Operation ................................................................ 206 5.16.9.1 Power State Mappings.............................................................. 206 5.16.9.2 Power State Transitions............................................................ 206 5.16.9.3 SMI Trapping (APM)................................................................. 207 5.16.10SATA Device Presence ........................................................................... 207 5.16.11SATA LED ............................................................................................ 208

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5.18

5.19 5.20 5.21

5.22

5.16.12AHCI Operation.................................................................................... 208 5.16.13SGPIO Signals ..................................................................................... 209 5.16.13.1Mechanism ............................................................................ 209 5.16.13.2Message Format ..................................................................... 210 5.16.13.3LED Message Type .................................................................. 210 5.16.13.4SGPIO Waveform .................................................................... 212 5.16.14External SATA...................................................................................... 213 High Precision Event Timers.............................................................................. 213 5.17.1 Timer Accuracy .................................................................................... 213 5.17.2 Interrupt Mapping ................................................................................ 214 5.17.3 Periodic vs. Non-Periodic Modes ............................................................. 214 5.17.4 Enabling the Timers.............................................................................. 215 5.17.5 Interrupt Levels ................................................................................... 215 5.17.6 Handling Interrupts .............................................................................. 216 5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors .............................. 216 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 217 5.18.1 EHC Initialization.................................................................................. 217 5.18.1.1 BIOS Initialization ................................................................... 217 5.18.1.2 Driver Initialization ................................................................. 217 5.18.1.3 EHC Resets ............................................................................ 217 5.18.2 Data Structures in Main Memory............................................................. 217 5.18.3 USB 2.0 Enhanced Host Controller DMA................................................... 218 5.18.4 Data Encoding and Bit Stuffing ............................................................... 218 5.18.5 Packet Formats .................................................................................... 218 5.18.6 USB 2.0 Interrupts and Error Conditions .................................................. 218 5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ................................ 219 5.18.7 USB 2.0 Power Management .................................................................. 219 5.18.7.1 Pause Feature ........................................................................ 219 5.18.7.2 Suspend Feature..................................................................... 219 5.18.7.3 ACPI Device States ................................................................. 219 5.18.7.4 ACPI System States ................................................................ 220 5.18.8 USB 2.0 Legacy Keyboard Operation ....................................................... 220 5.18.9 USB 2.0 Based Debug Port .................................................................... 220 5.18.9.1 Theory of Operation ............................................................... 221 5.18.10EHCI Caching....................................................................................... 225 5.18.11Intel USB Pre-Fetch Based Pause ......................................................... 225 5.18.12Function Level Reset Support (FLR) ........................................................ 225 5.18.12.1FLR Steps .............................................................................. 225 5.18.13USB Overcurrent Protection ................................................................... 226 Integrated USB 2.0 Rate Matching Hub .............................................................. 227 5.19.1 Overview ............................................................................................ 227 5.19.2 Architecture......................................................................................... 227 xHCI Controller (D20:F0) ................................................................................. 227 SMBus Controller (D31:F3) ............................................................................... 228 5.21.1 Host Controller..................................................................................... 228 5.21.1.1 Command Protocols ................................................................ 229 5.21.2 Bus Arbitration..................................................................................... 232 5.21.3 Bus Timing .......................................................................................... 233 5.21.3.1 Clock Stretching ..................................................................... 233 5.21.3.2 Bus Time Out (The PCH as SMBus Master) ................................. 233 5.21.4 Interrupts / SMI#................................................................................. 233 5.21.5 SMBALERT# ........................................................................................ 234 5.21.6 SMBus CRC Generation and Checking...................................................... 234 5.21.7 SMBus Slave Interface .......................................................................... 235 5.21.7.1 Format of Slave Write Cycle ..................................................... 236 5.21.7.2 Format of Read Command........................................................ 237 5.21.7.3 Slave Read of RTC Time Bytes .................................................. 239 5.21.7.4 Format of Host Notify Command ............................................... 240 Thermal Management ...................................................................................... 241 5.22.1 Thermal Sensor ................................................................................... 241 5.22.1.1 Internal Thermal Sensor Operation............................................ 241 5.22.2 PCH Thermal Throttling ......................................................................... 242 5.22.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) .... 243 5.22.3.1 Supported Addresses............................................................... 244 5.22.3.2 I2C Write Commands to the Intel ME ....................................... 245 5.22.3.3 Block Read Command.............................................................. 245 5.22.3.4 Read Data Format................................................................... 247

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5.23

5.24 5.25

5.26 5.27 5.28

5.29

5.22.3.5 Thermal Data Update Rate........................................................ 247 5.22.3.6 Temperature Comparator and Alert............................................ 247 5.22.3.7 BIOS Set Up ........................................................................... 249 5.22.3.8 SMBus Rules........................................................................... 249 5.22.3.9 Case for Considerations............................................................ 250 Intel High Definition Audio Overview (D27:F0)................................................... 252 5.23.1 Intel High Definition Audio Docking (Mobile Only).................................... 252 5.23.1.1 Dock Sequence ....................................................................... 252 5.23.1.2 Exiting D3/CRST# When Docked ............................................... 253 5.23.1.3 Cold Boot/Resume from S3 When Docked................................... 254 5.23.1.4 Undock Sequence.................................................................... 254 5.23.1.5 Normal Undock ....................................................................... 254 5.23.1.6 Surprise Undock...................................................................... 255 5.23.1.7 Interaction between Dock/Undock and Power Management States . 255 5.23.1.8 Relationship between HDA_DOCK_RST# and HDA_RST# .............. 255 Intel ME and Intel ME Firmware 8.0 ............................................................... 256 5.24.1 Intel ME Requirements ........................................................................ 257 Serial Peripheral Interface (SPI) ........................................................................ 258 5.25.1 SPI Supported Feature Overview ............................................................ 258 5.25.1.1 Non-Descriptor Mode ............................................................... 258 5.25.1.2 Descriptor Mode ...................................................................... 258 5.25.2 Flash Descriptor ................................................................................... 259 5.25.2.1 Descriptor Master Region ......................................................... 261 5.25.3 Flash Access ........................................................................................ 262 5.25.3.1 Direct Access Security.............................................................. 262 5.25.3.2 Register Access Security .......................................................... 262 5.25.4 Serial Flash Device Compatibility Requirements ........................................ 263 5.25.4.1 PCH SPI Based BIOS Requirements............................................ 263 5.25.4.2 Integrated LAN Firmware SPI Flash Requirements........................ 263 5.25.4.3 Intel Management Engine Firmware SPI Flash Requirements ....... 263 5.25.4.4 Hardware Sequencing Requirements .......................................... 264 5.25.5 Multiple Page Write Usage Model............................................................. 265 5.25.5.1 Soft Flash Protection................................................................ 265 5.25.5.2 BIOS Range Write Protection .................................................... 266 5.25.5.3 SMI# Based Global Write Protection........................................... 266 5.25.6 Flash Device Configurations ................................................................... 266 5.25.7 SPI Flash Device Recommended Pinout.................................................... 266 5.25.8 Serial Flash Device Package ................................................................... 267 5.25.8.1 Common Footprint Usage Model ................................................ 267 5.25.8.2 Serial Flash Device Package Recommendations ........................... 267 Fan Speed Control Signals (Server/Workstation Only)........................................... 268 5.26.1 PWM Outputs (Server/Workstation Only) ................................................. 268 5.26.2 TACH Inputs (Server/Workstation Only)................................................... 268 Feature Capability Mechanism ........................................................................... 268 PCH Display Interfaces and Intel Flexible Display Interconnect............................. 269 5.28.1 Analog Display Interface Characteristics................................................... 270 5.28.1.1 Integrated RAMDAC................................................................. 270 5.28.1.2 DDC (Display Data Channel) ..................................................... 271 5.28.2 Digital Display Interfaces ....................................................................... 271 5.28.2.1 LVDS (Mobile only) .................................................................. 271 5.28.2.2 High Definition Multimedia Interface .......................................... 273 5.28.2.3 Digital Video Interface* (DVI*) ................................................. 274 5.28.2.4 DisplayPort* ........................................................................... 275 5.28.2.5 Embedded DisplayPort* ........................................................... 275 5.28.2.6 DisplayPort* Aux Channel......................................................... 275 5.28.2.7 DisplayPort* Hot-Plug Detect (HPD) ........................................... 276 5.28.2.8 Integrated Audio over HDMI and DisplayPort* ............................. 276 5.28.2.9 Intel Serial Digital Video Out (Intel SDVO).............................. 276 5.28.3 Mapping of Digital Display Interface Signals ............................................. 277 5.28.4 Multiple Display Configurations ............................................................... 279 5.28.5 High-bandwidth Digital Content Protection* (HDCP*)................................. 281 5.28.6 Intel Flexible Display Interconnect ........................................................ 281 Intel Virtualization Technology ........................................................................ 281 5.29.1 Intel VT-d Objectives .......................................................................... 282 5.29.2 Intel VT-d Features Supported.............................................................. 282 5.29.3 Support for Function Level Reset (FLR) in PCH .......................................... 282 5.29.4 Virtualization Support for PCHs IOxAPIC.................................................. 282

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5.29.5 Virtualization Support for High Precision Event Timer (HPET)...................... 283 6 Ballout Definition................................................................................................... 285 6.1 Desktop PCH Ballout ........................................................................................ 285 6.2 Mobile PCH Ballout .......................................................................................... 297 6.3 Mobile SFF PCH Ballout .................................................................................... 309 Package Information ............................................................................................. 323 7.1 Desktop PCH package ...................................................................................... 323 7.2 Mobile PCH Package......................................................................................... 325 7.3 Mobile SFF PCH Package................................................................................... 327 Electrical Characteristics ....................................................................................... 329 8.1 Thermal Specifications ..................................................................................... 329 8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............... 329 8.1.2 Mobile Storage Specifications and Thermal Design Power (TDP) .................. 329 8.2 Absolute Maximum Ratings............................................................................... 330 8.3 PCH Power Supply Range ................................................................................. 331 8.4 General DC Characteristics ............................................................................... 331 8.5 Display DC Characteristics ................................................................................ 344 8.6 AC Characteristics ........................................................................................... 346 8.7 Power Sequencing and Reset Signal Timings ....................................................... 362 8.8 Power Management Timing Diagrams................................................................. 365 8.9 AC Timing Diagrams ........................................................................................ 370 Register and Memory Mapping............................................................................... 381 9.1 PCI Devices and Functions................................................................................ 382 9.2 PCI Configuration Map ..................................................................................... 383 9.3 I/O Map ......................................................................................................... 383 9.3.1 Fixed I/O Address Ranges ..................................................................... 383 9.3.2 Variable I/O Decode Ranges .................................................................. 386 9.4 Memory Map................................................................................................... 387 9.4.1 Boot-Block Update Scheme.................................................................... 389 Chipset Configuration Registers............................................................................. 391 10.1 Chipset Configuration Registers (Memory Space) ................................................. 391 10.1.1 RPCRoot Port Configuration Register .................................................... 393 10.1.2 RPFNRoot Port Function Number and Hide for PCI Express* Root Ports Register ................................................................. 394 10.1.3 FLRSTATFunction Level Reset Pending Status Register ............................ 395 10.1.4 TRSRTrap Status Register ................................................................... 396 10.1.5 TRCRTrapped Cycle Register ............................................................... 396 10.1.6 TWDRTrapped Write Data Register....................................................... 397 10.1.7 IOTRnI/O Trap Register (03) ............................................................. 397 10.1.8 V0CTLVirtual Channel 0 Resource Control Register ................................. 398 10.1.9 V0STSVirtual Channel 0 Resource Status Register .................................. 398 10.1.10V1CTLVirtual Channel 1 Resource Control Register ................................. 399 10.1.11V1STSVirtual Channel 1 Resource Status Register .................................. 399 10.1.12RECRoot Error Command Register ....................................................... 399 10.1.13LCAPLink Capabilities Register ............................................................. 400 10.1.14LCTLLink Control Register ................................................................... 400 10.1.15LSTSLink Status Register .................................................................... 401 10.1.16TCTLTCO Configuration Register .......................................................... 401 10.1.17D31IPDevice 31 Interrupt Pin Register.................................................. 402 10.1.18D30IPDevice 30 Interrupt Pin Register.................................................. 403 10.1.19D29IPDevice 29 Interrupt Pin Register.................................................. 403 10.1.20D28IPDevice 28 Interrupt Pin Register.................................................. 403 10.1.21D27IPDevice 27 Interrupt Pin Register.................................................. 405 10.1.22D26IPDevice 26 Interrupt Pin Register.................................................. 405 10.1.23D25IPDevice 25 Interrupt Pin Register.................................................. 405 10.1.24D22IPDevice 22 Interrupt Pin Register.................................................. 406 10.1.25D20IPDevice 20 Interrupt Pin Register.................................................. 406 10.1.26D31IRDevice 31 Interrupt Route Register ............................................. 407 10.1.27D29IRDevice 29 Interrupt Route Register ............................................. 408 10.1.28D28IRDevice 28 Interrupt Route Register ............................................. 409 10.1.29D27IRDevice 27 Interrupt Route Register ............................................. 410 10.1.30D26IRDevice 26 Interrupt Route Register ............................................. 411 10.1.31D25IRDevice 25 Interrupt Route Register ............................................. 412

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10.1.32D22IRDevice 22 Interrupt Route Register .............................................. 413 10.1.33D20IRDevice 20 Interrupt Route Register .............................................. 414 10.1.34OICOther Interrupt Control Register ..................................................... 415 10.1.35PRSTSPower and Reset Status Register................................................. 416 10.1.36PM_CFGPower Management Configuration Register................................. 417 10.1.37DEEP_S3_POLDeep Sx From S3 Power Policies Register .......................... 418 10.1.38DEEP_S4_POLDeep Sx From S4 Power Policies Register .......................... 418 10.1.39DEEP_S5_POLDeep Sx From S5 Power Policies Register .......................... 418 10.1.40PMSYNC_CFGPMSYNC Configuration ..................................................... 419 10.1.41RCRTC Configuration Register .............................................................. 419 10.1.42HPTCHigh Precision Timer Configuration Register ................................... 420 10.1.43GCSGeneral Control and Status Register ............................................... 420 10.1.44BUCBacked Up Control Register ........................................................... 422 10.1.45FDFunction Disable Register ................................................................ 423 10.1.46CGClock Gating Register ..................................................................... 425 10.1.47FDSWFunction Disable SUS Well Register .............................................. 426 10.1.48DISPBDFDisplay Bus, Device and Function Initialization Register ............................................................................ 426 10.1.49FD2Function Disable 2 Register ............................................................ 427 10.1.50MISCCTLMiscellaneous Control Register ................................................ 427 10.1.51USBOCM1Overcurrent MAP Register 1................................................... 428 10.1.52USBOCM2Overcurrent MAP Register 2................................................... 429 10.1.53RMHWKCTLRate Matching Hub Wake Control Register ............................. 430 11 PCI-to-PCI Bridge Registers (D30:F0).................................................................... 433 11.1 PCI Configuration Registers (D30:F0) ................................................................. 433 11.1.1 VID Vendor Identification Register (PCI-PCID30:F0)............................. 434 11.1.2 DID Device Identification Register (PCI-PCID30:F0) ............................. 434 11.1.3 PCICMDPCI Command Register (PCI-PCID30:F0) ................................. 434 11.1.4 PSTSPCI Status Register (PCI-PCID30:F0) .......................................... 435 11.1.5 RIDRevision Identification Register (PCI-PCID30:F0) ............................ 437 11.1.6 CCClass Code Register (PCI-PCID30:F0)............................................. 437 11.1.7 PMLTPrimary Master Latency Timer Register (PCI-PCID30:F0)................................................................................ 437 11.1.8 HEADTYPHeader Type Register (PCI-PCID30:F0) ................................. 438 11.1.9 BNUMBus Number Register (PCI-PCID30:F0) ...................................... 438 11.1.10SMLTSecondary Master Latency Timer Register (PCI-PCID30:F0)................................................................................ 438 11.1.11IOBASE_LIMITI/O Base and Limit Register (PCI-PCID30:F0)................................................................................ 439 11.1.12SECSTSSecondary Status Register (PCI-PCID30:F0) ............................ 440 11.1.13MEMBASE_LIMITMemory Base and Limit Register (PCI-PCID30:F0)................................................................................ 441 11.1.14PREF_MEM_BASE_LIMITPrefetchable Memory Base and Limit Register (PCI-PCID30:F0) ..................................................... 441 11.1.15PMBU32Prefetchable Memory Base Upper 32 Bits Register (PCI-PCID30:F0) ................................................................... 442 11.1.16PMLU32Prefetchable Memory Limit Upper 32 Bits Register (PCI-PCID30:F0) ................................................................... 442 11.1.17CAPPCapability List Pointer Register (PCI-PCID30:F0) .......................... 442 11.1.18INTRInterrupt Information Register (PCI-PCID30:F0) ........................... 442 11.1.19BCTRLBridge Control Register (PCI-PCID30:F0) ................................... 443 11.1.20SPDHSecondary PCI Device Hiding Register (PCI-PCID30:F0)................................................................................ 444 11.1.21DTCDelayed Transaction Control Register (PCI-PCID30:F0)................................................................................ 445 11.1.22BPSBridge Proprietary Status Register (PCI-PCID30:F0)................................................................................ 446 11.1.23BPCBridge Policy Configuration Register (PCI-PCID30:F0)................................................................................ 447 11.1.24SVCAPSubsystem Vendor Capability Register (PCI-PCID30:F0)................................................................................ 448 11.1.25SVIDSubsystem Vendor IDs Register (PCI-PCID30:F0) ......................... 448 Gigabit LAN Configuration Registers ...................................................................... 449 12.1 Gigabit LAN Configuration Registers (Gigabit LAN D25:F0) ................................................................................... 449

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12.2

12.1.1 VIDVendor Identification Register (Gigabit LAND25:F0).......................................................................... 450 12.1.2 DIDDevice Identification Register (Gigabit LAND25:F0).......................................................................... 450 12.1.3 PCICMDPCI Command Register (Gigabit LAND25:F0).......................................................................... 451 12.1.4 PCISTSPCI Status Register (Gigabit LAND25:F0).......................................................................... 452 12.1.5 RIDRevision Identification Register (Gigabit LAND25:F0).......................................................................... 453 12.1.6 CCClass Code Register (Gigabit LAND25:F0).......................................................................... 453 12.1.7 CLSCache Line Size Register (Gigabit LAND25:F0).......................................................................... 453 12.1.8 PLTPrimary Latency Timer Register (Gigabit LAND25:F0).......................................................................... 453 12.1.9 HEADTYPHeader Type Register (Gigabit LAND25:F0).......................................................................... 453 12.1.10MBARAMemory Base Address Register A (Gigabit LAND25:F0).......................................................................... 454 12.1.11MBARBMemory Base Address Register B (Gigabit LAND25:F0).......................................................................... 454 12.1.12MBARCMemory Base Address Register C (Gigabit LAND25:F0).......................................................................... 455 12.1.13SVIDSubsystem Vendor ID Register (Gigabit LAND25:F0).......................................................................... 455 12.1.14SIDSubsystem ID Register (Gigabit LAND25:F0).......................................................................... 455 12.1.15ERBAExpansion ROM Base Address Register (Gigabit LAND25:F0).......................................................................... 455 12.1.16CAPPCapabilities List Pointer Register (Gigabit LAND25:F0).......................................................................... 456 12.1.17INTRInterrupt Information Register (Gigabit LAND25:F0).......................................................................... 456 12.1.18MLMGMaximum Latency/Minimum Grant Register (Gigabit LAND25:F0).......................................................................... 456 12.1.19CLIST1Capabilities List Register 1 (Gigabit LAND25:F0).......................................................................... 456 12.1.20PMCPCI Power Management Capabilities Register (Gigabit LAND25:F0).......................................................................... 457 12.1.21PMCSPCI Power Management Control and Status Register (Gigabit LAND25:F0) ............................................................. 458 12.1.22DRData Register (Gigabit LAND25:F0).......................................................................... 459 12.1.23CLIST2Capabilities List Register 2 (Gigabit LAND25:F0).......................................................................... 459 12.1.24MCTLMessage Control Register (Gigabit LAND25:F0).......................................................................... 459 12.1.25MADDLMessage Address Low Register (Gigabit LAND25:F0).......................................................................... 460 12.1.26MADDHMessage Address High Register (Gigabit LAND25:F0).......................................................................... 460 12.1.27MDATMessage Data Register (Gigabit LAND25:F0).......................................................................... 460 12.1.28FLRCAPFunction Level Reset Capability (Gigabit LAND25:F0).......................................................................... 460 12.1.29FLRCLVFunction Level Reset Capability Length and Version Register (Gigabit LAND25:F0) .................................................. 461 12.1.30DEVCTRLDevice Control Register (Gigabit LAND25:F0)......................... 461 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 462 12.2.1 GBECSR1Gigabit Ethernet Capabilities and Status Register 1 ................... 462 12.2.2 GBECSR2Gigabit Ethernet Capabilities and Status Register 2 ................... 463 12.2.3 GBECSR3Gigabit Ethernet Capabilities and Status Register 3 ................... 463 12.2.4 GBECSR4Gigabit Ethernet Capabilities and Status Register 4 ................... 463 12.2.5 GBECSR5Gigabit Ethernet Capabilities and Status Register 5 ................... 464 12.2.6 GBECSR6Gigabit Ethernet Capabilities and Status Register 6 ................... 464 12.2.7 GBECSR7Gigabit Ethernet Capabilities and Status Register 7 ................... 464

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11

12.2.8 GBECSR8Gigabit Ethernet Capabilities and Status Register 8.................... 465 12.2.9 GBECSR9Gigabit Ethernet Capabilities and Status Register 9.................... 465 13 LPC Interface Bridge Registers (D31:F0) ............................................................... 467 13.1 PCI Configuration Registers (LPC I/FD31:F0) .................................................... 467 13.1.1 VIDVendor Identification Register (LPC I/FD31:F0) .............................. 468 13.1.2 DIDDevice Identification Register (LPC I/FD31:F0)............................... 468 13.1.3 PCICMDPCI COMMAND Register (LPC I/FD31:F0)................................. 469 13.1.4 PCISTSPCI Status Register (LPC I/FD31:F0)........................................ 469 13.1.5 RIDRevision Identification Register (LPC I/FD31:F0) ............................ 470 13.1.6 PIProgramming Interface Register (LPC I/FD31:F0) ............................. 470 13.1.7 SCCSub Class Code Register (LPC I/FD31:F0) ..................................... 470 13.1.8 BCCBase Class Code Register (LPC I/FD31:F0) .................................... 471 13.1.9 PLTPrimary Latency Timer Register (LPC I/FD31:F0) ............................ 471 13.1.10HEADTYPHeader Type Register (LPC I/FD31:F0) .................................. 471 13.1.11SSSub System Identifiers Register (LPC I/FD31:F0) ............................. 471 13.1.12CAPPCapability List Pointer Register (LPC I/FD31:F0) ........................... 472 13.1.13PMBASEACPI Base Address Register (LPC I/FD31:F0)........................... 472 13.1.14ACPI_CNTLACPI Control Register (LPC I/F D31:F0) ............................. 473 13.1.15GPIOBASEGPIO Base Address Register (LPC I/F D31:F0) ..................... 473 13.1.16GCGPIO Control Register (LPC I/F D31:F0) ........................................ 474 13.1.17PIRQ[n]_ROUTPIRQ[A,B,C,D] Routing Control Register (LPC I/FD31:F0) ................................................................................ 475 13.1.18SIRQ_CNTLSerial IRQ Control Register (LPC I/FD31:F0) ................................................................................ 476 13.1.19PIRQ[n]_ROUTPIRQ[E,F,G,H] Routing Control Register (LPC I/FD31:F0) ................................................................................ 477 13.1.20LPC_IBDFIOxAPIC Bus:Device:Function (LPC I/FD31:F0) ................................................................................ 477 13.1.21LPC_HnBDF HPET n Bus:Device:Function (LPC I/FD31:F0) ................................................................................ 478 13.1.22LPC_I/O_DECI/O Decode Ranges Register (LPC I/FD31:F0) ................................................................................ 479 13.1.23LPC_ENLPC I/F Enables Register (LPC I/FD31:F0) ................................ 480 13.1.24GEN1_DECLPC I/F Generic Decode Range 1 Register (LPC I/FD31:F0) ................................................................................ 481 13.1.25GEN2_DECLPC I/F Generic Decode Range 2 Register (LPC I/FD31:F0) ................................................................................ 481 13.1.26GEN3_DECLPC I/F Generic Decode Range 3 Register (LPC I/FD31:F0) ................................................................................ 482 13.1.27GEN4_DECLPC I/F Generic Decode Range 4 Register (LPC I/FD31:F0) ................................................................................ 482 13.1.28ULKMC USB Legacy Keyboard / Mouse Control Register(LPC I/FD31:F0) .......................................................... 483 13.1.29LGMR LPC I/F Generic Memory Range Register (LPC I/FD31:F0) ................................................................................ 484 13.1.30BIOS_SEL1BIOS Select 1 Register (LPC I/FD31:F0) ................................................................................ 485 13.1.31BIOS_SEL2BIOS Select 2 Register (LPC I/FD31:F0) ................................................................................ 486 13.1.32BIOS_DEC_EN1BIOS Decode Enable Register (LPC I/FD31:F0) .................................................................... 487 13.1.33BIOS_CNTLBIOS Control Register (LPC I/FD31:F0) ................................................................................ 489 13.1.34FDCAPFeature Detection Capability ID Register (LPC I/FD31:F0) ................................................................................ 490 13.1.35FDLENFeature Detection Capability Length Register (LPC I/FD31:F0) ................................................................................ 490 13.1.36FDVERFeature Detection Version Register (LPC I/FD31:F0) ................................................................................ 490 13.1.37FVECIDXFeature Vector Index Register (LPC I/FD31:F0) ................................................................................ 490 13.1.38FVECDFeature Vector Data Register (LPC I/FD31:F0) ................................................................................ 491 13.1.39Feature Vector Space ............................................................................ 491 13.1.39.1FVEC0Feature Vector Register 0 ............................................. 491 13.1.39.2FVEC1Feature Vector Register 1 ............................................. 492

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13.2

13.3

13.4

13.5

13.6

13.7

13.8

13.1.39.3FVEC2Feature Vector Register 2 ............................................. 492 13.1.39.4FVEC3Feature Vector Register 3 ............................................. 492 13.1.40RCBARoot Complex Base Address Register (LPC I/FD31:F0) ................................................................................ 493 DMA I/O Registers........................................................................................... 494 13.2.1 DMABASE_CADMA Base and Current Address Registers .......................... 495 13.2.2 DMABASE_CCDMA Base and Current Count Registers ............................. 496 13.2.3 DMAMEM_LPDMA Memory Low Page Registers ....................................... 496 13.2.4 DMACMDDMA Command Register ........................................................ 497 13.2.5 DMASTADMA Status Register .............................................................. 497 13.2.6 DMA_WRSMSKDMA Write Single Mask Register...................................... 498 13.2.7 DMACH_MODEDMA Channel Mode Register ........................................... 498 13.2.8 DMA Clear Byte Pointer Register............................................................. 499 13.2.9 DMA Master Clear Register .................................................................... 499 13.2.10DMA_CLMSKDMA Clear Mask Register .................................................. 499 13.2.11DMA_WRMSKDMA Write All Mask Register ............................................ 500 Timer I/O Registers ......................................................................................... 500 13.3.1 TCWTimer Control Word Register ......................................................... 501 13.3.2 SBYTE_FMTInterval Timer Status Byte Format Register........................... 503 13.3.3 Counter Access Ports Register ................................................................ 504 8259 Interrupt Controller (PIC) Registers ........................................................... 504 13.4.1 Interrupt Controller I/O MAP .................................................................. 504 13.4.2 ICW1Initialization Command Word 1 Register ........................................ 505 13.4.3 ICW2Initialization Command Word 2 Register ........................................ 506 13.4.4 ICW3Master Controller Initialization Command Word 3 Register ................................................................................... 506 13.4.5 ICW3Slave Controller Initialization Command Word 3 Register ................................................................................... 507 13.4.6 ICW4Initialization Command Word 4 Register ........................................ 507 13.4.7 OCW1Operational Control Word 1 (Interrupt Mask) Register .............................................................................................. 508 13.4.8 OCW2Operational Control Word 2 Register ............................................ 508 13.4.9 OCW3Operational Control Word 3 Register ............................................ 509 13.4.10ELCR1Master Controller Edge/Level Triggered Register ........................... 510 13.4.11ELCR2Slave Controller Edge/Level Triggered Register ............................. 511 Advanced Programmable Interrupt Controller (APIC)............................................ 512 13.5.1 APIC Register Map................................................................................ 512 13.5.2 INDIndex Register ............................................................................. 512 13.5.3 DATData Register .............................................................................. 513 13.5.4 EOIREOI Register .............................................................................. 513 13.5.5 IDIdentification Register ..................................................................... 514 13.5.6 VERVersion Register .......................................................................... 514 13.5.7 REDIR_TBLRedirection Table Register................................................... 515 Real Time Clock Registers................................................................................. 517 13.6.1 I/O Register Address Map ...................................................................... 517 13.6.2 Indexed Registers ................................................................................ 518 13.6.2.1 RTC_REGARegister A ............................................................ 519 13.6.2.2 RTC_REGBRegister B (General Configuration) .......................... 520 13.6.2.3 RTC_REGCRegister C (Flag Register) ...................................... 521 13.6.2.4 RTC_REGDRegister D (Flag Register) ...................................... 521 Processor Interface Registers ............................................................................ 522 13.7.1 NMI_SCNMI Status and Control Register ............................................... 522 13.7.2 NMI_ENNMI Enable (and Real Time Clock Index) Register .............................................................................................. 523 13.7.3 PORT92Init Register........................................................................... 523 13.7.4 COPROC_ERRCoprocessor Error Register .............................................. 523 13.7.5 RST_CNTReset Control Register........................................................... 524 Power Management Registers ........................................................................... 525 13.8.1 Power Management PCI Configuration Registers (PMD31:F0) ...................................................................................... 525 13.8.1.1 GEN_PMCON_1General PM Configuration 1 Register (PMD31:F0) ........................................................................ 526 13.8.1.2 GEN_PMCON_2General PM Configuration 2 Register (PMD31:F0) ........................................................................ 527 13.8.1.3 GEN_PMCON_3General PM Configuration 3 Register (PMD31:F0) ........................................................................ 528

Datasheet

13

13.8.1.4 GEN_PMCON_LOCKGeneral Power Management Configuration Lock Register.......................................................................... 531 13.8.1.5 BM_BREAK_EN_2 Register #2 (PMD31:F0) .............................. 531 13.8.1.6 BM_BREAK_EN Register (PMD31:F0) ....................................... 532 13.8.1.7 PMIRPower Management Initialization Register (PMD31:F0)..... 533 13.8.1.8 GPIO_ROUTGPIO Routing Control Register (PMD31:F0) ......................................................................... 533 13.8.2 APM I/O Decode Register ....................................................................... 534 13.8.2.1 APM_CNTAdvanced Power Management Control Port Register ..... 534 13.8.2.2 APM_STSAdvanced Power Management Status Port Register ...... 534 13.8.3 Power Management I/O Registers ........................................................... 535 13.8.3.1 PM1_STSPower Management 1 Status Register......................... 535 13.8.3.2 PM1_ENPower Management 1 Enable Register .......................... 538 13.8.3.3 PM1_CNTPower Management 1 Control Register ....................... 539 13.8.3.4 PM1_TMRPower Management 1 Timer Register ......................... 540 13.8.3.5 GPE0_STSGeneral Purpose Event 0 Status Register................... 540 13.8.3.6 GPE0_ENGeneral Purpose Event 0 Enables Register................... 543 13.8.3.7 SMI_ENSMI Control and Enable Register.................................. 545 13.8.3.8 SMI_STSSMI Status Register.................................................. 547 13.8.3.9 ALT_GP_SMI_ENAlternate GPI SMI Enable Register ................... 549 13.8.3.10ALT_GP_SMI_STSAlternate GPI SMI Status Register.................. 550 13.8.3.11GPE_CNTLGeneral Purpose Control Register ............................. 550 13.8.3.12DEVACT_STS Device Activity Status Register........................... 551 13.8.3.13PM2_CNTPower Management 2 Control Register ....................... 551 13.9 System Management TCO Registers ................................................................... 552 13.9.1 TCO_RLDTCO Timer Reload and Current Value Register........................... 552 13.9.2 TCO_DAT_INTCO Data In Register ....................................................... 553 13.9.3 TCO_DAT_OUTTCO Data Out Register................................................... 553 13.9.4 TCO1_STSTCO1 Status Register........................................................... 553 13.9.5 TCO2_STSTCO2 Status Register........................................................... 555 13.9.6 TCO1_CNTTCO1 Control Register ......................................................... 556 13.9.7 TCO2_CNTTCO2 Control Register ......................................................... 557 13.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers ....................................... 557 13.9.9 TCO_WDCNTTCO Watchdog Control Register ......................................... 558 13.9.10SW_IRQ_GENSoftware IRQ Generation Register ..................................... 558 13.9.11TCO_TMRTCO Timer Initial Value Register ............................................. 558 13.10 General Purpose I/O Registers ........................................................................... 559 13.10.1GPIO_USE_SELGPIO Use Select Register ............................................... 560 13.10.2GP_IO_SELGPIO Input/Output Select Register ....................................... 560 13.10.3GP_LVLGPIO Level for Input or Output Register...................................... 561 13.10.4GPO_BLINKGPO Blink Enable Register................................................... 561 13.10.5GP_SER_BLINKGP Serial Blink Register ................................................. 562 13.10.6GP_SB_CMDSTSGP Serial Blink Command Status Register..................................................................................... 562 13.10.7GP_SB_DATAGP Serial Blink Data Register ............................................ 563 13.10.8GPI_NMI_ENGPI NMI Enable Register ................................................... 563 13.10.9GPI_NMI_STSGPI NMI Status Register .................................................. 563 13.10.10GPI_INVGPIO Signal Invert Register.................................................... 564 13.10.11GPIO_USE_SEL2GPIO Use Select 2 Register ......................................... 564 13.10.12GP_IO_SEL2GPIO Input/Output Select 2 Register ................................. 565 13.10.13GP_LVL2GPIO Level for Input or Output 2 Register................................ 565 13.10.14GPIO_USE_SEL3GPIO Use Select 3 Register ......................................... 566 13.10.15GP_IO_SEL3GPIO Input/Output Select 3 Register ................................. 566 13.10.16GP_LVL3GPIO Level for Input or Output 3 Register................................ 567 13.10.17GP_RST_SEL1 GPIO Reset Select Register .......................................... 567 13.10.18GP_RST_SEL2 GPIO Reset Select Register .......................................... 568 13.10.19GP_RST_SEL3 GPIO Reset Select Register .......................................... 568 14 SATA Controller Registers (D31:F2) ....................................................................... 569 14.1 PCI Configuration Registers (SATAD31:F2) ........................................................ 569 14.1.1 VIDVendor Identification Register (SATAD31:F2) .................................. 571 14.1.2 DIDDevice Identification Register (SATAD31:F2) .................................. 571 14.1.3 PCICMDPCI Command Register (SATAD31:F2) ..................................... 571 14.1.4 PCISTS PCI Status Register (SATAD31:F2) ......................................... 572 14.1.5 RIDRevision Identification Register (SATAD31:F2) ................................ 573 14.1.6 PIProgramming Interface Register (SATAD31:F2) ................................. 573 14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h ........... 573

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Datasheet

14.2

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 573 14.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .......... 574 14.1.7 SCCSub Class Code Register (SATAD31:F2) ........................................ 574 14.1.8 BCCBase Class Code Register (SATAD31:F2SATAD31:F2) ................................................................ 574 14.1.9 PMLTPrimary Master Latency Timer Register (SATAD31:F2).................................................................................... 574 14.1.10HTYPEHeader Type Register (SATAD31:F2).................................................................................... 575 14.1.11PCMD_BARPrimary Command Block Base Address Register (SATAD31:F2) ....................................................................... 575 14.1.12PCNL_BARPrimary Control Block Base Address Register (SATAD31:F2).................................................................................... 575 14.1.13SCMD_BARSecondary Command Block Base Address Register (SATAD31:F2) ....................................................................... 576 14.1.14SCNL_BARSecondary Control Block Base Address Register (SATAD31:F2) ....................................................................... 576 14.1.15BARLegacy Bus Master Base Address Register (SATAD31:F2).................................................................................... 577 14.1.16ABAR/SIDPBAAHCI Base Address Register/Serial ATA Index Data Pair Base Address (SATAD31:F2).......................................... 577 14.1.16.1When SCC is not 01h............................................................... 577 14.1.16.2When SCC is 01h .................................................................... 578 14.1.17SVIDSubsystem Vendor Identification Register (SATAD31:F2).................................................................................... 578 14.1.18SIDSubsystem Identification Register (SATAD31:F2) ............................ 578 14.1.19CAPCapabilities Pointer Register (SATAD31:F2).................................... 578 14.1.20INT_LNInterrupt Line Register (SATAD31:F2) ...................................... 579 14.1.21INT_PNInterrupt Pin Register (SATAD31:F2)........................................ 579 14.1.22IDE_TIMIDE Timing Register (SATAD31:F2) ........................................ 579 14.1.23SIDETIMSlave IDE Timing Register (SATAD31:F2)................................ 580 14.1.24SDMA_CNTSynchronous DMA Control Register (SATAD31:F2).................................................................................... 580 14.1.25SDMA_TIMSynchronous DMA Timing Register (SATAD31:F2).................................................................................... 580 14.1.26IDE_CONFIGIDE I/O Configuration Register (SATAD31:F2).................................................................................... 581 14.1.27PIDPCI Power Management Capability Identification Register (SATAD31:F2) ....................................................................... 581 14.1.28PCPCI Power Management Capabilities Register (SATAD31:F2).................................................................................... 582 14.1.29PMCSPCI Power Management Control and Status Register (SATAD31:F2) ....................................................................... 582 14.1.30MSICIMessage Signaled Interrupt Capability Identification Register (SATAD31:F2) .................................................... 583 14.1.31MSIMCMessage Signaled Interrupt Message Control Register (SATAD31:F2) ............................................................ 583 14.1.32MSIMA Message Signaled Interrupt Message Address Register (SATAD31:F2) ........................................................... 585 14.1.33MSIMDMessage Signaled Interrupt Message Data Register (SATAD31:F2) ................................................................ 585 14.1.34MAPAddress Map Register (SATAD31:F2) ............................................ 586 14.1.35PCSPort Control and Status Register (SATAD31:F2).............................. 587 14.1.36SCLKCGSATA Clock Gating Control Register .......................................... 589 14.1.37SGCSATA General Configuration Register .............................................. 590 14.1.38SATACR0SATA Capability Register 0 (SATAD31:F2) .............................. 591 14.1.39SATACR1SATA Capability Register 1 (SATAD31:F2) .............................. 591 14.1.40FLRCIDFLR Capability ID Register (SATAD31:F2) ................................. 592 14.1.41FLRCLVFLR Capability Length and Version Register (SATAD31:F2) .......... 592 14.1.42FLRCFLR Control Register (SATAD31:F2)............................................. 593 14.1.43ATCAPM Trapping Control Register (SATAD31:F2) ................................ 593 14.1.44ATSAPM Trapping Status Register (SATAD31:F2) ................................. 594 14.1.45SPScratch Pad Register (SATAD31:F2)................................................ 594 14.1.46BFCSBIST FIS Control/Status Register (SATAD31:F2) ........................... 595 14.1.47BFTD1BIST FIS Transmit Data1 Register (SATAD31:F2) ........................ 597 14.1.48BFTD2BIST FIS Transmit Data2 Register (SATAD31:F2) ........................ 597 Bus Master IDE I/O Registers (D31:F2) .............................................................. 598

Datasheet

15

14.3

14.4

14.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2) .......................... 599 14.2.2 BMIS[P,S]Bus Master IDE Status Register (D31:F2)................................ 600 14.2.3 BMID[P,S]Bus Master IDE Descriptor Table Pointer Register (D31:F2)................................................................................. 601 14.2.4 AIRAHCI Index Register (D31:F2) ........................................................ 601 14.2.5 AIDRAHCI Index Data Register (D31:F2)............................................... 601 Serial ATA Index/Data Pair Superset Registers..................................................... 602 14.3.1 SINDXSerial ATA Index Register (D31:F2) ............................................. 602 14.3.2 SDATASerial ATA Data Register (D31:F2) .............................................. 603 14.3.2.1 PxSSTSSerial ATA Status Register (D31:F2) ............................. 603 14.3.2.2 PxSCTLSerial ATA Control Register (D31:F2) ............................ 604 14.3.2.3 PxSERRSerial ATA Error Register (D31:F2)............................... 605 AHCI Registers (D31:F2) .................................................................................. 606 14.4.1 AHCI Generic Host Control Registers (D31:F2).......................................... 607 14.4.1.1 CAPHost Capabilities Register (D31:F2) ................................... 607 14.4.1.2 GHCGlobal PCH Control Register (D31:F2) ............................... 609 14.4.1.3 ISInterrupt Status Register (D31:F2) ...................................... 610 14.4.1.4 PIPorts Implemented Register (D31:F2) .................................. 611 14.4.1.5 VSAHCI Version Register (D31:F2).......................................... 612 14.4.1.6 EM_LOCEnclosure Management Location Register (D31:F2)........ 612 14.4.1.7 EM_CTRLEnclosure Management Control Register (D31:F2)........ 612 14.4.1.8 CAP2HBA Capabilities Extended Register.................................. 613 14.4.1.9 RSTFIntel RST Feature Capabilities Register ........................... 614 14.4.2 Port Registers (D31:F2) ......................................................................... 616 14.4.2.1 PxCLBPort [5:0] Command List Base Address Register (D31:F2)................................................................................ 619 14.4.2.2 PxCLBUPort [5:0] Command List Base Address Upper 32-Bits Register (D31:F2) ........................................................ 619 14.4.2.3 PxFBPort [5:0] FIS Base Address Register (D31:F2) .................. 619 14.4.2.4 PxFBUPort [5:0] FIS Base Address Upper 32-Bits Register (D31:F2) ................................................................... 620 14.4.2.5 PxISPort [5:0] Interrupt Status Register (D31:F2) .................... 620 14.4.2.6 PxIEPort [5:0] Interrupt Enable Register (D31:F2) .................... 622 14.4.2.7 PxCMDPort [5:0] Command Register (D31:F2) ......................... 623 14.4.2.8 PxTFDPort [5:0] Task File Data Register (D31:F2)..................... 626 14.4.2.9 PxSIGPort [5:0] Signature Register (D31:F2) ........................... 626 14.4.2.10PxSSTSPort [5:0] Serial ATA Status Register (D31:F2) .............. 627 14.4.2.11PxSCTL Port [5:0] Serial ATA Control Register (D31:F2) ........... 628 14.4.2.12PxSERRPort [5:0] Serial ATA Error Register (D31:F2) ................ 629 14.4.2.13PxSACTPort [5:0] Serial ATA Active Register (D31:F2)............... 631 14.4.2.14PxCIPort [5:0] Command Issue Register (D31:F2) .................... 631

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SATA Controller Registers (D31:F5) ....................................................................... 633 15.1 PCI Configuration Registers (SATAD31:F5) ........................................................ 633 15.1.1 VIDVendor Identification Register (SATAD31:F5) ................................. 634 15.1.2 DIDDevice Identification Register (SATAD31:F5) ................................. 634 15.1.3 PCICMDPCI Command Register (SATAD31:F5) ..................................... 635 15.1.4 PCISTS PCI Status Register (SATAD31:F5) ......................................... 636 15.1.5 RIDRevision Identification Register (SATAD31:F5) ............................... 636 15.1.6 PIProgramming Interface Register (SATAD31:F5) ................................. 637 15.1.7 SCCSub Class Code Register (SATAD31:F5) ......................................... 637 15.1.8 BCCBase Class Code Register (SATAD31:F5SATAD31:F5)................................................................. 637 15.1.9 PMLTPrimary Master Latency Timer Register (SATAD31:F5) .................................................................................... 638 15.1.10PCMD_BARPrimary Command Block Base Address Register (SATAD31:F5)........................................................................ 638 15.1.11PCNL_BARPrimary Control Block Base Address Register (SATAD31:F5) .................................................................................... 638 15.1.12SCMD_BARSecondary Command Block Base Address Register (SATA D31:F5) ........................................................................ 639 15.1.13SCNL_BARSecondary Control Block Base Address Register (SATA D31:F5) ........................................................................ 639 15.1.14BAR Legacy Bus Master Base Address Register (SATAD31:F5) ......