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IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
ACPI 2.0 ACPI 2.0 Specification Specification Technical ReviewTechnical Review
Guy TherienGuy TherienACPI Architecture Mgr. ACPI Architecture Mgr. Mobile Architecture LabMobile Architecture LabIntel CorporationIntel CorporationJune/July 2000June/July 2000
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Learning ObjectivesLearning ObjectivesDifferentiate the changes in ACPI moving from Differentiate the changes in ACPI moving from
ACPI 1.0b to ACPI 2.0ACPI 1.0b to ACPI 2.0
Identify the specific ACPI 2.0 changes that Identify the specific ACPI 2.0 changes that support or impact mobile platformssupport or impact mobile platforms
Explain how Intel products will be supported Explain how Intel products will be supported using ACPI 2.0 interfacesusing ACPI 2.0 interfaces
Articulate the time frame for when ACPI 2.0 Articulate the time frame for when ACPI 2.0 platform support will be required including the platform support will be required including the estimated OS support timelineestimated OS support timeline
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
AgendaAgendaACPI 2.0 OverviewACPI 2.0 Overview
Section by Section Review of Section by Section Review of
ChangesChanges
ACPI 2.0 Release ScheduleACPI 2.0 Release Schedule
Platform Support TimelinePlatform Support Timeline
OS Support TimelineOS Support Timeline
Call to ActionCall to Action
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
ACPI 2.0 OverviewACPI 2.0 Overview64-bit processor / addressing support added64-bit processor / addressing support addedProcessor / device performance states addedProcessor / device performance states addedSM Bus CM interfaces rewrittenSM Bus CM interfaces rewrittenMany server related enhancements added Many server related enhancements added
– hot-pluggable CPUs, memory, GPE Blockshot-pluggable CPUs, memory, GPE BlocksLegacy Reduced HW IA-PC support includedLegacy Reduced HW IA-PC support includedFunctional Fixed Hardware concept definedFunctional Fixed Hardware concept definedGeneral readability/consistency enhancementsGeneral readability/consistency enhancementsASL examples updated (corrected)ASL examples updated (corrected)
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 1 - IntroductionSection 1 - Introduction
Enhanced for readabilityEnhanced for readability
Technical references updatedTechnical references updated
Requirements removed!Requirements removed!–Design guides will now specify required Design guides will now specify required
ACPI 2.0 defined interfaces / platform ACPI 2.0 defined interfaces / platform featuresfeatures
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000Section 2 - DefinitionsSection 2 - Definitions
Definitions updated, added, removedDefinitions updated, added, removed–EFIEFI
–APIC / SAPICAPIC / SAPIC
–PSDT removedPSDT removed
Device and processor performance Device and processor performance state definitions addedstate definitions added
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 3 - OverviewSection 3 - Overview Battery behavior clarifiedBattery behavior clarified
– Batteries must comply with their interface requirementsBatteries must comply with their interface requirements
– Multi-battery systems are not required to present a compositeMulti-battery systems are not required to present a composite
– OS must be notified of changes in battery statusOS must be notified of changes in battery status– Insertion, removal, warning and low levelsInsertion, removal, warning and low levels
Device and processor performance states addedDevice and processor performance states added– Supports mobile Pentium® III processor featuring Intel® Supports mobile Pentium® III processor featuring Intel®
SpeedStepSpeedStepTMTM Technology Technology
Thermal management section rewrittenThermal management section rewritten
Incorporate Device Performance Incorporate Device Performance States In All New SystemsStates In All New Systems
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 4 - HardwareSection 4 - Hardware No hardware changes are required for ACPI 2.0No hardware changes are required for ACPI 2.0
– ACPI 1.0 compliant silicon is compliant with ACPI 2.0ACPI 1.0 compliant silicon is compliant with ACPI 2.0
Updated for readabilityUpdated for readability
Fixed hardware register locations expanded Fixed hardware register locations expanded – I/O, Memory, PCI Config, Functional Fixed HWI/O, Memory, PCI Config, Functional Fixed HW
Processor control moved to section 8Processor control moved to section 8
Server SupportServer Support– GPE block device addedGPE block device added
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Hardware – continuedHardware – continued Functional Fixed HardwareFunctional Fixed Hardware
– CPU manufacturer may provide functional equivalent “fixed CPU manufacturer may provide functional equivalent “fixed hardware” interface comprised of hardware and softwarehardware” interface comprised of hardware and software
– May be defined when the interfaces are May be defined when the interfaces are common across common across machine designsmachine designs e.g. systems sharing a common CPU e.g. systems sharing a common CPU architecture that does not support fixed hardware for all the architecture that does not support fixed hardware for all the required interfacesrequired interfaces
– OEMs may only specify interfaces as Functional Fixed OEMs may only specify interfaces as Functional Fixed Hardware as specified by the CPU manufacturerHardware as specified by the CPU manufacturer
– Intel® SpeedStepIntel® SpeedStepTMTM Technology interfaces employ the Technology interfaces employ the Functional Fixed Hardware definitionFunctional Fixed Hardware definition
– See example later on in this presentationSee example later on in this presentation
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Hardware - continuedHardware - continued Reset RegisterReset Register
– The optional ACPI reset mechanism specifies a The optional ACPI reset mechanism specifies a standard mechanism that provides a complete standard mechanism that provides a complete system reset. When implemented, this system reset. When implemented, this mechanism must reset the entire system. This mechanism must reset the entire system. This includes processors, core logic, all buses, and includes processors, core logic, all buses, and all peripherals. Asserting the reset mechanism all peripherals. Asserting the reset mechanism is the logical equivalent to power cycling the is the logical equivalent to power cycling the machinemachine from a software perspective from a software perspective
– Added to support legacy reduced HW IA-PCAdded to support legacy reduced HW IA-PC
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 5 - SoftwareSection 5 - Software ACPI system description table definitions contain ACPI system description table definitions contain
significant changes significant changes
– Fixed register address space locations expandedFixed register address space locations expanded– New Generic Address Structure allows a register’s address space New Generic Address Structure allows a register’s address space
to be specifiedto be specified
– 64 bit addressing enhancements64 bit addressing enhancements
– IA-64 Interrupt controller (SAPIC / IOSAPIC) tables addedIA-64 Interrupt controller (SAPIC / IOSAPIC) tables added
– New fields have been added at end of the system description New fields have been added at end of the system description tables to maintain compatibility with ACPI 1.0tables to maintain compatibility with ACPI 1.0
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Software - continuedSoftware - continued RSDP Structure extended to allow 64-bit pointer to the RSDP Structure extended to allow 64-bit pointer to the
new extended RSDT (XSDT)new extended RSDT (XSDT)
Added support for finding the RSDP structure on EFI-Added support for finding the RSDP structure on EFI-enabled systems (IA-64)enabled systems (IA-64)
Added XSDT (extended RSDT)Added XSDT (extended RSDT)– Provides identical functionality to the RSDT but accommodates Provides identical functionality to the RSDT but accommodates
64-bit physical addresses64-bit physical addresses
– XSDT supersedes RSDT – ACPI 2.0 OS will look for XSDT firstXSDT supersedes RSDT – ACPI 2.0 OS will look for XSDT first
– Allows platform to provide one set of tables to an ACPI 1.0 OS Allows platform to provide one set of tables to an ACPI 1.0 OS and another set of tables to an ACPI 2.0 OSand another set of tables to an ACPI 2.0 OS
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Software - continuedSoftware - continuedFADT ExtensionsFADT Extensions
– Expanded for 64-bit addressingExpanded for 64-bit addressing– Preferred PM profile field addedPreferred PM profile field added
– System types field used to set default power System types field used to set default power management policy parameters during OS management policy parameters during OS installation installation
– Ease of use enhancement
– Legacy reduced HW IA-PCs accommodatedLegacy reduced HW IA-PCs accommodated– IA-PC Boot Architecture FlagsIA-PC Boot Architecture Flags
– Set of flags is used by an operating system to guide the assumptions it can make in initializing hardware on IA-PC platforms
– Added Debug Port Table for Windows* PCsAdded Debug Port Table for Windows* PCs
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Software - continuedSoftware - continued Added IA-64 Interrupt controller support Added IA-64 Interrupt controller support
– Added SAPIC / IOSAPIC tablesAdded SAPIC / IOSAPIC tables
New Device Notifications added forNew Device Notifications added for– Processor, Thermal, and PCI Hot PlugProcessor, Thermal, and PCI Hot Plug
Complete list of ALL ACPI-dComplete list of ALL ACPI-defined generic objects and efined generic objects and control methodscontrol methods now provided now provided
Expanded reserved table signaturesExpanded reserved table signatures– DBGP, ECDT, ETDT, HMEM, OEMxDBGP, ECDT, ETDT, HMEM, OEMx
System type attributes added to fixed feature flagsSystem type attributes added to fixed feature flags– Sealed case, headlessSealed case, headless
Removed the PSDTRemoved the PSDT Namespace search rules clarifiedNamespace search rules clarified
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Software - continuedSoftware - continued \_PR and \_TZ scopes obsoleted\_PR and \_TZ scopes obsoleted
– Processors and thermal zones now defined under \_SBProcessors and thermal zones now defined under \_SB
Server EnhancementsServer Enhancements– Introduced GPE blocks implemented via GPE Block device Introduced GPE blocks implemented via GPE Block device
into the event modelinto the event model
Embedded Controller Boot Resources Table addedEmbedded Controller Boot Resources Table added– Enables use of EC operation regions during enumerationEnables use of EC operation regions during enumeration
_REV now evaluates to revision of ACPI that OS _REV now evaluates to revision of ACPI that OS implementsimplements
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
ACPI 2.0 System DescriptionACPI 2.0 System Description Tables Tables
RSDP Structure
RSDT XSDT
SSDT SSDT
DSDTFADT
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 6 - ConfigurationSection 6 - Configuration Clarified that an _HID or _ADR is required for Clarified that an _HID or _ADR is required for
each deviceeach device
_DMA (DMA Resource)_DMA (DMA Resource)– Only defined under devices that represent bussesOnly defined under devices that represent busses
– It specifies the ranges the bus controller (bridge) It specifies the ranges the bus controller (bridge) decodes on the child-side of it’s interfacedecodes on the child-side of it’s interface
_STR (String)_STR (String)– Provides a Unicode string used by the OS to provide Provides a Unicode string used by the OS to provide
information to an end user when describing the deviceinformation to an end user when describing the device – e.g. when device is unknown by OS, this string can be e.g. when device is unknown by OS, this string can be
displayeddisplayed
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Configuration - continuedConfiguration - continued_INI behavior expanded_INI behavior expanded
Clarified use of_REG methodClarified use of_REG method– Make sure you use it!Make sure you use it!
Moved floppy related objects to section 10Moved floppy related objects to section 10
Resource Type Specific Flags enhancedResource Type Specific Flags enhanced– Memory types expandedMemory types expanded
All Macros moved to Section 15 – ASLAll Macros moved to Section 15 – ASL– Added Generic Register Descriptor macroAdded Generic Register Descriptor macro
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Configuration - continuedConfiguration - continued_EDL (Eject Device List)_EDL (Eject Device List)
– This object evaluates to a package of name This object evaluates to a package of name space references containing the names of space references containing the names of device objects that are dependent on the device device objects that are dependent on the device under which the _EDL object is declaredunder which the _EDL object is declared
– Allows multiple mobile docks to be correctly Allows multiple mobile docks to be correctly representedrepresented
See _EJD / _EDL example on next slideSee _EJD / _EDL example on next slide
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
An example use of _EJD and _EDL with pass-through docks is as follows: Scope(\_SB.PCI0) { Device(DOCK1) { // Pass through dock – DOCK1 Name(_ADR, …) Method(_EJ0, 0) {…} Method(_DCK, 1) {…} Name(_BDN, …) Method(_STA, 0) {0xF} Name(_EDL, Package( ) { // DOCK1 has two dependent devices – IDE2 and CB2 \_SB.PCI0.IDE2, \_SB.PCI0.CB2}) } Device(DOCK2) { // Pass through dock – DOCK2 Name(_ADR, …) Method(_EJ0, 0) {…} Method(_DCK, 1) {…} Name(_BDN, …) Method(_STA, 0) {0x0} Name(_EDL, Package( ) { // DOCK2 has one dependent device – IDE2 \_SB.PCI0.IDE2}) } Device(IDE1) { // IDE Drive1 not dependent on the dock Name(_ADR, …) } Device(IDE2) { // IDE Drive2 Name(_ADR, …) Name(_EJD,” \_SB.PCI0.DOCK1”) // Dependent on DOCK1 } Device(CB2) { // CardBus Controller Name(_ADR, …) Name(_EJD,” \_SB.PCI0.DOCK1”) // Dependent on DOCK1 } } // end \_SB.PCIO
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Configuration Enhancements Configuration Enhancements for Serversfor Servers _FIX (Fixed Hardware)_FIX (Fixed Hardware)
– Provides a correlation between the fixed hardware register Provides a correlation between the fixed hardware register blocks and the devices in the ACPI namespace that implement blocks and the devices in the ACPI namespace that implement themthem
_MAT (Multiple APIC Table Entry)_MAT (Multiple APIC Table Entry) – Facilitates hot plugging of APICsFacilitates hot plugging of APICs
_PXM (Proximity)_PXM (Proximity)– Provides topology information conveying proximity of Provides topology information conveying proximity of
processors and memory enabling CC-NUMA optimizations processors and memory enabling CC-NUMA optimizations _HPP (Hot Plug Parameters)_HPP (Hot Plug Parameters)
– Specifies the Cache-line size, Latency timer, SERR enable, and Specifies the Cache-line size, Latency timer, SERR enable, and PERR enable values for use during hot inserting a PCI devicePERR enable values for use during hot inserting a PCI device
_SEG (Segment)_SEG (Segment)– Indicates a bus segment location - a level higher than _BBNIndicates a bus segment location - a level higher than _BBN
– Each segment has a potential of 256 PCI Bus Numbers Each segment has a potential of 256 PCI Bus Numbers
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 7 – Power and Performance Section 7 – Power and Performance ManagementManagementAdded Device Performance State conceptAdded Device Performance State concept
New _GTS (Going To Sleep) MethodNew _GTS (Going To Sleep) Method– Optional. If it exists, OSPM must execute the _GTS Optional. If it exists, OSPM must execute the _GTS
control method just prior to setting the sleep control method just prior to setting the sleep enable (SLP_EN) bit in the PM1 control register enable (SLP_EN) bit in the PM1 control register when entering the S1, S2, S3, and S4 sleeping when entering the S1, S2, S3, and S4 sleeping states and when entering S5 for orderly shutdownstates and when entering S5 for orderly shutdown
New _BFS (Back From Sleep)New _BFS (Back From Sleep) Method Method– Optional. If it exists, OSPM must execute the _BFS Optional. If it exists, OSPM must execute the _BFS
method immediately following wake from any method immediately following wake from any sleeping state S1, S2, S3, or S4sleeping state S1, S2, S3, or S4
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Power & Performance - Power & Performance - continuedcontinuedClarified _PRx methods must return Clarified _PRx methods must return
consistent dataconsistent data
Clarified _SxD method definitionsClarified _SxD method definitions
Clarified system sleep state semanticsClarified system sleep state semantics
Wake events now enabled in S5Wake events now enabled in S5– Enables “Remote Power On”Enables “Remote Power On”
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 8 - ProcessorSection 8 - Processor Removed processor power state policyRemoved processor power state policy Refined processor power state descriptionsRefined processor power state descriptions ACPI 2.0 processor objects are declared under ACPI 2.0 processor objects are declared under
the \_SB scopethe \_SB scope– Device related objects may appear in the object listDevice related objects may appear in the object list– A processor driver is impliedA processor driver is implied
New processor object list definitions:New processor object list definitions: _PTC_PTC (Processor Throttling Control)(Processor Throttling Control)
– _PTC - optional object used to define a processor _PTC - optional object used to define a processor throttling control register alternative to the I/O address throttling control register alternative to the I/O address spaced-based P_BLK throttling control register spaced-based P_BLK throttling control register (P_CNT)(P_CNT)
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Processor - continuedProcessor - continued _CST (C States)_CST (C States)
– Optional object that provides an alternative method Optional object that provides an alternative method to declare the supported processor power states (C-to declare the supported processor power states (C-States).States).
– Supports additional C-States beyond C3Supports additional C-States beyond C3– Supports dynamic C-states – New notify code Supports dynamic C-states – New notify code
defined defined
_PCT_PCT (Performance Control) (Performance Control) – Optional object declares an interface that allows Optional object declares an interface that allows
OSPM to transition the processor into a performance OSPM to transition the processor into a performance statestate
– _PCT, _PSS and _PPC comprise the ACPI defined _PCT, _PSS and _PPC comprise the ACPI defined interface for controlling Intel® SpeedStepinterface for controlling Intel® SpeedStepTMTM Technology performance transitionsTechnology performance transitions
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Processor - continuedProcessor - continued_PSS_PSS (Performance Supported States)(Performance Supported States)
– Optional object conveys the total number of Optional object conveys the total number of processor performance states that a system processor performance states that a system supportssupports
_PPC_PPC (Performance Present Capabilities)(Performance Present Capabilities)– Optional object is a method that dynamically Optional object is a method that dynamically
indicates the highest number of performance indicates the highest number of performance states that is currently supported by the states that is currently supported by the platformplatform
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Processor Performance Control Processor Performance Control ASL ExampleASL Example
In this example, a uni-processor platform that has processor performance In this example, a uni-processor platform that has processor performance capabilities with support for three performance states as follows:capabilities with support for three performance states as follows:
500-MHz (8.2W) supported at any time500-MHz (8.2W) supported at any time
600-MHz (14.9W) supported only when AC powered600-MHz (14.9W) supported only when AC powered
650-MHz (21.5W) supported only when docked650-MHz (21.5W) supported only when docked
It takes no more than 500 microseconds to transition from one performance It takes no more than 500 microseconds to transition from one performance state to any other performance state.state to any other performance state.
During a performance transition, bus masters are unable to access memory During a performance transition, bus masters are unable to access memory for a maximum of 300 microsecondsfor a maximum of 300 microseconds
The _PCT - PERF_CTRL and PERF_STATUS registers are implemented as The _PCT - PERF_CTRL and PERF_STATUS registers are implemented as Functional Fixed HardwareFunctional Fixed Hardware
The following ASL objects are implemented within the system:The following ASL objects are implemented within the system:
\_SB.DOCK: Evaluates to one if system is docked, zero otherwise.\_SB.DOCK: Evaluates to one if system is docked, zero otherwise.
\_SB.AC:\_SB.AC: Evaluates to one if AC is connected, zero Evaluates to one if AC is connected, zero otherwise.otherwise.
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Performance Control Example – Performance Control Example – continuedcontinued
Processor (\_SB.CPU0, // Processor Name 1, // ACPI Processor number 0x120, // PBlk system IO address 6 ) // PBlkLen { Name(_PCT, Package () // Performance Control object { ResourceTemplate() {Register(FFixedHW, 0, 0, 0)}, // PERF_CTRL ResourceTemplate() {Register(FFixedHW, 0, 0, 0)} // PERF_STATUS }) // End of _PCT object
Name (_PSS, Package() { Package(){650, 21500, 500, 300, 0x00, 0x08}, // Performance State zero (P0) Package(){600, 14900, 500, 300, 0x01, 0x05}, // Performance State one (P1) Package(){500, 8200, 500, 300, 0x02, 0x06} // Performance State two (P2) }) // End of _PSS object
Method (_PPC, 0) // Performance Present Capabilities method {
If (\_SB.DOCK) { Return(0) // All _PSS states available (650, 600, 500). } If (\_SB.AC) { Return(1) // States 1 and 2 available (600, 500). } Else { Return(2) // State 2 available (500) } } // End of _PPC method
} // End of processor object list The platform issues a Notify(\_SB.CPU0, 0x80) to inform OSPM to re-evaluate the _PPC object when the number of available processor performance states changes.
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 9 – Wake / SleepSection 9 – Wake / SleepAdded _GTS and _BFS control method Added _GTS and _BFS control method
invocationinvocation
Added requirement for cache flush on entry Added requirement for cache flush on entry into S1into S1– Driven by Soft Error Rate Q&R guidelinesDriven by Soft Error Rate Q&R guidelines
Added detailed description of S2 and S3 Added detailed description of S2 and S3 wakeupwakeup
Added provisions for ACPI only machinesAdded provisions for ACPI only machines– Without legacy modeWithout legacy mode
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 10 – Device Section 10 – Device ObjectsObjects Updated _GTF for clarity and added expanded exampleUpdated _GTF for clarity and added expanded example
Floppy related objects relocated hereFloppy related objects relocated here– _FDI and _FDE_FDI and _FDE– _FDM Added - Switches floppy drive mode between 300 and 360 RPM_FDM Added - Switches floppy drive mode between 300 and 360 RPM
Server EnhancementsServer Enhancements
– Added GPE Block Device (ACPI0006)Added GPE Block Device (ACPI0006)
– Added Module Device (ACPI0004)Added Module Device (ACPI0004)– Resource consumer / serverResource consumer / server
– Added Memory Device (PNP0C80)Added Memory Device (PNP0C80)– Conveys memory resources in addition to the system address map Conveys memory resources in addition to the system address map
interfaces interfaces – Supports hot pluggable memory Supports hot pluggable memory
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 11 – Power SourceSection 11 – Power SourceSmart Battery UpdatesSmart Battery Updates
– Smart Battery System ManagerSmart Battery System Manager
Multiple Control Method Battery clarifications Multiple Control Method Battery clarifications and updatesand updates– Describes how to update temporarily unknown Describes how to update temporarily unknown
valuesvalues– OSPM requires accuracy so calculated data must be OSPM requires accuracy so calculated data must be
returned rather than hard coded valuesreturned rather than hard coded values– Clarifications of low, warning, and critical behavior Clarifications of low, warning, and critical behavior
including when to send notificationsincluding when to send notifications
Smart Battery-based systems Smart Battery-based systems enable the most robust OSPM enable the most robust OSPM
implementationimplementation
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 12 - ThermalSection 12 - Thermal _TZD (Thermal Zone Devices)_TZD (Thermal Zone Devices)
– This optional object evaluates to a package of device names. Each This optional object evaluates to a package of device names. Each name corresponds to a device in the ACPI namespace that is name corresponds to a device in the ACPI namespace that is associated with the thermal zoneassociated with the thermal zone
AddedAdded Notify Notify((thermal_zonethermal_zone, 0x82), 0x82)– statement can be used to inform OSPM that a change has been made to statement can be used to inform OSPM that a change has been made to
the thermal zone device liststhe thermal zone device lists (_TZD) (_TZD)
_TZP (Thermal Zone Polling)_TZP (Thermal Zone Polling)– This optional object evaluates to a This optional object evaluates to a recommendedrecommended polling frequency for polling frequency for
a thermal zonea thermal zone – Use is strongly discouragedUse is strongly discouraged– OS is not required to poll at this frequencyOS is not required to poll at this frequency
_HOT (HOT - Critical trip point)_HOT (HOT - Critical trip point)– New trip point where OSPM has enough time to enter S4New trip point where OSPM has enough time to enter S4
Use ACPI-friendly sensorsUse ACPI-friendly sensors
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 13 – Embedded Section 13 – Embedded ControllerController
Multiple clarifications throughout chapterMultiple clarifications throughout chapter
Added status code (1F) for CRC return code errorAdded status code (1F) for CRC return code error
Added description of packet error checking Added description of packet error checking (PEC - bit 7) of the protocol register (PEC - bit 7) of the protocol register
Added reference to Smart battery system Added reference to Smart battery system manager specmanager spec
Added multiple SMBus devices to the example Added multiple SMBus devices to the example ASL codeASL code
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 14 - SMBusSection 14 - SMBus New chapter for SMBusNew chapter for SMBus
Includes a completely redesigned SMBus ASL interfaceIncludes a completely redesigned SMBus ASL interface– Supports all of current SMBus features as well as the ability to Supports all of current SMBus features as well as the ability to
operate on non-EC based SMBus segmentsoperate on non-EC based SMBus segments
– Defines SMBus Op regions Defines SMBus Op regions
Definition of SMBus 1.0 device characteristics under Definition of SMBus 1.0 device characteristics under SMBus 2.0 host controllers given to SBS-IF SMBus 2.0 host controllers given to SBS-IF
– For more info see: http://www.sbs-if.orgFor more info see: http://www.sbs-if.org
SMBus 2.0 HC added (ACPI0005)SMBus 2.0 HC added (ACPI0005)
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 15 – System Address Section 15 – System Address Map InterfacesMap Interfaces
Old chapter 14Old chapter 14
EFI address map reporting EFI address map reporting mechanisms addedmechanisms added–Supports IA-64 systemsSupports IA-64 systems
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 16 - ASLSection 16 - ASL Old chapter 15Old chapter 15 Added Qword arithmetic supportAdded Qword arithmetic support Arithmetic constants now availableArithmetic constants now available Added support for String and Buffer constantsAdded support for String and Buffer constants Break is fixed – now you’ll be able use it!Break is fixed – now you’ll be able use it! Added Continue termAdded Continue term Added Switch termAdded Switch term Added ElseIF termAdded ElseIF term New Operation RegionsNew Operation Regions
– CMOSCMOS
– PCI BAR TargetPCI BAR Target
DDB handles and object references can now be passed as DDB handles and object references can now be passed as parameters to and can be returned from control methodsparameters to and can be returned from control methods
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
ASL - continuedASL - continued Processor object / thermal zone moved from \_PR to \_SBProcessor object / thermal zone moved from \_PR to \_SB Added LoadTable functionAdded LoadTable function Added data table operation region Added data table operation region Resource macro fields extendedResource macro fields extended Useful operators / macros added / enhancedUseful operators / macros added / enhanced
– ConcatResTemplate (resource template concatenation)ConcatResTemplate (resource template concatenation)– DecStr/HexStr/Int/Buff/String/Copy (explicit data type conversion)DecStr/HexStr/Int/Buff/String/Copy (explicit data type conversion)– UnicodeUnicode– Added Mid operator for strings and buffersAdded Mid operator for strings and buffers– Enhanced DerefOf operator to allow string arguments Enhanced DerefOf operator to allow string arguments – Added Mod operatorAdded Mod operator– Index operator operation clarified and now works with stringsIndex operator operation clarified and now works with strings
Reserved _T_x for ASL compiler useReserved _T_x for ASL compiler use Many syntax clarificationsMany syntax clarifications SMBus interfaces moved to section 14SMBus interfaces moved to section 14
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Section 17 - AMLSection 17 - AML
Old Section 16Old Section 16
Updated for Chapter 16 changesUpdated for Chapter 16 changes
Syntax clarificationsSyntax clarifications
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Appendix UpdatesAppendix UpdatesDevice Class specifications are now Appendix ADevice Class specifications are now Appendix A
Video Extensions now Appendix BVideo Extensions now Appendix BNew Methods Added:New Methods Added:– _GPD (Get Post Device)_GPD (Get Post Device)
– Gets video device to post at next boot (add-in PCI vs. add-in Gets video device to post at next boot (add-in PCI vs. add-in AGP)AGP)
– _SPD (Set Post Device)_SPD (Set Post Device)– Sets video device to post at next boot (add-in PCI vs. add-in Sets video device to post at next boot (add-in PCI vs. add-in
AGP)AGP)
– _VPO (Video Post Options)_VPO (Video Post Options)– Tells OS what video devices are possible to post during bootTells OS what video devices are possible to post during boot– Motherboard VGA, Add-in PCI VGA, Add-in AGPMotherboard VGA, Add-in PCI VGA, Add-in AGP
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
ACPI 2.0 Release ACPI 2.0 Release ScheduleSchedule
ACPI 2.0 Is published!ACPI 2.0 Is published!Download the spec from the Download the spec from the
teleport site:teleport site:
http://www.teleport.com/~acpihttp://www.teleport.com/~acpi
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Platform Support TimelinePlatform Support Timeline
PC2001 may be updated to require ACPI 2.0 PC2001 may be updated to require ACPI 2.0 defined interfaces once ACPI 2.0 is publisheddefined interfaces once ACPI 2.0 is published– Required interfaces / platform features will be addedRequired interfaces / platform features will be added
– Compliance date is unknownCompliance date is unknown
– We will tell you as soon as we knowWe will tell you as soon as we know
Next System Design Guide will require ACPI 2.0Next System Design Guide will require ACPI 2.0– Expected compliance date - June 2002Expected compliance date - June 2002
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
OS Support TimelineOS Support TimelineMicrosoft* will have a phased implementation Microsoft* will have a phased implementation
approachapproach– Small subset of interfaces supported in Win64 and Small subset of interfaces supported in Win64 and
BTS 2001 OS releasesBTS 2001 OS releases– General support in the OS release after BTS 2001General support in the OS release after BTS 2001– Ask Microsoft for more informationAsk Microsoft for more information
Linux support will vary with distributorLinux support will vary with distributor– Contact your Linux distributor for more informationContact your Linux distributor for more information– See also: See also: http://phobos.fachschaften.tu-muenchen.de/acpi/http://phobos.fachschaften.tu-muenchen.de/acpi/
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
What we learned today:What we learned today:The changes in ACPI moving from ACPI 1.0b to The changes in ACPI moving from ACPI 1.0b to
ACPI 2.0ACPI 2.0
The specific ACPI 2.0 changes that support or The specific ACPI 2.0 changes that support or impact mobile platformsimpact mobile platforms
How Intel products are supported using ACPI How Intel products are supported using ACPI 2.0 defined interfaces2.0 defined interfaces
The probable time frame for when ACPI 2.0 The probable time frame for when ACPI 2.0 platform support will be required including an platform support will be required including an estimated OS support timelineestimated OS support timeline
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Call To ActionCall To Action Review the ACPI 2.0 specificationReview the ACPI 2.0 specification
– http://www.teleport.com/~acpihttp://www.teleport.com/~acpi
Contact us with implementation questionsContact us with implementation questions– Use the email reflectorsUse the email reflectors
– [email protected]@hwdev.org (Windows) (Windows)– [email protected]@telelist.com (General) (General)
Include ACPI 2.0 support in your emerging platformsInclude ACPI 2.0 support in your emerging platforms– Ask your BIOS vendor for ACPI 2.0 supportAsk your BIOS vendor for ACPI 2.0 support– Request / implement devices performance state supportRequest / implement devices performance state support
Become an ACPI 2.0 AdopterBecome an ACPI 2.0 Adopter
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000BackupBackup
IntelIntel LabsLabsCopyright © 2000 Intel Corporation.
Fall 2000
Thermal Zone Object Thermal Zone Object RequirementsRequirements
1. All thermal zones must contain the _TMP object. 2. A thermal zone must define at least one trip point -_CRT, _ACx, or _PSV. 3. If _ACx is defined then an associated _ALx must be defined (e.g. defining
_AC0 requires _AL0 also be defined). 4. If _PSV is defined then either _PSL or _TZD must be defined. _PSL and
_TZD may both be defined. 5. If _PSL is defined then:
a. If a performance control register is defined (via either P_BLK or _PTC) for a processor defined in _PSL then _TC1, _TC2, and _TSP must be defined. b. If a performance control register is not defined (via either P_BLK or _PTC) for a any processor defined in _PSL then the processor must support processor performance states (i.e. the processor’s processor object must include _PCT, _PSS, and _PPC).
6. If _PSV is defined and _PSL is not defined (i.e. only _TZD is defined) then at least one device in the _TZD device list must support device performance states.
7. _SCP is optional. 8. _TZD is optional outside of the _PSV requirement outlined in #4 above.