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Intel Core (microarchitecture)From Wikipedia, the free encyclopedia

This article is about the Intel microarchitecture. For Intel processors branded as  Intel Core, including the 

Core microarchitecture based Core 2 and others not based on the Core microarchitecture, see  Intel Core . 

The Intel Core microarchitecture (previously known as the Next-Generation Micro-Architecture, or

NGMA) is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. It is based around an

updated version of the Yonah core and could be considered the latest iteration of the P6 microarchitecture, 

which traces its history back to the Pentium Pro introduced in 1995. The high power consumption and heat

intensity of NetBurst-based processors, the resulting inability to effectively increase clock speed, and other

bottlenecks such as the inefficient pipeline were the primary reasons Intel abandoned the NetBurst

microarchitecture. The Core microarchitecture was designed by the Intel Israel (IDC) team that previously

designed the Pentium M mobile processor[citation needed ]

.

The first processors that used this architecture were code-named Merom, Conroe, and Woodcrest; 

Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and

workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed,

and power consumption. Mainstream Core-based processors are branded Pentium Dual- 

Core or Pentium  and low end branded Celeron ; server and workstation Core-based processors are

branded Xeon , while desktop and mobile Core-based processors are branded as Core 2 . Despite their

names, processors sold as Core Solo / Core Duo and Core i3/i5/i7 do not actually use the Core

microarchitecture and are based on the Enhanced Pentium M and newer Nehalem / Sandy

Bridgemicroarchitectures, respectively.

Contents

[hide] 

1 Features 

2 Technology 

3 Processor cores 

o  3.1 Conroe/Merom (65 nm) 

o  3.2 Conroe-L/Merom-L 

o  3.3 Penryn/Wolfdale (45 nm) 

o  3.4 Dunnington 

4 Steppings 

o  4.1 Steppings using 65 nm process 

o  4.2 Steppings using 45 nm process 

5 System requirements 

o  5.1 Motherboard compatibility 

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o  5.2 Synchronous memory modules 

6 Chip errata 

7 See also 

8 References 

9 External links 

[edit]Features

The Core microarchitecture returned to lower clock rates and improved the usage of both available clock

cycles and power when compared with the preceding NetBurst microarchitecture of the Pentium 4 / D-

branded CPUs.[1]

 The Core microarchitecture provides more efficient decoding stages, execution

units, caches, and buses, reducing the power consumption of Core 2-branded CPUs while increasing their

processing capacity. Intel's CPUs have varied widely in power consumption according to clock rate,

architecture, and semiconductor process, shown in the CPU power dissipationtables.

Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware virtualization

support (marketed as Intel VT-x), as well as Intel 64 and SSSE3. However, Core-based processors do not

have the Hyper-Threading Technology found in Pentium 4 processors. This is because the Core

microarchitecture is a descendant of the P6 microarchitecture used by Pentium Pro, Pentium II, Pentium III,

and Pentium M.

The L1 cache size was enlarged in the Core microarchitecture, from 32KB on Pentium II/III (16 KB L1 Data

+ 16 KB L1 Instruction) to 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) on Pentium M and

Core/Core 2. It also lacks an L3 Cache found in the Gallatin core of the Pentium 4 Extreme Edition,

although an L3 Cache is present in high-end versions of Core-based Xeons. Both an L3 cache and Hyper-

threading were reintroduced in the Nehalem microarchitecture. 

[edit]Technology

Intel CPU core roadmaps from NetBurst  and P6  to Skylake  

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The Intel Core Microarchitecture was designed from the ground up, but is similar to the  Pentium

M microarchitecture in design philosophy. The Penryn pipeline is 14 stages long[2]

 — less than half

ofPrescott's, a signature feature of wide order execution cores. Penryn's successor, Nehalem has 20-24

pipeline stages.[2]

 Core's execution unit is 4 issues wide, compared to the 3-issue cores of  P6,Pentium M, 

and NetBurst microarchitectures. The new architecture is a dual core design with linked  L1 cache and

shared L2 cache engineered for maximum performance per watt and improved scalability.

One new technology included in the design is  Macro-Ops Fusion, which combines two x86 instructions into

a single micro-operation. For example, a common code sequence like a compare followed by a conditional

 jump would become a single micro-op.

Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and

a new power saving design. All components will run at minimum speed, ramping up speed dynamically as

needed (similar to AMD's Cool'n'Quiet power-saving technology, as well as Intel's

own SpeedStep technology from earlier mobile processors). This allows the chip to produce less heat, and

consume as little power as possible.

Intel Core microarchitecture.

For most Woodcrest CPUs, the front side bus (FSB) runs at 1333 MT/s; however, this is scaled down to

1066 MT/s for lower end 1.60 and 1.86 GHz variants.

[3][4]

 The Merom mobile variant was initially targeted torun at a FSB of 667 MT/s while the second wave of Meroms, supporting 800 MT/s FSB, were released as

part of the Santa Rosa platform with a different socket in May 2007. The desktop-oriented Conroe began

with models having an FSB of 800 MT/s or 1066 MT/s with a 1333 MT/s line officially launched on July 22,

2007.

The power consumption of these new processors is extremely low—average use energy consumption is to

be in the 1-2 watt range in ultra low voltage variants, with  thermal design powers (TDPs) of 65 watts for

Conroe and most Woodcrests, 80 watts for the 3.0 GHz Woodcrest, and 40 watts for the low-voltage

Woodcrest. In comparison, an AMD Opteron 875HE processor consumes 55 watts, while the energyefficient Socket AM2 line fits in the 35 watt thermal envelope (specified a different way so not directly

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comparable). Merom, the mobile variant, is listed at 35 watts TDP for standard versions and 5 watts TDP

for Ultra Low Voltage (ULV) versions.[citation needed ]

 

Previously, Intel announced that it would now focus on power efficiency, rather than raw performance.

However, at IDF in the spring of 2006, Intel advertised both. Some of the promised numbers were:

  20% more performance for Merom at the same power level (compared to Core Duo) 

  40% more performance for Conroe at 40% less power (compared to Pentium D) 

  80% more performance for Woodcrest at 35% less power (compared to the original dual-core Xeon) 

[edit]Processor cores

The processors of the Core microarchitecture can be categorized by number of cores, cache size, and

socket; each combination of these has a unique code name and product code that is used across a number

of brands. For instance, code name "Allendale" with product code 80557 has two cores, 2 MB L2 cache

and uses the desktop socket 775, but has been marketed as Celeron, Pentium, Core 2 and Xeon, each

with different sets of features enabled. Most of the mobile and desktop processors come in two variants

that differ in the size of the L2 cache, but the specific amount of L2 cache in a product can also be reduced

by disabling parts at production time. Wolfdale-DP and all quad-core processors except Dunnington QC are

multi-chip modules combining two dies. For the 65 nm processors, the same product code can be shared

by processors with different dies, but the specific information about which one is used can be derived from

the stepping.

fabcore

sMobile

Desktop, UP

Server

CL

ServerDP Server

MP

Server

Single-

Core 6

5 nm 

65

nm 

1

Merom

-L 

80537

Conroe-L 

80557

Single-Core 4

5 nm 

45nm 

1 Penryn-L 

80585

Wolfdale-CL 

80588

Dual-

Core

65 nm

65 n

m2

Merom

-2M 

80537

Mero

m 

80537

Allendale 

80557

Conroe 

80557

Conroe-

CL 

80556

Woodcrest 

80556

Tigerton-

DC 

80564

Dual-Core

45 n

m 2 Penryn-3M 

Penryn 

80576 Wolfdale-3M 

Wolfdale 

80570 Wolfdale-CL  Wolfdale-DP 

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45 nm 80577 80571 80588 80573

Quad-

Core

65 nm

65 n

m4

Kentsfiel

d 

80562

Clovertow

n 

80563

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Quad-

Core

45 nm

45 n

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Penryn

-QC 

80581

Yorkfield

-6M 

80580

Yorkfiel

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80569

Yorkfield

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80584

Harpertow

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80574

Dunningto

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Six-

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45 n

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Dunningto

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80582

[edit]Conroe/Merom (65 nm)

The original Core 2 processors are based around the same dies that can be identified as  CPUID Family 6

Model 15. Depending on their configuration and packaging, their code names are Conroe (LGA 775, 4 MB

L2 cache), Allendale (LGA 775, 2 MB L2 cache), Merom (Socket M, 4 MB L2 cache) and Kentsfield (Multi-

chip module, LGA 775, 2x4MB L2 cache). Merom and Allendale processors with limited features can be

found in Pentium Dual Core and Celeron processors, while Conroe, Allendale and Kentsfield also are sold

as Xeon processors.

Additional code names for processors based on this model are Woodcrest (LGA 771, 4 MB L2

cache), Clovertown (MCM, LGA 771, 2x4MB L2 cache) and Tigerton (MCM, Socket 604, 2x4MB L2 cache),

all of which are marketed only under the Xeon brand.

Processor Brand nameModel

(list)Cores L2 Cache Socket TDP

Merom-2M

Mobile Core 2 Duo

U7xxx

2

2 MiB

BGA479

10 W

Merom L7xxx  4 MiB 17 W

Merom

Merom-2M

T5xxx

T7xxx2-4 MiB

Socket M 

Socket P 

BGA479

35 W

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MeromMobile Core 2

ExtremeX7xxx 2 4 MiB Socket P 44 W

Merom

Celeron M  

5x0

1

512 KiBSocket M

Socket P

30 W

Merom-2M 5x5 Socket P 31 W

Merom-2M Celeron Dual-Core T1xxx 2512-1024

KiBSocket P 35 W

Merom-2M Pentium Dual-Core T2xxxT3xxx

2 1 MiB Socket P 35 W

Allendale 

Xeon  

3xxx 

2

2 MB

LGA 775  65 W

Conroe 3xxx  2-4 MB

Conroe and

Allendale

Core 2 Duo  

E4xxx

2

2 MBLGA 775

65 WE6xx0 2-4 MB

Conroe-CL E6xx5 2-4 MB LGA 771 

Conroe-XE Core 2 Extreme  X6xxx 2 4 MB LGA 775 75 W

Allendale Pentium Dual-Core E2xxx 2 1 MB LGA 775 65 W

Allendale Celeron  E1xxx 2 512 KB LGA 775 65 W

Kentsfield  Xeon   32xx  4 2x4 MiB LGA 775  95-105 W

Kentsfield Core 2 Quad   Q6xxx 4 2x4 MiB LGA 775 95-105 W

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Kentsfield

XECore 2 Extreme  QX6xxx   4 2x4 MiB LGA 775 130 W

Woodcrest 

Xeon  

51xx  2 4 MB LGA 771 65-80 W

Clovertown 

L53xx 

4 2x4 MB LGA 771

40-50 W

E53xx 80 W

X53xx120-150

W

Tigerton-DC  E72xx 2

2x4 MB

Socket

604 

80 W

Tigerton

L73xx

4

50 W

E73xx 2x2-2x4 MB 80 W

X73xx 2x4 MB 130 W

[edit]Conroe-L/Merom-L

The Conroe-L and Merom-L processors are based around the same core as Conroe and Merom, but only

contain a single core and 1 MB of L2 cache, significantly reducing production cost and power consumption

of the processor at the expense of performance compared to the dual-core version. It is used only in ultra-

low voltage Core 2 Solo U2xxx and in Celeron processors and is identified as CPUID family 6 model 22.

Processor Brand name Model (list) Cores L2 Cache Socket TDP

Merom-L Mobile Core 2 Solo  U2xxx 1 2 MiB BGA479 5.5 W

Merom-L Celeron M   5x0 1 512 KiBSocket MSocket P

27 W

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Merom-L 5x3 512-1024 KiB BGA479 5.5-10 W

Conroe-L

Celeron M  

4x0

1 512 KiB

LGA 775 35 W

Conroe-CL 4x5 LGA 771 65 W

[edit]Penryn/Wolfdale (45 nm)

In Intel's Tick-Tock cycle, the 2007/2008 "Tick" was the shrink of the Core microarchitecture to 45

nanometers as CPUID model 23. In Core 2 processors, it is used with the code names Penryn (Socket P),

Wolfdale (LGA 775) and Yorkfield (MCM, LGA 775), some of which are also sold as Celeron, Pentium and

Xeon processors. In the Xeon brand, the Wolfdale-DP and Harpertown code names are used for LGA 771based MCMs with two or four active Wolfdale cores.

The chips come in two sizes, with 6 MB and 3 MB L2 cache. The smaller version is commonly called

Penryn-3M and Wolfdale-3M as well as Yorkfield-6M, respectively. The single-core version of Penryn,

listed as Penryn-L here, is not a separate model like Merom-L but a version of the Penryn-3M model with

only one active core.

Processor Brand nameModel

(list)Cores L2 Cache Socket TDP

Penryn-L Core 2 Solo  SU3xxx 1 3 MiB BGA956 5.5 W

Penryn-3M 

Core 2 Duo

SU7xxx

2

3 MB

BGA956

10 W

SU9xxx

Penryn  

SL9xxx 

6 MiB

17 W

SP9xxx   25/28 W

Penryn-3M

P7xxx 

3 MiBSocket P 

FCBGA625 W

P8xxx 

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Penryn P9xxx  6 MiB

Penryn-3M

T6xxx 2 MiB

35 WT8xxx 3 MiB

Penryn

T9xxx 6 MiB

E8x35 6 MiB Socket P 35-55 W

Penryn-QC Core 2 Quad Q9xxx 42x3-2x6

MiBSocket P 45 W

Penryn XE

Core 2

Extreme

X9xxx 2 6 MiB

Socket P

44 W

Penryn-QC QX9xxx  4 2x6 MiB 45 W

Penryn-3M

Celeron 

T3xxx 

2 1 MiB

Socket P 35 W

SU2xxxµFC-BGA

95610 W

Penryn-L

9x0

1 1 MiB

Socket P 35 W

7x3µFC-BGA

95610 W

Penryn-3M

Pentium

T4xxx

2

1 MiB Socket P 35 W

SU4xxx

2 MiBµFC-BGA

956

10 W

Penryn-L SU2xxx 1 5.5 W

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Wolfdale-3M 

Celeron  E3xxx

2

1 MB

LGA 775

65 W

Pentium

E2210

E5xxx

2 MB

E6xxx

Core 2 Duo  

E7xxx 3 MB

Wolfdale

E8xxx

6 MB

Xeon  

31x0 45-65 W

Wolfdale-CL

30x4 1

LGA 771 

30 W

31x3 2 65 W

Yorkfield 

Xeon  

X33x0

4

2×3 – 2×6

MB

LGA 775  65 – 95 W

Yorkfield-CL X33x3 LGA 771  80 W

Yorkfield-6M

Core 2 Quad  

Q8xxx 2×2 MB

LGA 775

65 – 95 WQ9x0x  2×3 MB

Yorkfield Q9x5x  2×6 MB

Yorkfield XECore 2

ExtremeQX9xxx  2×6 MB

130 – 136

W

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QX9xx5 LGA 771 150 W

Wolfdale-DP 

Xeon

E52xx

2 6 MB LGA 771

65 W

L52xx 20-55 W

X52xx 80 W

Harpertown 

E54xx

4 2×6 MB LGA 771

80 W

L54xx 40-50 W

X54xx 120-150 W

[edit]Dunnington

The Xeon "Dunnington" processor (CPUID Family 6, model 30) is closely related to Wolfdale but comes

with six cores and an on-chip L3 cache and is designed for servers with Socket 604, so it is marketed only

as Xeon, not as Core 2.

Processor Brand name Model (list) Cores L3 Cache Socket TDP

Dunnington  Xeon

E74xx 4-6 8-16 MB

Socket 604 

90 W

L74xx 4-6 12 MB 50-65 W

X7460 6 16 MB 130 W

[edit]Steppings

The Core microarchitecture uses a number of steppings, which unlike previous microarchitectures not only

represent incremental improvements but also different sets of features like cache size and low power

modes. Most of these steppings are used across brands, typically by disabling some of the features andlimiting clock frequencies on low-end chips.

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Steppings with a reduced cache size use a separate naming scheme, which means that the releases are

no longer in alphabetic order. Additional steppings have been used in internal and engineering samples,

but are not listed in the tables.

Many of the high-end Core 2 and Xeon processors use Multi-Chip Modules of two or three chips in order toget larger cache sizes or more than two cores.

[edit]Steppings using 65 nm process

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Steppings B2/B3, E1 and G0 of model 15 (cpuid 06fx) processors are evolutionary steps of the standard

Merom/Conroe die with 4 MiB L2 cache, with the short-lived E1 stepping only being used in mobile

processors. Stepping L2 and M0 are the "Allendale" chips with just 2 MiB L2 cache, reducing production

cost and power consumption for low-end processors.

The G0 and M0 steppings improve idle power consumption in C1E state and add the C2E state in desktopprocessors. In mobile processors, all of which support C1 through C4 idle states, steppings E1, G0, and M0

add support for the Mobile Intel 965 Express (Santa Rosa) platform with Socket P, while the earlier B2 and

L2 steppings only appear for the Socket M based Mobile Intel 945 Express (Napa refresh) platform.

The model 22 stepping A1 (cpuid 10661h) marks a significant design change, with just a single core and

1 MiB L2 cache further reducing the power consumption and manufacturing cost for the low-end. Like the

earlier steppings, A1 is not used with the Mobile Intel 965 Express platform.

Steppings G0, M0 and A1 mostly replaced all older steppings in 2008. In 2009, a new stepping G2 was

introduced to replace the original stepping B2.[5] 

[edit]Steppings using 45 nm process

Mobile (Penryn) Desktop

(Wolfdale) 

Desktop

(Yorkfield

)

Server

(Wolfdal

e-

DP, Har

pertown,

Dunning

ton) 

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In the model 23 (cpuid 01067xh), Intel started marketing stepping with full (6 MiB) and reduced (3 MiB) L2

cache at the same time, and giving them identical cpuid values. All steppings have the

newSSE4.1 instructions. Stepping C1/M1 was a bug fix version of C0/M0 specifically for quad core

processors and only used in those. Stepping E0/R0 adds two new instructions (XSAVE/XRSTOR) and

replaces all earlier steppings.

In mobile processors, stepping C0/M0 is only used in the Intel Mobile 965 Express (Santa Rosa refresh) 

platform, whereas stepping E0/R0 supports the later Intel Mobile 4 Express (Montevina) platform.

Model 30 stepping A1 (cpuid 106d1h) adds an L3 cache as well as six instead of the usual two cores,

which leads to an unusually large die size of 503 mm².[6] As of February 2008, it has only found its way into

the very high-end Xeon 7400 series (Dunnington).

[edit]System requirements

[edit]Motherboard compatibilityConroe, Conroe XE and Allendale all use Socket LGA 775; however, not every motherboard is compatible

with these processors.

Supporting chipsets are:

  Intel: 865G/PE/P, 945G/GZ/GC/P/PL, 965G/P, 975X, P/G/Q965, Q963, 946GZ/PL, P3x, G3x, Q3x,

X38, X48, P4x , 5400 Express, Intel G31, G33 Chipsets

  NVIDIA: nForce4 Ultra/SLI X16 for Intel, nForce 570/590 SLI for Intel, nForce 650i Ultra/650i SLI/680i

LT SLI/680i SLI and nForce 750i SLI/780i SLI/790i SLI/790i Ultra SLI. 

  VIA: P4M800, P4M800PRO, P4M890, P4M900, PT880 Pro/Ultra, PT890.

  SiS: 662, 671, 671fx, 672, 672fx

  ATI: Radeon Xpress 200 and CrossFire Xpress 3200 for Intel

See also:  List of Intel chipsets  

The currently released Yorkfield XE model QX9770 (45 nm with 1600FSB) currently has limited

chipset compatibility - with only X38, P35 (With Overclocking) and some high-performance X48 and

P45 motherboards being compatible. BIOS updates are gradually being released to provide support for

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the new Penryn technology, and the new QX9775 is only compatible with D5400XS. The Wolfdale-3M

model E7200 also has limited compatibility (at least the Xpress 200 chipset is incompatible )[citation needed ]

.

Although a motherboard may have the required chipset to support Conroe, some motherboards based

on the above mentioned chipsets do not support Conroe. This is because all Conroe-based processorsrequire a new power delivery feature set specified in  Voltage Regulator-Down (VRD) 11.0. This

requirement is a result of Conroe's significantly lower power consumption, compared to the Pentium

4/D CPUs it is replacing. A motherboard that has both a supporting chipset and VRD 11 supports

Conroe processors, but even then some boards will need an updated BIOS to recognize Conroe's FID

(Frequency ID) and VID (Voltage ID).

[edit]Synchronous memory modules

Unlike the previous Pentium 4 and Pentium D design, the Core 2 technology sees a greater benefit

from memory running synchronously with the Front Side Bus (FSB). This means that for the Conroe

CPUs with FSB of 1066 MT/s, the ideal memory performance for DDR2 is  PC2-8500. In a few

configurations, using PC2-5300 instead of PC2-4200 can actually decrease performance. Only when

going to PC2-6400 is there a significant performance increase. While DDR2 memory models with

tighter timing specifications do improve performance, the difference in real world games and

applications is often negligible.[7]

 

Optimally, the memory bandwidth afforded should match the bandwidth of the FSB, that is to say that a

CPU with a 533 MT/s rated bus speed should be paired with RAM matching the same rated speed, for

example DDR2 533, or PC2-4200. A common myth[citation needed ] is that installing interleaved RAM will

offer double the bandwidth. This myth is false; at most the increase in bandwidth by installing

interleaved RAM is roughly 5 –10%. The AGTL+ PSB used by all NetBurst processors as well as

current and medium-term (pre-QuickPath) Core 2 processors provide a 64-bit data path. Current

chipsets provide for a couple of either DDR2 or DDR3 channels.

Matched processor and RAM ratings

Processor modelFront side

bus

Matched memory and maximumbandwidthsingle channel / dual channel 

DDR  DDR2  DDR3  

mobile: T5200, T5300, U2n00, U7n00 533 MT/s  PC-3200 PC2-4200 PC3-8500

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desktop: E6n00, E6n20, X6n00, E7n00,

Q6n00 and QX6n00

mobile: T9400, T9550, T9600, P7350,

P7450, P8400, P8600, P8700, P9500,

P9600, SP9300, SP9400, X9100

1066 MT/s

(DDR-

400)3.2 GB/s 

(DDR2-

533)4.264 GB/s PC2-8500

(DDR2-

1066)8.532 GB/s 

(DDR3-

1066)8.530 GB/s 

mobile: T5n00, T5n50, T7n00 (Socket

M), L7200, L7400667 MT/s

PC-3200

(DDR-

400)3.2 GB/s 

PC2-5300

(DDR2-

667)5.336 GB/s 

PC3-10600

(DDR3-

1333)10.670 GB/s 

desktop: E6n40, E6n50, E8nn0, Q9nn0,

QX6n50, QX96501333 MT/s

mobile: T5n70, T6400, T7n00 (Socket

P), L7300, L7500, X7n00, T8n00,

T9300, T9500, X9000

desktop: E4n00, Pentium E2nn0,

Pentium E5nn0, Celeron 4n0, E3n00

800 MT/s

PC-3200

(DDR-

400)3.2 GB/s 

PC-3200

(DDR-

400)3.2 GB/s 

PC2-6400

(DDR2-

800)6.400 GB/s PC2-8500

(DDR2-

1066)8.532 GB/s 

PC3-6400

(DDR3-

800)6.400 GB/s 

PC3-12800

(DDR3-

1600)12.800 GB/s 

desktop: QX9770, QX9775 1600 MT/s

On jobs requiring large amounts of memory access, the quad-core Core 2 processors can benefit

significantly[8]

 from using a PC2-8500 memory, which runs exactly the same speed as the CPU's FSB;

this is not an officially supported configuration, but a number of motherboards offer it.

The Core 2 processor does not require the use of DDR2. While the Intel 975X and P965 chipsets

require this memory, some motherboards and chipsets support both the Core 2 and DDR memory.

When using DDR memory, performance may be reduced because of the lower available memory

bandwidth.

[edit]Chip errata

The Core 2 memory management unit (MMU) in X6800, E6000 and E4000 processors does not

operate to previous specifications implemented in previous generations of x86 hardware. This may

cause problems, many of them serious security and stability issues, with existing operating

system software. Intel's documentation states that their programming manuals will be updated "in the

coming months" with information on recommended methods of managing the translation lookaside

buffer (TLB) for Core 2 to avoid issues, and admits that, "in rare instances, improper TLB invalidation

may result in unpredictable system behavior, such as hangs or incorrect data."[9]

 

Among the issues noted:

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  Non-execute bit is shared across the cores.

  Floating point instruction non-coherencies.

  Allowed memory corruptions outside of the range of permitted writing for a process by running

common instruction sequences.

Intel errata Ax39, Ax43, Ax65, Ax79, Ax90, Ax99 are said to be particularly serious.[10]

 39, 43, 79,

which can cause unpredictable behavior or system hang, have been fixed in recent steppings. 

Among those who have noted the errata to be particularly serious are  OpenBSD's Theo de

Raadt[11]

 and DragonFly BSD's Matthew Dillon.[12]

 Taking a contrasting view was Linus Torvalds, 

calling the TLB issue "totally insignificant", adding, "The biggest problem is that Intel should just have

documented the TLB behavior better."[13]

 

Microsoft has issued update KB936357 to address the errata by microcode update,[14]

 with no

performance penalty. BIOS updates are also available to fix the issue.