Intel® PXA255 ProcessorDeveloper’s Manual

January, 2004

Order Number: 278693-002

ii Intel® PXA255 Processor Developer’s Manual

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Contents

Contents

1 Introduction...................................................................................................................................1-1

1.1 Intel XScale® Microarchitecture Features.........................................................................1-11.2 System Integration Features..............................................................................................1-1

1.2.1 Memory Controller ................................................................................................1-21.2.2 Clocks and Power Controllers...............................................................................1-21.2.3 Universal Serial Bus (USB) Client.........................................................................1-21.2.4 DMA Controller (DMAC) .......................................................................................1-31.2.5 LCD Controller ......................................................................................................1-31.2.6 AC97 Controller ....................................................................................................1-31.2.7 Inter-IC Sound (I2S) Controller .............................................................................1-31.2.8 Multimedia Card (MMC) Controller .......................................................................1-31.2.9 Fast Infrared (FIR) Communication Port...............................................................1-31.2.10 Synchronous Serial Protocol Controller (SSPC)...................................................1-41.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit....................................................1-41.2.12 GPIO.....................................................................................................................1-41.2.13 UARTs ..................................................................................................................1-41.2.14 Real-Time Clock (RTC).........................................................................................1-51.2.15 OS Timers.............................................................................................................1-51.2.16 Pulse-Width Modulator (PWM) .............................................................................1-51.2.17 Interrupt Control ....................................................................................................1-51.2.18 Network Synchronous Serial Protocol Port...........................................................1-5

2 System Architecture .....................................................................................................................2-1

2.1 Overview............................................................................................................................2-12.2 Intel XScale® Microarchitecture Implementation Options.................................................2-2

2.2.1 Coprocessor 7 Register 4 - PSFS Bit ...................................................................2-22.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring.....................................2-32.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management......................2-32.2.4 Coprocessor 15 Register 0 - ID Register Definition ..............................................2-32.2.5 Coprocessor 15 Register 1 - P-Bit ........................................................................2-4

2.3 I/O Ordering .......................................................................................................................2-52.4 Semaphores ......................................................................................................................2-52.5 Interrupts............................................................................................................................2-52.6 Reset .................................................................................................................................2-62.7 Internal Registers...............................................................................................................2-72.8 Selecting Peripherals vs. General Purpose I/O .................................................................2-72.9 Power on Reset and Boot Operation .................................................................................2-82.10 Power Management...........................................................................................................2-82.11 Pin List ...............................................................................................................................2-82.12 Memory Map....................................................................................................................2-182.13 System Architecture Register Summary..........................................................................2-21

3 Clocks and Power Manager .........................................................................................................3-1

3.1 Clock Manager Introduction...............................................................................................3-13.2 Power Manager Introduction..............................................................................................3-23.3 Clock Manager...................................................................................................................3-2

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3.3.1 32.768 kHz Oscillator............................................................................................3-43.3.2 3.6864 MHz Oscillator ..........................................................................................3-43.3.3 Core Phase Locked Loop .....................................................................................3-43.3.4 95.85 MHz Peripheral Phase Locked Loop ..........................................................3-53.3.5 147.46 MHz Peripheral Phase Locked Loop ........................................................3-53.3.6 Clock Gating .........................................................................................................3-6

3.4 Resets and Power Modes..................................................................................................3-63.4.1 Hardware Reset....................................................................................................3-63.4.2 Watchdog Reset ...................................................................................................3-73.4.3 GPIO Reset ..........................................................................................................3-83.4.4 Run Mode .............................................................................................................3-93.4.5 Turbo Mode ..........................................................................................................3-93.4.6 Idle Mode............................................................................................................3-103.4.7 Frequency Change Sequence............................................................................3-113.4.8 33-MHz Idle Mode ..............................................................................................3-133.4.9 Sleep Mode.........................................................................................................3-153.4.10 Power Mode Summary .......................................................................................3-20

3.5 Power Manager Registers ...............................................................................................3-223.5.1 Power Manager Control Register (PMCR) .........................................................3-233.5.2 Power Manager General Configuration Register (PCFR)...................................3-243.5.3 Power Manager Wake-Up Enable Register (PWER)..........................................3-253.5.4 Power Manager Rising-Edge Detect Enable Register (PRER) ..........................3-263.5.5 Power Manager Falling-Edge Detect Enable Register (PFER) ..........................3-273.5.6 Power Manager GPIO Edge Detect Status Register (PEDR).............................3-283.5.7 Power Manager Sleep Status Register (PSSR) .................................................3-293.5.8 Power Manager Scratch Pad Register (PSPR) ..................................................3-303.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)...............3-313.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2).........3-313.5.11 Reset Controller Status Register (RCSR)...........................................................3-33

3.6 Clocks Manager Registers...............................................................................................3-343.6.1 Core Clock Configuration Register (CCCR) .......................................................3-343.6.2 Clock Enable Register (CKEN)...........................................................................3-363.6.3 Oscillator Configuration Register (OSCC) ..........................................................3-38

3.7 Coprocessor 14: Clock and Power Management ............................................................3-383.7.1 Core Clock Configuration Register (CCLKCFG).................................................3-393.7.2 Power Mode Register (PWRMODE)...................................................................3-40

3.8 External Hardware Considerations ..................................................................................3-403.8.1 Power-On-Reset Considerations ........................................................................3-403.8.2 Power Supply Connectivity .................................................................................3-403.8.3 Driving the Crystal Pins from an External Clock Source.....................................3-413.8.4 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator...............3-41

3.9 Clocks and Power Manager Register Summary..............................................................3-413.9.1 Clocks Manager Register Locations ...................................................................3-413.9.2 Power Manager Register Summary....................................................................3-41

4 System Integration Unit ................................................................................................................4-1

4.1 General-Purpose I/O..........................................................................................................4-14.1.1 GPIO Operation ....................................................................................................4-14.1.2 GPIO Alternate Functions.....................................................................................4-24.1.3 GPIO Register Definitions.....................................................................................4-6

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4.2 Interrupt Controller...........................................................................................................4-204.2.1 Interrupt Controller Operation .............................................................................4-204.2.2 Interrupt Controller Register Definitions..............................................................4-21

4.3 Real-Time Clock (RTC) ...................................................................................................4-284.3.1 Real-Time Clock Operation.................................................................................4-284.3.2 RTC Register Definitions ....................................................................................4-294.3.3 Trim Procedure ...................................................................................................4-32

4.4 Operating System (OS) Timer .........................................................................................4-344.4.1 Watchdog Timer Operation.................................................................................4-354.4.2 OS Timer Register Definitions ............................................................................4-35

4.5 Pulse Width Modulator.....................................................................................................4-384.5.1 Pulse Width Modulator Operation .......................................................................4-384.5.2 Register Descriptions..........................................................................................4-404.5.3 Pulse Width Modulator Output Wave Example...................................................4-43

4.6 System Integration Unit Register Summary.....................................................................4-444.6.1 GPIO Register Locations ....................................................................................4-444.6.2 Interrupt Controller Register Locations ...............................................................4-454.6.3 Real-Time Clock Register Locations...................................................................4-454.6.4 OS Timer Register Locations..............................................................................4-454.6.5 Pulse Width Modulator Register Locations.........................................................4-46

5 DMA Controller .............................................................................................................................5-1

5.1 DMA Description................................................................................................................5-15.1.1 DMAC Channels ...................................................................................................5-25.1.2 Signal Descriptions ...............................................................................................5-25.1.3 DMA Channel Priority Scheme .............................................................................5-35.1.4 DMA Descriptors...................................................................................................5-55.1.5 Channel States .....................................................................................................5-85.1.6 Read and Write Order...........................................................................................5-95.1.7 Byte Transfer Order ..............................................................................................5-95.1.8 Trailing Bytes ......................................................................................................5-10

5.2 Transferring Data.............................................................................................................5-115.2.1 Servicing Internal Peripherals .............................................................................5-115.2.2 Quick Reference for DMA Programming ............................................................5-135.2.3 Servicing Companion Chips and External Peripherals .......................................5-145.2.4 Memory-to-Memory Moves.................................................................................5-16

5.3 DMAC Registers ..............................................................................................................5-175.3.1 DMA Interrupt Register (DINT) ...........................................................................5-175.3.2 DMA Channel Control/Status Register (DCSRx) ................................................5-175.3.3 DMA Request to Channel Map Registers (DRCMRx) ........................................5-205.3.4 DMA Descriptor Address Registers (DDADRx) ..................................................5-205.3.5 DMA Source Address Registers .........................................................................5-215.3.6 DMA Target Address Registers (DTADRx).........................................................5-225.3.7 DMA Command Registers (DCMDx) ..................................................................5-23

5.4 Examples .........................................................................................................................5-265.5 DMA Controller Register Summary .................................................................................5-28

6 Memory Controller ........................................................................................................................6-1

6.1 Overview............................................................................................................................6-16.2 Functional Description .......................................................................................................6-2

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6.2.1 SDRAM Interface Overview..................................................................................6-26.2.2 Static Memory Interface / Variable Latency I/O Interface .....................................6-36.2.3 16-Bit PC Card / Compact Flash Interface ...........................................................6-4

6.3 Memory System Examples ................................................................................................6-46.4 Memory Accesses .............................................................................................................6-7

6.4.1 Reads and Writes .................................................................................................6-86.4.2 Aborts and Nonexistent Memory ..........................................................................6-8

6.5 Synchronous DRAM Memory Interface .............................................................................6-86.5.1 SDRAM MDCNFG Register (MDCNFG................................................................6-86.5.2 SDRAM Mode Register Set Configuration Register (MDMRS) ..........................6-126.5.3 SDRAM MDREFR Register (MDREFR) .............................................................6-146.5.4 Fixed-Delay or Return-Clock Data Latching .......................................................6-176.5.5 SDRAM Memory Options ...................................................................................6-186.5.6 SDRAM Command Overview .............................................................................6-276.5.7 SDRAM Waveforms............................................................................................6-28

6.6 Synchronous Static Memory Interface.............................................................................6-326.6.1 Synchronous Static Memory Configuration Register (SXCNFG)........................6-326.6.2 Synchronous Static Memory Mode Register Set Configuration

Register (SXMRS) ..............................................................................................6-376.6.3 Synchronous Static Memory Timing Diagrams...................................................6-386.6.4 Non-SDRAM Timing SXMEM Operation ............................................................6-39

6.7 Asynchronous Static Memory ..........................................................................................6-426.7.1 Static Memory Interface......................................................................................6-426.7.2 Static Memory SA-1111 Compatibility Configuration Register (SA1111CR) ......6-446.7.3 Asynchronous Static Memory Control Registers (MSCx) ...................................6-466.7.4 ROM Interface ....................................................................................................6-506.7.5 SRAM Interface Overview ..................................................................................6-536.7.6 Variable Latency I/O (VLIO) Interface Overview.................................................6-556.7.7 FLASH Memory Interface ...................................................................................6-58

6.8 16-Bit PC Card/Compact Flash Interface ........................................................................6-606.8.1 Expansion Memory Timing Configuration Register ............................................6-606.8.2 Expansion Memory Configuration Register (MECR) ..........................................6-636.8.3 16-Bit PC Card Overview....................................................................................6-646.8.4 External Logic for 16-Bit PC Card Implementation .............................................6-666.8.5 Expansion Card Interface Timing Diagrams and Parameters ............................6-69

6.9 Companion Chip Interface...............................................................................................6-706.9.1 Alternate Bus Master Mode ................................................................................6-72

6.10 Options and Settings for Boot Memory............................................................................6-746.10.1 Alternate Booting ................................................................................................6-746.10.2 Boot Time Defaults .............................................................................................6-746.10.3 Memory Interface Reset and Initialization...........................................................6-78

6.11 Hardware, Watchdog, or Sleep Reset Operation ............................................................6-796.12 GPIO Reset Procedure....................................................................................................6-816.13 Memory Controller Register Summary ............................................................................6-81

7 LCD Controller..............................................................................................................................7-1

7.1 Overview............................................................................................................................7-17.1.1 Features................................................................................................................7-27.1.2 Pin Descriptions....................................................................................................7-4

7.2 LCD Controller Operation ..................................................................................................7-4

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7.2.1 Enabling the Controller .........................................................................................7-47.2.2 Disabling the Controller ........................................................................................7-57.2.3 Resetting the Controller ........................................................................................7-5

7.3 Detailed Module Descriptions ............................................................................................7-57.3.1 Input FIFOs ...........................................................................................................7-57.3.2 Lookup Palette ......................................................................................................7-67.3.3 Temporal Modulated Energy Distribution (TMED) Dithering.................................7-67.3.4 Output FIFOs ........................................................................................................7-87.3.5 LCD Controller Pin Usage ....................................................................................7-87.3.6 DMA......................................................................................................................7-9

7.4 LCD External Palette and Frame Buffers ........................................................................7-107.4.1 External Palette Buffer ........................................................................................7-107.4.2 External Frame Buffer.........................................................................................7-11

7.5 Functional Timing ............................................................................................................7-147.6 Register Descriptions.......................................................................................................7-17

7.6.1 LCD Controller Control Register 0 (LCCR0) .......................................................7-187.6.2 LCD Controller Control Register 1 (LCCR1) .......................................................7-247.6.3 LCD Controller Control Register 2 (LCCR2) .......................................................7-267.6.4 LCD Controller Control Register 3 (LCCR3) .......................................................7-287.6.5 LCD Controller DMA ...........................................................................................7-327.6.6 LCD DMA Frame Branch Registers (FBRx) .......................................................7-377.6.7 LCD Controller Status Register (LCSR)..............................................................7-387.6.8 LCD Controller Interrupt ID Register (LIIDR) ......................................................7-417.6.9 TMED RGB Seed Register (TRGBR) .................................................................7-427.6.10 TMED Control Register (TCR) ............................................................................7-43

7.7 LCD Controller Register Summary ..................................................................................7-44

8 Synchronous Serial Port Controller ..............................................................................................8-1

8.1 Overview............................................................................................................................8-18.2 Signal Description..............................................................................................................8-1

8.2.1 External Interface to Synchronous Serial Peripherals ..........................................8-18.3 Functional Description .......................................................................................................8-2

8.3.1 Data Transfer ........................................................................................................8-28.4 Data Formats .....................................................................................................................8-2

8.4.1 Serial Data Formats for Transfer to/from Peripherals ...........................................8-28.4.2 Parallel Data Formats for FIFO Storage ...............................................................8-6

8.5 FIFO Operation and Data Transfers ..................................................................................8-78.5.1 Using Programmed I/O Data Transfers ................................................................8-78.5.2 Using DMA Data Transfers ...................................................................................8-7

8.6 Baud-Rate Generation.......................................................................................................8-78.7 SSP Serial Port Registers..................................................................................................8-8

8.7.1 SSP Control Register 0 (SSCR0) .........................................................................8-88.7.2 SSP Control Register 1 (SSCR1) .......................................................................8-118.7.3 SSP Data Register (SSDR) ................................................................................8-158.7.4 SSP Status Register (SSSR)..............................................................................8-16

8.8 SSP Controller Register Summary ..................................................................................8-19

9 I2C Bus Interface Unit ...................................................................................................................9-1

9.1 Overview............................................................................................................................9-19.2 Signal Description..............................................................................................................9-1

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9.3 Functional Description .......................................................................................................9-19.3.1 Operational Blocks................................................................................................9-39.3.2 I2C Bus Interface Modes .....................................................................................9-39.3.3 Start and Stop Bus States ....................................................................................9-4

9.4 I2C Bus Operation .............................................................................................................9-79.4.1 Serial Clock Line (SCL) Generation......................................................................9-79.4.2 Data and Addressing Management ......................................................................9-79.4.3 I2C Acknowledge..................................................................................................9-89.4.4 Polling ...................................................................................................................9-99.4.5 Arbitration .............................................................................................................9-99.4.6 Master Operations ..............................................................................................9-129.4.7 Slave Operations ................................................................................................9-149.4.8 General Call Address..........................................................................................9-16

9.5 Slave Mode Programming Examples ..............................................................................9-189.5.1 Initialize Unit .......................................................................................................9-189.5.2 Write n Bytes as a Slave.....................................................................................9-189.5.3 Read n Bytes as a Slave ....................................................................................9-18

9.6 Master Programming Examples ......................................................................................9-199.6.1 Initialize Unit .......................................................................................................9-199.6.2 Write 1 Byte as a Master ....................................................................................9-199.6.3 Read 1 Byte as a Master ....................................................................................9-209.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master..............................9-209.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort ..................................9-21

9.7 Glitch Suppression Logic .................................................................................................9-219.8 Reset Conditions .............................................................................................................9-219.9 Register Definitions..........................................................................................................9-22

9.9.1 I2C Bus Monitor Register (IBMR) .......................................................................9-229.9.2 I2C Data Buffer Register (IDBR).........................................................................9-229.9.3 I2C Control Register (ICR)..................................................................................9-239.9.4 I2C Status Register (ISR) ...................................................................................9-259.9.5 I2C Slave Address Register (ISAR)....................................................................9-27

10 UARTs ........................................................................................................................................10-1

10.1 Feature List......................................................................................................................10-110.2 Overview..........................................................................................................................10-2

10.2.1 Full Function UART ............................................................................................10-210.2.2 Bluetooth UART..................................................................................................10-210.2.3 Standard UART ..................................................................................................10-210.2.4 Compatibility with 16550.....................................................................................10-2

10.3 Signal Descriptions ..........................................................................................................10-310.4 UART Operational Description ........................................................................................10-4

10.4.1 Reset ..................................................................................................................10-510.4.2 Internal Register Descriptions.............................................................................10-510.4.3 FIFO Interrupt Mode Operation ........................................................................10-2110.4.4 FIFO Polled Mode Operation............................................................................10-2210.4.5 DMA Requests..................................................................................................10-2210.4.6 Slow Infrared Asynchronous Interface..............................................................10-23

10.5 UART Register Summary ..............................................................................................10-2610.5.1 UART Register Differences ..............................................................................10-28

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11 Fast Infrared Communication Port..............................................................................................11-1

11.1 Signal Description............................................................................................................11-111.2 FICP Operation................................................................................................................11-1

11.2.1 4PPM Modulation ...............................................................................................11-211.2.2 Frame Format .....................................................................................................11-311.2.3 Address Field ......................................................................................................11-311.2.4 Control Field .......................................................................................................11-311.2.5 Data Field ...........................................................................................................11-311.2.6 CRC Field ...........................................................................................................11-411.2.7 Baud Rate Generation ........................................................................................11-411.2.8 Receive Operation ..............................................................................................11-411.2.9 Transmit Operation .............................................................................................11-511.2.10 Transmit and Receive FIFOs..............................................................................11-611.2.11 Trailing or Error Bytes in the Receive FIFO........................................................11-7

11.3 FICP Register Definitions ................................................................................................11-711.3.1 FICP Control Register 0 (ICCR0)........................................................................11-811.3.2 FICP Control Register 1 (ICCR1)......................................................................11-1011.3.3 FICP Control Register 2 (ICCR2)......................................................................11-1111.3.4 FICP Data Register (ICDR)...............................................................................11-1211.3.5 FICP Status Register 0 (ICSR0) .......................................................................11-1311.3.6 FICP Status Register 1 (ICSR1) .......................................................................11-15

11.4 FICP Register Summary................................................................................................11-16

12 USB Device Controller................................................................................................................12-1

12.1 USB Overview .................................................................................................................12-112.2 Device Configuration .......................................................................................................12-212.3 USB Protocol ...................................................................................................................12-2

12.3.1 Signalling Levels .................................................................................................12-312.3.2 Bit Encoding........................................................................................................12-312.3.3 Field Formats ......................................................................................................12-412.3.4 Packet Formats...................................................................................................12-512.3.5 Transaction Formats ...........................................................................................12-612.3.6 UDC Device Requests ........................................................................................12-812.3.7 Configuration ......................................................................................................12-9

12.4 UDC Hardware Connection ...........................................................................................12-1012.4.1 Self-Powered Device ........................................................................................12-1012.4.2 Bus-Powered Devices ......................................................................................12-12

12.5 UDC Operation ..............................................................................................................12-1212.5.1 Case 1: EP0 Control Read ...............................................................................12-1212.5.2 Case 2: EP0 Control Read with a Premature Status Stage..............................12-1312.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage............12-1412.5.4 Case 4: EP0 No Data Command ......................................................................12-1512.5.5 Case 5: EP1 Data Transmit (BULK-IN).............................................................12-1512.5.6 Case 6: EP2 Data Receive (BULK-OUT)..........................................................12-1612.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)...........................................12-1712.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)........................................12-1812.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN) .................................................12-2012.5.10 Case 10: RESET Interrupt ................................................................................12-2012.5.11 Case 11: SUSPEND Interrupt...........................................................................12-2112.5.12 Case 12: RESUME Interrupt.............................................................................12-21

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12.6 UDC Register Definitions...............................................................................................12-2112.6.1 UDC Control Register (UDCCR).......................................................................12-2212.6.2 UDC Control Function Register (UDCCFR)......................................................12-2412.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0) .......................................12-2512.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)................................12-2712.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)................................12-2912.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)................................12-3112.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)................................12-3212.6.8 UDC Endpoint x Control/Status Register (UDCCS5/10/15)..............................12-3412.6.9 UDC Interrupt Control Register 0 (UICR0) .......................................................12-3612.6.10 UDC Interrupt Control Register 1 (UICR1) .......................................................12-3812.6.11 UDC Status/Interrupt Register 0 (USIR0) .........................................................12-3912.6.12 UDC Status/Interrupt Register 1 (USIR1) .........................................................12-4112.6.13 UDC Frame Number High Register (UFNHR) ..................................................12-4212.6.14 UDC Frame Number Low Register (UFNLR) ...................................................12-4412.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14) ...........................................12-4412.6.16 UDC Endpoint 0 Data Register (UDDR0) .........................................................12-4512.6.17 UDC Endpoint x Data Register (UDDR1/6/11) .................................................12-4612.6.18 UDC Endpoint x Data Register (UDDR2/7/12) .................................................12-4612.6.19 UDC Endpoint x Data Register (UDDR3/8/13) .................................................12-4712.6.20 UDC Endpoint x Data Register (UDDR4/9/14) .................................................12-4712.6.21 UDC Endpoint x Data Register (UDDR5/10/15) ...............................................12-48

12.7 USB Device Controller Register Summary ....................................................................12-48

13 AC’97 Controller Unit..................................................................................................................13-1

13.1 Overview..........................................................................................................................13-113.2 Feature List......................................................................................................................13-113.3 Signal Description............................................................................................................13-2

13.3.1 Signal Configuration Steps .................................................................................13-213.3.2 Example AC-link .................................................................................................13-2

13.4 AC-link Digital Serial Interface Protocol...........................................................................13-313.4.1 AC-link Audio Output Frame (SDATA_OUT)......................................................13-413.4.2 AC-link Audio Input Frame (SDATA_IN).............................................................13-8

13.5 AC-link Low Power Mode ..............................................................................................13-1213.5.1 Powering Down the AC-link ..............................................................................13-1213.5.2 Waking up the AC-link ......................................................................................13-13

13.6 ACUNIT Operation.........................................................................................................13-1413.6.1 Initialization .......................................................................................................13-1513.6.2 Trailing bytes ....................................................................................................13-1713.6.3 Operational Flow for Accessing CODEC Registers..........................................13-17

13.7 Clocks and Sampling Frequencies ................................................................................13-1713.8 Functional Description ...................................................................................................13-18

13.8.1 FIFOs................................................................................................................13-1813.8.2 Interrupts...........................................................................................................13-1913.8.3 Registers...........................................................................................................13-19

13.9 AC’97 Register Summary ..............................................................................................13-35

14 Inter-Integrated-Circuit Sound (I2S) Controller...........................................................................14-1

14.1 Overview..........................................................................................................................14-114.2 Signal Descriptions ..........................................................................................................14-2

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14.3 Controller Operation ........................................................................................................14-314.3.1 Initialization .........................................................................................................14-314.3.2 Disabling and Enabling Audio Replay.................................................................14-414.3.3 Disabling and Enabling Audio Record ................................................................14-414.3.4 Transmit FIFO Errors ..........................................................................................14-514.3.5 Receive FIFO Errors ...........................................................................................14-514.3.6 Trailing Bytes ......................................................................................................14-5

14.4 Serial Audio Clocks and Sampling Frequencies..............................................................14-514.5 Data Formats ...................................................................................................................14-6

14.5.1 FIFO and Memory Format ..................................................................................14-614.5.2 I2S and MSB-Justified Serial Audio Formats......................................................14-6

14.6 Registers..........................................................................................................................14-814.6.1 Serial Audio Controller Global Control Register (SACR0) ..................................14-814.6.2 Serial Audio Controller I2S/MSB-Justified Control Register (SACR1) ..............14-1014.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)................14-1114.6.4 Serial Audio Clock Divider Register (SADIV)....................................................14-1214.6.5 Serial Audio Interrupt Clear Register (SAICR)..................................................14-1314.6.6 Serial Audio Interrupt Mask Register (SAIMR) .................................................14-1414.6.7 Serial Audio Data Register (SADR) ..................................................................14-14

14.7 Interrupts........................................................................................................................14-1514.8 I2S Controller Register Summary ..................................................................................14-15

15 MultiMediaCard Controller..........................................................................................................15-1

15.1 Overview..........................................................................................................................15-115.2 MMC Controller Functional Description ...........................................................................15-4

15.2.1 Signal Description ...............................................................................................15-615.2.2 MMC Controller Reset ........................................................................................15-615.2.3 Card Initialization Sequence ...............................................................................15-615.2.4 MMC and SPI Modes..........................................................................................15-615.2.5 Error Detection....................................................................................................15-815.2.6 Interrupts.............................................................................................................15-815.2.7 Clock Control ......................................................................................................15-915.2.8 Data FIFOs .......................................................................................................15-10

15.3 Card Communication Protocol.......................................................................................15-1215.3.1 Basic, No Data, Command and Response Sequence......................................15-1315.3.2 Data Transfer ....................................................................................................15-1315.3.3 Busy Sequence.................................................................................................15-1615.3.4 SPI Functionality ...............................................................................................15-17

15.4 MultiMediaCard Controller Operation ............................................................................15-1715.4.1 Start and Stop Clock.........................................................................................15-1715.4.2 Initialize .............................................................................................................15-1715.4.3 Enabling SPI Mode ...........................................................................................15-1715.4.4 No Data Command and Response Sequence..................................................15-1815.4.5 Erase ................................................................................................................15-1815.4.6 Single Data Block Write ....................................................................................15-1815.4.7 Single Block Read ............................................................................................15-1915.4.8 Multiple Block Write ..........................................................................................15-2015.4.9 Multiple Block Read ..........................................................................................15-2015.4.10 Stream Write .....................................................................................................15-2115.4.11 Stream Read.....................................................................................................15-21

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15.5 MMC Controller Registers .............................................................................................15-2215.5.1 MMC_STRPCL Register...................................................................................15-2215.5.2 MMC_Status Register (MMC_STAT) ...............................................................15-2315.5.3 MMC_CLKRT Register (MMC_CLKRT) ...........................................................15-2415.5.4 MMC_SPI Register (MMC_SPI) .......................................................................15-2515.5.5 MMC_CMDAT Register (MMC_CMDAT) .........................................................15-2615.5.6 MMC_RESTO Register (MMC_RESTO) ..........................................................15-2715.5.7 MMC_RDTO Register (MMC_RDTO) ..............................................................15-2815.5.8 MMC_BLKLEN Register (MMC_BLKLEN) .......................................................15-2915.5.9 MMC_NOB Register (MMC_NOB) ...................................................................15-2915.5.10 MMC_PRTBUF Register (MMC_PRTBUF) ......................................................15-3015.5.11 MMC_I_MASK Register (MMC_I_MASK) ........................................................15-3015.5.12 MMC_I_REG Register (MMC_I_REG) .............................................................15-3115.5.13 MMC_CMD Register (MMC_CMD) ..................................................................15-3315.5.14 MMC_ARGH Register (MMC_ARGH) ..............................................................15-3515.5.15 MMC_ARGL Register (MMC_ARGL) ...............................................................15-3515.5.16 MMC_RES FIFO...............................................................................................15-3615.5.17 MMC_RXFIFO FIFO.........................................................................................15-3615.5.18 MMC_TXFIFO FIFO .........................................................................................15-37

15.6 MultiMediaCard Controller Register Summary ..............................................................15-37

16 Network SSP Serial Port ............................................................................................................16-1

16.1 Overview..........................................................................................................................16-116.2 Features...........................................................................................................................16-116.3 Signal Description............................................................................................................16-216.4 Operation .........................................................................................................................16-2

16.4.1 Processor and DMA FIFO Access......................................................................16-216.4.2 Trailing Bytes in the Receive FIFO .....................................................................16-316.4.3 Data Formats ......................................................................................................16-316.4.4 Hi-Z on SSPTXD...............................................................................................16-1316.4.5 FIFO Operation.................................................................................................16-1716.4.6 Baud-Rate Generation......................................................................................16-17

16.5 Register Descriptions.....................................................................................................16-1816.5.1 SSP Control Register 0 (SSCR0) .....................................................................16-1816.5.2 SSP Control Register 1 (SSCR1) .....................................................................16-2016.5.3 SSP Programmable Serial Protocol Register (SSPSP)....................................16-2216.5.4 SSP Time Out Register (SSTO) .......................................................................16-2416.5.5 SSP Interrupt Test Register (SSITR)................................................................16-2416.5.6 SSP Status Register (SSSR)............................................................................16-2516.5.7 SSP Data Register (SSDR) ..............................................................................16-28

16.6 Network SSP Serial Port Register Summary.................................................................16-29

17 Hardware UART .........................................................................................................................17-1

17.1 Overview..........................................................................................................................17-117.2 Features...........................................................................................................................17-117.3 Signal Descriptions ..........................................................................................................17-317.4 Operation .........................................................................................................................17-3

17.4.1 Reset ..................................................................................................................17-417.4.2 FIFO Operation...................................................................................................17-417.4.3 Autoflow Control .................................................................................................17-7

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17.4.4 Auto-Baud-Rate Detection ..................................................................................17-717.4.5 Slow Infrared Asynchronous Interface................................................................17-8

17.5 Register Descriptions.....................................................................................................17-1017.5.1 Receive Buffer Register (RBR) .........................................................................17-1017.5.2 Transmit Holding Register (THR)......................................................................17-1017.5.3 Divisor Latch Registers (DLL and DLH)............................................................17-1017.5.4 Interrupt Enable Register (IER) ........................................................................17-1117.5.5 Interrupt Identification Register (IIR) .................................................................17-1317.5.6 FIFO Control Register (FCR)............................................................................17-1517.5.7 Receive FIFO Occupancy Register (FOR) .......................................................17-1617.5.8 Auto-Baud Control Register (ABR) ...................................................................17-1717.5.9 Auto-Baud Count Register (ACR).....................................................................17-1717.5.10 Line Control Register (LCR)..............................................................................17-1817.5.11 Line Status Register (LSR) ...............................................................................17-1917.5.12 Modem Control Register (MCR) .......................................................................17-2117.5.13 Modem Status Register (MSR) .........................................................................17-2317.5.14 Scratchpad Register (SCR) ..............................................................................17-2417.5.15 Infrared Selection Register (ISR) ......................................................................17-24

17.6 Hardware UART Register Summary..............................................................................17-25

Figures2-1 Block Diagram ...........................................................................................................................2-22-2 Memory Map (Part One) — From 0x8000_0000 to 0xFFFF FFFF..........................................2-192-3 Memory Map (Part Two) — From 0x0000_0000 to 0x7FFF FFFF ..........................................2-203-1 Clocks Manager Block Diagram ................................................................................................3-34-1 General-Purpose I/O Block Diagram .........................................................................................4-24-2 Interrupt Controller Block Diagram ..........................................................................................4-214-3 PWMn Block Diagram..............................................................................................................4-394-4 Basic Pulse Width Waveform ..................................................................................................4-435-1 DMAC Block Diagram................................................................................................................5-15-2 DREQ timing requirements........................................................................................................5-35-3 No-Descriptor Fetch Mode Channel State.................................................................................5-65-4 Descriptor Fetch Mode Channel State.......................................................................................5-85-5 Little Endian Transfers.............................................................................................................5-106-1 General Memory Interface Configuration...................................................................................6-26-2 SDRAM Memory System Example............................................................................................6-56-3 Static Memory System Example................................................................................................6-66-4 External to Internal Address Mapping Options ........................................................................6-196-5 Basic SDRAM Timing Parameters...........................................................................................6-296-6 SDRAM_Read_diffbank_diffrow ..............................................................................................6-296-7 SDRAM_read_samebank_diffrow ...........................................................................................6-306-8 SDRAM_read_samebank_samerow .......................................................................................6-306-9 SDRAM_write ..........................................................................................................................6-316-10 SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions.....................................................6-316-11 SDRAM 4-Beat Write / 4-Write Same Bank, Same Row .........................................................6-326-12 SMROM Read Timing Diagram Half-Memory Clock Frequency .............................................6-396-13 Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode) ..........................6-416-14 Flash Memory Reset Using State Machine .............................................................................6-42

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6-15 Flash Memory Reset Logic if Watchdog Reset is Not Necessary ...........................................6-426-16 MSC0/1/2.................................................................................................................................6-466-17 32-Bit Burst-of-Eight ROM or Flash Read Timing Diagram (MSC0[RDF] = 4,

MSC0[RDN] = 1, MSC0[RRR] = 1)..........................................................................................6-516-18 Eight-Beat Burst Read from 16-Bit Burst-of-Four ROM or Flash

(MSC0[RDF] = 4, MSC0[RDN] = 1, MSC0[RRR] = 0) .............................................................6-526-19 32-Bit Non-burst ROM, SRAM, or Flash Read Timing Diagram - Four Data

Beats (MSC0[RDF] = 4, MSC0[RRR] = 1)...............................................................................6-536-20 32-Bit SRAM Write Timing Diagram (4-beat Burst (MSC0[RDN] = 2,

MSC0[RRR] = 1)......................................................................................................................6-546-21 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per

Beat) (MSC0[RDF] = 2, MSC0[RDN] = 2, MSC0[RRR] = 1) ...................................................6-566-22 32-Bit Variable Latency I/O Write Timing (Burst-of-Four, Variable Wait Cycles

Per Beat) .................................................................................................................................6-576-23 Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes) .................................................6-596-24 MCMEM1.................................................................................................................................6-606-25 MCATT1 ..................................................................................................................................6-606-26 16-Bit PC Card Memory Map ..................................................................................................6-646-27 Expansion Card External Logic for a One-Socket Configuration.............................................6-676-28 Expansion Card External Logic for a Two-Socket Configuration.............................................6-686-29 16-Bit PC Card Memory or I/O 16-Bit (Half-word) Access.......................................................6-696-30 16-Bit PC Card I/O 16-Bit Access to 8-Bit Device ...................................................................6-706-31 Alternate Bus Master Mode .....................................................................................................6-716-32 Variable Latency IO .................................................................................................................6-716-33 Asynchronous Boot Time Configurations and Register Defaults.............................................6-766-34 SMROM Boot Time Configurations and Register Defaults......................................................6-776-35 SMROM Boot Time Configurations and Register Defaults......................................................6-787-1 LCD Controller Block Diagram ..................................................................................................7-37-2 Temporal Dithering Concept - Single Color...............................................................................7-67-3 Compare Range for TMED........................................................................................................7-77-4 TMED Block Diagram ...............................................................................................................7-87-5 Palette Buffer Format ..............................................................................................................7-117-6 1 Bit Per Pixel Data Memory Organization ..............................................................................7-117-7 2 Bits Per Pixel Data Memory Organization ............................................................................7-127-8 4 Bits Per Pixel Data Memory Organization ............................................................................7-127-9 8 Bits Per Pixel Data Memory Organization ............................................................................7-127-10 16 Bits Per Pixel Data Memory Organization - Passive Mode ................................................7-137-11 16 Bits Per Pixel Data Memory Organization - Active Mode ...................................................7-137-12 Passive Mode Start-of-Frame Timing......................................................................................7-157-13 Passive Mode End-of-Frame Timing .......................................................................................7-157-14 Passive Mode Pixel Clock and Data Pin Timing......................................................................7-167-15 Active Mode Timing .................................................................................................................7-167-16 Active Mode Pixel Clock and Data Pin Timing ........................................................................7-177-17 Frame Buffer/Palette Output to LCD Data Pins in Active Mode ..............................................7-207-18 LCD Data-Pin Pixel Ordering...................................................................................................7-228-1 Texas Instruments’ Synchronous Serial Frame* Format...........................................................8-48-2 Motorola SPI* Frame Format.....................................................................................................8-58-3 National Microwire* Frame Format............................................................................................8-68-4 Motorola SPI* Frame Formats for SPO and SPH Programming .............................................8-139-1 I2C Bus Configuration Example................................................................................................9-29-2 Start and Stop Conditions..........................................................................................................9-5

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9-3 START and STOP Conditions ...................................................................................................9-69-4 Data Format of First Byte in Master Transaction .......................................................................9-89-5 Acknowledge on the I2C Bus.....................................................................................................9-99-6 Clock Synchronization During the Arbitration Procedure.........................................................9-109-7 Arbitration Procedure of Two Masters .....................................................................................9-119-8 Master-Receiver Read from Slave-Transmitter .......................................................................9-149-9 Master-Receiver Read from Slave-Transmitter / Repeated Start / Master-

Transmitter Write to Slave-Receiver........................................................................................9-149-10 A Complete Data Transfer .......................................................................................................9-149-11 Master-Transmitter Write to Slave-Receiver............................................................................9-169-12 Master-Receiver Read to Slave-Transmitter ...........................................................................9-169-13 Master-Receiver Read to Slave-Transmitter, Repeated START, Master-

Transmitter Write to Slave-Receiver........................................................................................9-169-14 General Call Address...............................................................................................................9-1710-1 Example UART Data Frame ....................................................................................................10-410-2 Example NRZ Bit Encoding – (0b0100 1011 ...........................................................................10-510-3 IR Transmit and Receive Example ........................................................................................10-2510-4 XMODE Example...................................................................................................................10-2511-1 4PPM Modulation Encodings...................................................................................................11-211-2 4PPM Modulation Example .....................................................................................................11-211-3 Frame Format for IrDA Transmission (4.0 Mbps) ....................................................................11-312-1 NRZI Bit Encoding Example ....................................................................................................12-412-2 Self-Powered Device .............................................................................................................12-1113-1 Data Transfer Through the AC-link..........................................................................................13-313-2 AC’97 Standard Bidirectional Audio Frame .............................................................................13-413-3 AC-link Audio Output Frame....................................................................................................13-513-4 Start of Audio Output Frame....................................................................................................13-513-5 AC’97 Input Frame...................................................................................................................13-913-6 Start of an Audio Input Frame..................................................................................................13-913-7 AC-link Powerdown Timing....................................................................................................13-1213-8 SDATA_IN Wake Up Signaling..............................................................................................13-1313-9 PCM Transmit and Receive Operation ..................................................................................13-2713-10 Mic-in Receive-Only Operation..............................................................................................13-2913-11 Modem Transmit and Receive Operation ..............................................................................13-3214-1 I2S Data Formats (16 bits).......................................................................................................14-714-2 MSB-Justified Data Formats (16 bits .......................................................................................14-714-3 Transmit and Receive FIFO Accesses Through the SADR...................................................14-1515-1 MMC System Interaction .........................................................................................................15-115-2 MMC Mode Operation Without Data Token.............................................................................15-315-3 MMC Mode Operation With Data Token..................................................................................15-315-4 SPI Mode Operation Without Data Token ...............................................................................15-415-5 SPI Mode Read Operation.......................................................................................................15-415-6 SPI Mode Write Operation.......................................................................................................15-416-1 Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers) .........................16-516-2 Texas Instruments Synchronous Serial Frame* Protocol (single transfers) ............................16-616-3 Motorola SPI* Frame Protocol (multiple transfers) ..................................................................16-716-4 Motorola SPI* Frame Protocol (single transfers) .....................................................................16-716-5 Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple transfers).............16-816-6 Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers)................16-916-7 National Semiconductor Microwire* Frame Protocol (multiple transfers) ..............................16-10

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16-8 National Semiconductor Microwire* Frame Protocol (single transfers) .................................16-1016-9 Programmable Serial Protocol (multiple transfers)................................................................16-1116-10 Programmable Serial Protocol (single transfers)...................................................................16-1216-11 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=0.................................................................16-1316-12 TI SSP with SSCR[TTE]=1 and SSCR[TTELP]=1.................................................................16-1416-13 Motorola SPI with SSCR[TTE]=1...........................................................................................16-1416-14 National Semiconductor Microwire with SSCR1[TTE]=1.......................................................16-1516-15 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (slave to frame).............................16-1516-16 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame) ..........................16-1616-17 PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame) ...............16-1617-1 Example UART Data Frame....................................................................................................17-317-2 Example NRZ Bit Encoding – (0b0100 1011...........................................................................17-417-3 IR Transmit and Receive Example ..........................................................................................17-917-4 XMODE Example. ...................................................................................................................17-9

Tables 2-1CPU Core Fault Register Bit Definitions...............................................................................2-3

2-2 ID Bit Definitions ........................................................................................................................2-42-3 PXA255 Processor ID Values....................................................................................................2-42-4 Effect of Each Type of Reset on Internal Register State ...........................................................2-62-5 Processor Pin Types .................................................................................................................2-82-6 Pin & Signal Descriptions for the PXA255 Processor................................................................2-92-7 Pin Description Notes ..............................................................................................................2-172-8 System Architecture Register Address Summary ...................................................................2-213-1 Core PLL Output Frequencies for 3.6864 MHz Crystal .............................................................3-53-2 95.85 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ..................................3-53-3 147.46 MHz Peripheral PLL Output Frequencies for 3.6864 MHz Crystal ................................3-63-4 Power Mode Entry Sequence Table.......................................................................................3-203-5 Power Mode Exit Sequence Table .........................................................................................3-203-6 Power and Clock Supply Sources and States During Power Modes .....................................3-223-7 PMCR Bit Definitions ...............................................................................................................3-233-8 PCFR Bit Definitions................................................................................................................3-243-9 PWER Bit Definitions...............................................................................................................3-253-10 PRER Bit Definitions................................................................................................................3-263-11 PFER Bit Definitions ................................................................................................................3-273-12 PEDR Bit Definitions................................................................................................................3-283-13 PSSR Bit Definitions................................................................................................................3-293-14 PSPR Bit Definitions................................................................................................................3-303-15 PMFW Register Bitmap and Bit Definitions .............................................................................3-313-16 PGSR0 Bit Definitions .............................................................................................................3-323-17 PGSR1 Bit Definitions .............................................................................................................3-323-18 PGSR2 Bit Definitions .............................................................................................................3-333-19 RCSR Bit Definitions ...............................................................................................................3-343-20 CCCR Bit Definitions ...............................................................................................................3-353-21 CKEN Bit Definitions................................................................................................................3-363-22 OSCC Bit Definitions ...............................................................................................................3-383-23 Coprocessor 14 Clock and Power Management Summary.....................................................3-393-24 CCLKCFG Bit Definitions ........................................................................................................3-393-25 PWRMODE Bit Definitions ......................................................................................................3-40

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3-26 Clocks Manager Register Summary ........................................................................................3-413-27 Power Manager Register Summary.........................................................................................3-424-1 GPIO Alternate Functions..........................................................................................................4-34-2 GPIO Register Definitions..........................................................................................................4-64-3 GPLR0 Bit Definitions ................................................................................................................4-74-4 GPLR1 Bit Definitions ................................................................................................................4-84-5 GPLR2 Bit Definitions ................................................................................................................4-84-6 GPDR0 Bit Definitions ...............................................................................................................4-94-7 GPDR1 Bit Definitions ...............................................................................................................4-94-8 GPDR2 Bit Definitions ...............................................................................................................4-94-9 GPSR0 Bit Definitions..............................................................................................................4-104-10 GPSR1 Bit Definitions..............................................................................................................4-104-11 GPSR2 Bit Definitions..............................................................................................................4-114-12 GPCR0 Bit Definitions .............................................................................................................4-114-13 GPCR1 Bit Definitions .............................................................................................................4-114-14 GPCR2 Bit Definitions .............................................................................................................4-124-15 GRER0 Bit Definitions .............................................................................................................4-134-16 GRER1 Bit Definitions .............................................................................................................4-134-17 GRER2 Bit Definitions .............................................................................................................4-134-18 GFER0 Bit Definitions...........................