Interconnect Efficient Interconnect Efficient LDPC Code DesignLDPC Code Design

Interconnect Efficient Interconnect Efficient LDPC Code DesignLDPC Code Design

Aiman El-Maleh Basil Arkasosy Aiman El-Maleh Basil Arkasosy Adnan Al-AndalusiAdnan Al-Andalusi

King Fahd University of Petroleum & Minerals, King Fahd University of Petroleum & Minerals, Saudi ArabiaSaudi Arabia

Aiman El-Maleh Basil Arkasosy Aiman El-Maleh Basil Arkasosy Adnan Al-AndalusiAdnan Al-Andalusi

King Fahd University of Petroleum & Minerals, King Fahd University of Petroleum & Minerals, Saudi ArabiaSaudi Arabia

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OutlineOutlineOutlineOutline

MotivationMotivation LDPC Code OverviewLDPC Code Overview LDPC Codes and CyclesLDPC Codes and Cycles Cycles Detection AlgorithmCycles Detection Algorithm Area Constrained LDPC code DesignArea Constrained LDPC code Design Experimental resultsExperimental results ConclusionsConclusions

MotivationMotivation LDPC Code OverviewLDPC Code Overview LDPC Codes and CyclesLDPC Codes and Cycles Cycles Detection AlgorithmCycles Detection Algorithm Area Constrained LDPC code DesignArea Constrained LDPC code Design Experimental resultsExperimental results ConclusionsConclusions

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MotivationMotivationMotivationMotivation

LDPC codes belong to a family of error correction LDPC codes belong to a family of error correction systems with performance close to information-systems with performance close to information-theoretic limits.theoretic limits.

Selected for next-generation digital satellite Selected for next-generation digital satellite broadcasting standard (DVB-S2), ultra high-speed broadcasting standard (DVB-S2), ultra high-speed Local Area Networks (10Gbps Ethernet LANs). Local Area Networks (10Gbps Ethernet LANs).

LDPC codes inherently more amenable to LDPC codes inherently more amenable to parallelization. parallelization.

LDPC code design based on random code generation LDPC code design based on random code generation results in long interconnect wires, lower speed, results in long interconnect wires, lower speed, higher power and less area utilization.higher power and less area utilization.

Objective to design interconnect-efficient LDPC Objective to design interconnect-efficient LDPC codes with relatively good error correction codes with relatively good error correction performance.performance.

LDPC codes belong to a family of error correction LDPC codes belong to a family of error correction systems with performance close to information-systems with performance close to information-theoretic limits.theoretic limits.

Selected for next-generation digital satellite Selected for next-generation digital satellite broadcasting standard (DVB-S2), ultra high-speed broadcasting standard (DVB-S2), ultra high-speed Local Area Networks (10Gbps Ethernet LANs). Local Area Networks (10Gbps Ethernet LANs).

LDPC codes inherently more amenable to LDPC codes inherently more amenable to parallelization. parallelization.

LDPC code design based on random code generation LDPC code design based on random code generation results in long interconnect wires, lower speed, results in long interconnect wires, lower speed, higher power and less area utilization.higher power and less area utilization.

Objective to design interconnect-efficient LDPC Objective to design interconnect-efficient LDPC codes with relatively good error correction codes with relatively good error correction performance.performance.

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LDPC Codes OverviewLDPC Codes OverviewLDPC Codes OverviewLDPC Codes Overview

LDPC codes linear block codes decoded by efficient LDPC codes linear block codes decoded by efficient iterative decoding.iterative decoding.

An LDPC parity check matrix An LDPC parity check matrix HH represents the parity represents the parity equations in a linear formequations in a linear form• codeword codeword cc satisfies the set of parity equations satisfies the set of parity equations H cH c = 0. = 0.

• each column in the matrix represents a codeword bit each column in the matrix represents a codeword bit

• each row represents a parity check equation each row represents a parity check equation

LDPC codes linear block codes decoded by efficient LDPC codes linear block codes decoded by efficient iterative decoding.iterative decoding.

An LDPC parity check matrix An LDPC parity check matrix HH represents the parity represents the parity equations in a linear formequations in a linear form• codeword codeword cc satisfies the set of parity equations satisfies the set of parity equations H cH c = 0. = 0.

• each column in the matrix represents a codeword bit each column in the matrix represents a codeword bit

• each row represents a parity check equation each row represents a parity check equation

1 0 1 1 0 0 0

0 1 0 1 1 0 0

0 0 1 0 1 1 0

0 0 0 1 0 1 1

H

cc00 c c11 c c33 = 0 = 0

cc11 c c22 c c44 = 0 = 0

cc22 c c33 c c55 = 0 = 0

cc33 c c33 c c66 = 0 = 0

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LDPC Codes OverviewLDPC Codes OverviewLDPC Codes OverviewLDPC Codes Overview

LDPC codes can be classified as regular or irregular LDPC codes can be classified as regular or irregular

H matrix is H matrix is (W(Wcc,W,Wrr)-regular)-regular

• each row contains same number Weach row contains same number Wrr

• each column contains same number Weach column contains same number Wcc..

LDPC codes represented by Tanner Graphs LDPC codes represented by Tanner Graphs • two types of vertices: Bit Vertices and Check Vertices two types of vertices: Bit Vertices and Check Vertices

Code RateCode Rate ratio of information bits to total number of ratio of information bits to total number of bits in codeword bits in codeword

LDPC codes can be classified as regular or irregular LDPC codes can be classified as regular or irregular

H matrix is H matrix is (W(Wcc,W,Wrr)-regular)-regular

• each row contains same number Weach row contains same number Wrr

• each column contains same number Weach column contains same number Wcc..

LDPC codes represented by Tanner Graphs LDPC codes represented by Tanner Graphs • two types of vertices: Bit Vertices and Check Vertices two types of vertices: Bit Vertices and Check Vertices

Code RateCode Rate ratio of information bits to total number of ratio of information bits to total number of bits in codeword bits in codeword

0 2 31

00 11 22 33 44 55 66

1 0 1 1 0 0 0

0 1 0 1 1 0 0

0 0 1 0 1 1 0

0 0 0 1 0 1 1

H

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LDPC Codes & CyclesLDPC Codes & CyclesLDPC Codes & CyclesLDPC Codes & Cycles

Existence of cycles (loops) in tanner graphs of LDPC Existence of cycles (loops) in tanner graphs of LDPC codes impact performance.codes impact performance.

A cycle of size A cycle of size KK is a closed path of is a closed path of KK edges visiting a edges visiting a vertex more than once, while visiting each edge in vertex more than once, while visiting each edge in this path only once. this path only once.

Possible cycles are of even sizes, starting by four.Possible cycles are of even sizes, starting by four.

Existence of cycles (loops) in tanner graphs of LDPC Existence of cycles (loops) in tanner graphs of LDPC codes impact performance.codes impact performance.

A cycle of size A cycle of size KK is a closed path of is a closed path of KK edges visiting a edges visiting a vertex more than once, while visiting each edge in vertex more than once, while visiting each edge in this path only once. this path only once.

Possible cycles are of even sizes, starting by four.Possible cycles are of even sizes, starting by four.

B0B1

C0C1

B0B1

C0C1

B2

C2

4-loop4-loop 6-loop6-loop

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Cycle Detection AlgorithmCycle Detection AlgorithmCycle Detection AlgorithmCycle Detection Algorithm

Checking if an edge between the bit node Checking if an edge between the bit node ii and the and the check node check node j j creates a creates a four loopfour loop::• Find the set of all bit nodes Find the set of all bit nodes KK to which check node to which check node jj is is

connected.connected.

• For For eacheach bit node bit node kk in in K (k K (k i), i), find all the check nodes find all the check nodes LL that are connected to that are connected to thatthat node. node.

• For For eacheach check node check node ll in in L (l L (l j), j), find all the bit nodes find all the bit nodes MM that are connected to that are connected to thatthat node. node.

• If node If node ii is in is in MM, then a four loop is detected, then a four loop is detected

Checking if an edge between the bit node Checking if an edge between the bit node ii and the and the check node check node j j creates a creates a four loopfour loop::• Find the set of all bit nodes Find the set of all bit nodes KK to which check node to which check node jj is is

connected.connected.

• For For eacheach bit node bit node kk in in K (k K (k i), i), find all the check nodes find all the check nodes LL that are connected to that are connected to thatthat node. node.

• For For eacheach check node check node ll in in L (l L (l j), j), find all the bit nodes find all the bit nodes MM that are connected to that are connected to thatthat node. node.

• If node If node ii is in is in MM, then a four loop is detected, then a four loop is detected

B0B1

C0C1

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Area Constrained LDPC Code DesignArea Constrained LDPC Code DesignArea Constrained LDPC Code DesignArea Constrained LDPC Code Design

Randomly designed LDPC codes achieve good error Randomly designed LDPC codes achieve good error correction performance.correction performance.

Wire lengths in decoders can become very large.Wire lengths in decoders can become very large. Objective to design LDPC codes with constrains on Objective to design LDPC codes with constrains on

interconnect wire lengthinterconnect wire length• considerable decrease the signal delayconsiderable decrease the signal delay

• lowering interconnect routing congestionlowering interconnect routing congestion

• reducing chip area reducing chip area

• reducing power dissipationreducing power dissipation

Designed LDPC codes with 1024 bits and ½ rate.Designed LDPC codes with 1024 bits and ½ rate.

Randomly designed LDPC codes achieve good error Randomly designed LDPC codes achieve good error correction performance.correction performance.

Wire lengths in decoders can become very large.Wire lengths in decoders can become very large. Objective to design LDPC codes with constrains on Objective to design LDPC codes with constrains on

interconnect wire lengthinterconnect wire length• considerable decrease the signal delayconsiderable decrease the signal delay

• lowering interconnect routing congestionlowering interconnect routing congestion

• reducing chip area reducing chip area

• reducing power dissipationreducing power dissipation

Designed LDPC codes with 1024 bits and ½ rate.Designed LDPC codes with 1024 bits and ½ rate.

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Area Constrained LDPC Code DesignArea Constrained LDPC Code DesignArea Constrained LDPC Code DesignArea Constrained LDPC Code Design

Bit & check nodes laid out in Bit & check nodes laid out in a two-dimensional structure.a two-dimensional structure.

Connections btw. bit & check Connections btw. bit & check nodes constrained within a nodes constrained within a window of rows & columns.window of rows & columns.

Guarantees wire length Guarantees wire length bounded by a maximum bounded by a maximum length.length.

Example:Example:

• Window(R,C) = (2,3).Window(R,C) = (2,3).

• Bit node 16 can only Bit node 16 can only connect to check nodes connect to check nodes (4,5,6,8,9,10).(4,5,6,8,9,10).

Bit & check nodes laid out in Bit & check nodes laid out in a two-dimensional structure.a two-dimensional structure.

Connections btw. bit & check Connections btw. bit & check nodes constrained within a nodes constrained within a window of rows & columns.window of rows & columns.

Guarantees wire length Guarantees wire length bounded by a maximum bounded by a maximum length.length.

Example:Example:

• Window(R,C) = (2,3).Window(R,C) = (2,3).

• Bit node 16 can only Bit node 16 can only connect to check nodes connect to check nodes (4,5,6,8,9,10).(4,5,6,8,9,10).

B0 B1

C2

B2

C0

B3 B4

C3C1

B5 B6 B7

B8 B9

C6

B10

C4

B11 B12

C7C5

B13 B14 B15

B16 B17

C10

B18

C8

B19 B20

C11C9

B21 B22 B23

B24 B25

C14

B26

C12

B27 B28

C15C13

B29 B30 B31

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Set of Check Nodes for a Bit Node Set of Check Nodes for a Bit Node Set of Check Nodes for a Bit Node Set of Check Nodes for a Bit Node

Row#=Row#=i/Mi/M; Col#= i ; Col#= i modmod M; Vertical Domain=R/2 M; Vertical Domain=R/2Assigned check node = Assigned check node = (Col#+Row#*M)/2(Col#+Row#*M)/2 ; t = 1; ; t = 1;for each t for each t Vertical Domain Vertical Domain{{ if (assigned check node + (t-1) * (M/2)) < No. check nodes Thenif (assigned check node + (t-1) * (M/2)) < No. check nodes Then assigned check node = assigned check node + ((t -1)* (M/2)) assigned check node = assigned check node + ((t -1)* (M/2)) Add_HorizontalAdd_Horizontal( assigned check node , Row# + (t-1) )( assigned check node , Row# + (t-1) ) if (assigned check node – t * (M/2)) if (assigned check node – t * (M/2)) 0 Then 0 Then assigned check node = assigned check node – (t * (M/2))assigned check node = assigned check node – (t * (M/2)) Add_HorizontalAdd_Horizontal( assigned check node , Row# - t )( assigned check node , Row# - t ) t = t + 1;t = t + 1;}}

NxM bit nodes, NxM/2 check nodes, window constraint (R, C)NxM bit nodes, NxM/2 check nodes, window constraint (R, C)

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Set of Check Nodes for a Bit NodeSet of Check Nodes for a Bit NodeSet of Check Nodes for a Bit NodeSet of Check Nodes for a Bit Node

Add_HorizontalAdd_Horizontal (assigned check node , Row#) (assigned check node , Row#){{Horizontal Domain =(C-1/)2; Horizontal Domain =(C-1/)2; add the assigned check node; k = 1;add the assigned check node; k = 1; for each k for each k Horizontal Domain { Horizontal Domain { if (assigned check node + k) < ((M/2) * (Row# +1)) Thenif (assigned check node + k) < ((M/2) * (Row# +1)) Then add the check node “assigned check node + k”add the check node “assigned check node + k” if (assigned check node - k) if (assigned check node - k) ((M/2) * Row#) Then ((M/2) * Row#) Then add the check node “assigned check node - k”add the check node “assigned check node - k” k = k + 1;k = k + 1; }}}}

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Experimental ResultsExperimental ResultsExperimental ResultsExperimental Results

Designed LDPC codes (3,6)-regular with 1024 bits and Designed LDPC codes (3,6)-regular with 1024 bits and ½ rate.½ rate.

LDPC codes randomly generated under given LDPC codes randomly generated under given constraints.constraints.

Five LDPC codes for each criteria considered & best Five LDPC codes for each criteria considered & best selectedselected• 4-loop free (4L), 4-loop free (4L),

• 6-loop free (6L),6-loop free (6L),

• minimized 8-loop (M8L), minimized 8-loop (M8L),

• window constrained minimized 8-loop (WM8L). window constrained minimized 8-loop (WM8L).

LDPC codes with 32x32 layout of bit nodes and 32x16 LDPC codes with 32x32 layout of bit nodes and 32x16 layout of check nodes. layout of check nodes.

A constraint window (R, C)=(16, 15) is assumed.A constraint window (R, C)=(16, 15) is assumed.

Designed LDPC codes (3,6)-regular with 1024 bits and Designed LDPC codes (3,6)-regular with 1024 bits and ½ rate.½ rate.

LDPC codes randomly generated under given LDPC codes randomly generated under given constraints.constraints.

Five LDPC codes for each criteria considered & best Five LDPC codes for each criteria considered & best selectedselected• 4-loop free (4L), 4-loop free (4L),

• 6-loop free (6L),6-loop free (6L),

• minimized 8-loop (M8L), minimized 8-loop (M8L),

• window constrained minimized 8-loop (WM8L). window constrained minimized 8-loop (WM8L).

LDPC codes with 32x32 layout of bit nodes and 32x16 LDPC codes with 32x32 layout of bit nodes and 32x16 layout of check nodes. layout of check nodes.

A constraint window (R, C)=(16, 15) is assumed.A constraint window (R, C)=(16, 15) is assumed.

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Experimental ResultsExperimental ResultsExperimental ResultsExperimental Results

FER performance using simulations at different SNR FER performance using simulations at different SNR pointspoints• stopping criteria of 200 frame errors at SNRstopping criteria of 200 frame errors at SNR2 and 200,000 2 and 200,000

code words for SNR>2. code words for SNR>2.

• Iterative decoding performed for 64 iterations.Iterative decoding performed for 64 iterations.

Hardware comparisons based on VHDL model with Hardware comparisons based on VHDL model with parallel implem. of LDPC decoder from H matrixparallel implem. of LDPC decoder from H matrix• functions of check and variables nodes a dummy single gatefunctions of check and variables nodes a dummy single gate

Synthesis performed using Xilinx synthesis tools on Synthesis performed using Xilinx synthesis tools on Xilinx Spartan3 XC3S5000-fg900 FPGA optimized for Xilinx Spartan3 XC3S5000-fg900 FPGA optimized for area. area.

FER performance using simulations at different SNR FER performance using simulations at different SNR pointspoints• stopping criteria of 200 frame errors at SNRstopping criteria of 200 frame errors at SNR2 and 200,000 2 and 200,000

code words for SNR>2. code words for SNR>2.

• Iterative decoding performed for 64 iterations.Iterative decoding performed for 64 iterations.

Hardware comparisons based on VHDL model with Hardware comparisons based on VHDL model with parallel implem. of LDPC decoder from H matrixparallel implem. of LDPC decoder from H matrix• functions of check and variables nodes a dummy single gatefunctions of check and variables nodes a dummy single gate

Synthesis performed using Xilinx synthesis tools on Synthesis performed using Xilinx synthesis tools on Xilinx Spartan3 XC3S5000-fg900 FPGA optimized for Xilinx Spartan3 XC3S5000-fg900 FPGA optimized for area. area.

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FER Comparison of LDPC codes FER Comparison of LDPC codes FER Comparison of LDPC codes FER Comparison of LDPC codes

0.00001

0.0001

0.001

0.01

0.1

1

0 0.5 1 1.5 2 2.5 3

4L

6L

M8L

WM8L

SNRSNR

FERFER

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Loop Count and Synthesis ResultsLoop Count and Synthesis ResultsLoop Count and Synthesis ResultsLoop Count and Synthesis Results

LDPC LDPC CodeCode

StructureStructure

No. of Loops No. of Loops Synthesis Synthesis

Slices usedSlices usedout of 33,280out of 33,280

Delay Delay (ns)(ns)44 66 88

4L 0 172 1273 2,562 14.19

6L 0 0 1300 2,562 14.34

M8L 0 0 226 2,562 13.10

WM8L 0 0 870 2,527 11.88

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Post Place and Route Snapshots of Post Place and Route Snapshots of Synthesized LDPC codes Synthesized LDPC codes Post Place and Route Snapshots of Post Place and Route Snapshots of Synthesized LDPC codes Synthesized LDPC codes

M8LM8L WM8LWM8L

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ConclusionsConclusionsConclusionsConclusions

Investigated design of interconnect-efficient LDPC Investigated design of interconnect-efficient LDPC codes that reduce area and delay of decoder while codes that reduce area and delay of decoder while maintaining good error correction performance.maintaining good error correction performance.

LDPC codes designed with loop constraints & LDPC codes designed with loop constraints & window constraint on interconnect wire length. window constraint on interconnect wire length.

Demonstrated possibility to deign LDPC codes that Demonstrated possibility to deign LDPC codes that are interconnect efficient are interconnect efficient • small performance impact compared to randomly small performance impact compared to randomly

unconstrained generated LDPC codes. unconstrained generated LDPC codes.

• Less delay and routing congestionLess delay and routing congestion

Investigated design of interconnect-efficient LDPC Investigated design of interconnect-efficient LDPC codes that reduce area and delay of decoder while codes that reduce area and delay of decoder while maintaining good error correction performance.maintaining good error correction performance.

LDPC codes designed with loop constraints & LDPC codes designed with loop constraints & window constraint on interconnect wire length. window constraint on interconnect wire length.

Demonstrated possibility to deign LDPC codes that Demonstrated possibility to deign LDPC codes that are interconnect efficient are interconnect efficient • small performance impact compared to randomly small performance impact compared to randomly

unconstrained generated LDPC codes. unconstrained generated LDPC codes.

• Less delay and routing congestionLess delay and routing congestion