2014 Master Thesis
Interface control process toward
un-pinned metal/germanium
Schottky contact
Ryo Yoshihara
12M36374
Department of Electrical and Electronic Engineering
Tokyo Institute of Technology
Supervisor
Associate Professor: Kuniyuki Kakushima
Professor: Hiroshi Iwai
February, 2014 Abstract of Master Thesis
Interface control process toward un-pinned metal/germanium
Schottky contact
Supervisor: Associate Prof. Kuniyuki Kakushima
Supervisor: Prof. Hiroshi Iwai
Tokyo Institute of Technology
Department of Electrical and Electronic Engineering
12M36374 Ryo Yoshihara
Germanium channels have attracted lots of interests as alternatives to further improve the
performance of complementary metal-oxide-semiconductors owing to its high intrinsic
mobility. One of the concerns is the presence of Fermi-level pinning near the valence band
which leads large Schottky barrier height for electrons, which eventually increases the contact
resistance for n-type germanium channel. Un-pinned metal contact processes including thin
oxide insertion between metal and germanium substrate, and formation of thin amorphous
germanium layer at the interface have been proposed so far. Due to insertion thickness
sensitivity and small process window, a stable un-pinned process is required. The purpose of
this thesis is to present a guideline to achieve an un-pinned contact at metal and germanium
interface for low contact resistance which is compatible to gate formation processes. Firstly,
characteristics of thermally stable metals are presented and secondly an original unpin process
using interface impurity incorporation is described.
Thermally stable nickel di-silicide, which has been formed by cyclic deposition of nickel and
silicon layers, has been used as a contact metal. A stable sheet resistance in the temperature
range from 350 to 700 degree C has been obtained, and nearly ideal Schottky diode
characteristics have been achieved, owing to little interface reaction. The chemical bonding
states of nickel di-silicides on germanium substrates, analyzed by x-ray photoelectron
spectroscopy, has revealed the formation of nickel di-silicides when annealed at 500 degree C,
whereas at high temperature annealing, nickel germanide phase start to appear.
Next, insertion of phosphorous atoms at nickel di-silicides and germanium interface has been
performed by changing the Ni layer to Ni3P layer. An effective energy barrier height
modification has been confirmed by diode characterization, and Ohmic contacts have been
achieved at annealing temperature as low as 300 degree C and up to 600 degree C. Also, x-ray
photoelectron spectroscopy has revealed surface potential shift, which indicates that the
metal/germanium interface has been un-pinned. Transmission electron microscopy has
revealed an atomically flat metal and germanium interface with a thin interface layer. Analysis
of the thin layer has revealed a mixture of nickel, silicon, phosphorous and germanium atoms.
With circular transmission line method, the contact resistance has been obtained an order of
10 to the minus third power ohm square centimeter from 300 degree C and up to 600 degree
C.
The above un-pinned process gives further insights into low contact resistance process as
well as interface researches.
i
Contents
1 Introduction
1.1 Introduction of CMOS scaling...................................................2
1.2 Introduction of high mobility channel material..........................4
1.3 Introduction of metal Schottky source/drain.........................5
1.4 Issues of metal/germanium Schottky junction.......................6
1.5 Repots on un-pinned metal/germanium process............................7
1.6 Purpose of this study......................................................................9
References
2 Experimental setup
2.1 Device fabrication
2.1.1 Radio frequency magnetron sputtering.....................................14
2.1.2 Rapid thermal annealing.........................................................15
2.1.3 Vacuum evaporation...................................................................15
2.2 Four-point method.....................................................................16
2.3 Transmission electron microscopy................................................16
2.4 J-V characteristics
2.4.1 Thermionic emission theory...............................................18
2.4.2 Image-force-induced barrier lowering..............................18
2.5 Atomic force microscope...............................................................19
2.6 X-ray photoelectron spectroscopy.................................................20
2.7 Back-side secondary ion mass spectrometry...........................21
ii
2.8 Circular transmission line method.............................................22
References
3 Composition and morphology of Ni-silicide films
3.1 Process of Ni-silicide.......................................................................29
3.2 Measurement of sheet resistance and roughness.........................29
3.3 Analysis of the chemical composition............................................31
3.4 J-V characteristics of stacked silicide diode.................................31
3.5 Conclusions......................................................................................34
References
4 Schottky barrier height lowering with P
incorporation
4.1 Incorporation P atoms...................................................................37
4.2 Observation of cross-section surface.............................................37
4.3 Analysis of concentration distribution.......................................40
4.4 Measurement of J-V characteristics..................................41
4.5 Extraction of contact resistance................................................42
4.6 Extraction of Schottky barrier height......................................44
4.7 Observance of band bending........................................................46
4.8 Conclusions......................................................................................51
References
iii
5 Conclusions.................................................................................53
Acknowledgement........................................................................57
1
Chapter 1
Introduction
1 Introduction
1.1 Introduction of CMOS scaling...................................................2
1.2 Introduction of high mobility channel material..........................4
1.3 Introduction of metal Schottky source/drain.........................5
1.4 Issues of metal/germanium Schottky junction.......................6
1.5 Repots on un-pinned metal/germanium process............................7
1.6 Purpose of this study......................................................................9
References
2
1.1 Introduction of CMOS scaling
Very Large Scale Integration (VLSI) technology has been considered essential to
modern information society. VLSI circuits have been constructed by Complementally
Metal-Oxide-Semiconductor (CMOS) Field-Effect-Transistor (FET). It is necessary
for development of Information Technology (IT) that CMOSFET with high speed, low
power consumption is achieved. The key to the advancement of VLSI technology is
the device scaling which means scaling down the size of MOSFETs. Table 1.1 and fig.
1.1 show the scaling rules for various device and circuit parameters. Scaling rules show
speed up of circuit and reduction of power consumption are obtained with the scaling
of the device dimensions [1.1]. Therefore, scaling leads to improvement of
convenience for people and saving energy.
Table 1.1 Constant-field scaling of MOSFET device and circuit parameters.
The scaling remains electrical field unchanged.
1Electric field (E)
1/kJunction depth (xj)
kDoping concentration (N)
1/kDepletion layer width (Wd)
1/k2Device area (A)
1/kCircuit delay time (t)
1/k2Power consumption (P)
1/kGate oxide thickness (tox)
1/kChannel width (W)
1/kChannel length (L)
Multiplicative factorParameters
1Electric field (E)
1/kJunction depth (xj)
kDoping concentration (N)
1/kDepletion layer width (Wd)
1/k2Device area (A)
1/kCircuit delay time (t)
1/k2Power consumption (P)
1/kGate oxide thickness (tox)
1/kChannel width (W)
1/kChannel length (L)
Multiplicative factorParameters
3
Fig. 1.1 Schematic illustration of scaling MOSFET.
However, continuous shrinking CMOS device into 16 and 11 nm technology nodes is
facing tremendous difficulties, including severe short channel effects, degraded
driving current, dopant penetrations and poly-silicon depletion, high-field effects,
direct gate tunneling current and high series resistance [1.2]. Thus, the introduction of
new materials such as high-k gate insulators (to replace SiO2 gate insulators), strained
silicon, Ge and III-V substrates (to replace Si substrates) metal gates (to replace
polysilicon gates) and metal source/drains (S/Ds) (to replace doped silicon S/Ds), and
structures such as silicon on insulator (SOI), Fin and silicon nanowires (SiNWs), have
been investigated as shown in table 1.2 and fig. 1.2 [1.3].
Table 1.2 The building-block materials of conventional and new material MOSFETs.
Strained-Si, Ge, III-VSiSubstrate
Metal (silicide)DopedS/D
MetalPolysiliconGate electrode
high-kSiO2Gate insulator
New materialConventional
Strained-Si, Ge, III-VSiSubstrate
Metal (silicide)DopedS/D
MetalPolysiliconGate electrode
high-kSiO2Gate insulator
New materialConventional
4
Fig. 1.2 Schematic illustration of MOSFET with new structures.
1.2 Introduction of high mobility channel material
The scaling of advanced MOS devices is approaching its technological and
fundamental limits. Further performance enhancements of MOSFETs require
exploitation of more efficient materials and architectures. An important factor defining
the transistor speed is the carrier injection velocity into the channel region which is
proportional to the carrier mobility. Therefore, germanium has been receiving
attention as an alternative channel material [1.4, 1.5] due to its high intrinsic mobility.
Table 1.2 show properties of semiconductors [1.6], germanium has two times higher
for electrons and four times higher for holes as compared to those in silicon.
5
Table 1.2 Mobility and band gap for Si, Ge, GaAs and InSb.
1.3 Introduction of metal Schottky source/drain
For short channel MOSFETs, there are some issues which are decrease of threshold
voltage, drain induced barrier lowering (DIBL) and so on. Thus, it is one of the key
for suppression of short channel effects to achieve abrupt and shallow junction at S/D
[1.7]. An approach to realize the abrupt and shallow junction is using Schottky barrier
S/D, which is typically formed by silicide. Schottky barrier S/D has some advantages
which is atomically abrupt and shallow junctions and low parasitic resistance [1.8]. In
addition to these advantages, a low temperature process capability is another advantage
of Schottky barrier S/D [1.9]. Therefore, Schottky barrier S/D is the key technology to
realize suppression of short channel effects as shown in fig. 1.3.
Si Ge GaAs InSb
electron mob.
(cm2/Vs)1500 3900 8500 77000
hole mob.
(cm2/Vs)470 1900 400 1000
band gap (eV) 1.12 0.67 1.42 0.17
6
Fig. 1.3 (a) 3D-FETs with conventional pn junctions suffer from short channel effects
with channel length scaling due to the dopant diffusions which lower the abruptness.
(b) Metal (silicide) Schottky junction is one of the solutions to suppress short channel
effects because of abrupt junctions [1.10, 1.11].
1.4 Issues in metal/germanium Schottky junction
Reduction of parasitic resistance of metallic contact on Ge substrate is one of the
issues for Ge FETs, and low contact resistance of NiGe with Ge substrate has been
studied as metallic contact on Ge substrate [1.12]. However, agglomeration of NiGe
roughens metal/Ge interface thereby increasing the sheet resistance at the interface
[1.13]. Moreover, as shown in fig. 1.4 [1.14], a strong Fermi-level pinning near the
valence band of Ge results in large Schottky barrier height for electrons (Bn), which
eventually leads to high contact resistance for n-type Ge channel [1.15].
Hard
mask
Gate
SourceDrain
SourceDrain
Gate
Lphy
Do
pa
ntC
on
c.
y position
Gate
(a) Conventional doping S/D
Gate
MetalMetal
MetalMetal
Gate
Me
tal C
on
c.
y position
Gate
Lphy = Leff
(b) Schottky barrier S/D
7
Fig. 1.4 Barrier height for electrons vs metal work function of Ge.
1.5 Repots on un-pinned metal/germanium process
Fermi level pinning at the metal/Ge Schottky junction is released and Schottky barrier
height comes to be modulated by tuning metal work function. Fermi level position is
then determined by the insulator, and theoretically any insulator (SiN [1.16],Ge3N4
[1.17], or Al2O3 [1.18], etc.) which has larger band gap and smaller dielectric constant
can release Fermi level pinning more effectively as shown in fig.1.5 [1.19]. However,
there has a problem which is the sensitivity of insulator thickness and the trade-off
relation between insulator thickness and contact resistance as shown in fig. 1.6. The
inserted interlayer would need to be kept a thickness of more than 1 nm, which would
limit the suppression of contact resistance for metal/n-Ge.
8
Fig. 1.5 The schematic band diagram at the metal/Ge Schottky junction
(a) without thin insulator and (b) with thin insulator.
Without insulator, the Fermi level of the metal is pinned close to a charge
neutrality level (ECNL), which is located near the Ge valence band.
With insulator, Fermi level pinning is released and effective Schottky barrier
height becomes small.
Fig. 1.6 J-V characteristics of Al/SiN/n-Ge shottky diodes.
9
Another solving Fermi level pinning has proposed TiN/n-Ge, with an approximately
1-nm-thick interlayer formed at a TiN/Ge interface, by direct sputter deposition from
a TiN target and subsequent postmetallization annealing at 350 oC as show in fig.1.7
[1.20]. However, there has a problem which is sensitivity and limit of annealing
temperature.
Fig. 1.7 J-V characteristics and HAADF-STEM image of
TiN/n-Ge shottky diodes at 350 oC annealing.
1.5 Purpose of this study
It is necessary for futures n-Ge MOSFET to lower contact resistance, control junction
position and apply widely and stably process range without inserted insulator. The
purpose of this thesis is to present a guideline to achieve an un-pinned contact of
metal/germanium for low contact resistance with compatible to gate formation
processes.
10
References
[1.1] Y. Taur, and T. H. Ning, “Fundamentals of MODERN VLSI DEVICES,” p.204-
p.206, Cambridge University Press (1998).
[1.2] Y. Song, H. Zhou, and Q. Xu: “Source/drain technologies for the scaling of
nanoscale CMOS device’’, Solid State Sciences, 13, p.294-p.305 (2011)
[1.3] T. Skotnicki, James A. Hutchby, Tsu-Jae King, H.-S. Philip Wong and Frederic
Boeuf, “The end of CMOS scaling: toward the introduction of new materials and
structural changes to improve MOSFET performance,” IEEE Circuits and Devices
Magazine, 21, p.16-p.26 (2005).
[1.4] A. Ritenour, S. Yu, M. L. Lee, N. Lu, W. Bai, A. Pitera, E. A. Fitzgerald, D. L.
Kwong, and D. A. Antoniadis, “Epitaxial Strained Germanium p-MOSFETs with HfO2
Gate Dielectric and TaN Gate Electrode,” Technical Digest - International Electron
Devices Meeting, p.433-p.436 (2003).
[1.5] C. O. Chui, S. Ramanathan, B. B. Triplet, P. C. McIntyre, and K. C. Saraswat,
“Germanium MOS Capacitors Incorporating Ultrathin High-k Gate Dielectric” IEEE
Electron Device Letters, 23, p.473-p.475 (2002).
[1.6] D. Schroder, “Semiconductor Material and Device Characterization,” third
edition, WILEY-INTERSCIENCE (2006).
[1.7] K. Tanaka, K. Takeuchi and M. Hane, “Practical FinFET Design considering
GIDL for LSTP (Low Standby Power) Devices,” Technical Digest - International
Electron Devices Meeting, p.980-p.983 (2005).
[1.8] J. M. Larson and J. P. Snyder, “Overview and Status of Metal S/D Schottky-
Barrier MOSFET Technology,” IEEE Transactions on Electron Devices, 53, p.1048-
p.1058 (2006).
11
[1.9] W. Mizubayashi, S. Migita, Y. Morita, and H. Ota, “Exact Control of Junction
Position and Schottky Barrier Height in Dopant-Segregated Epitaxial NiSi2 for High
Performance Metal Source/Drain MOSFETs,” Digest of Technical Papers -
Symposium on VLSI Technology, p.88-p.89 (2011).
[1.10] A. Kaneko, A. Yagishita, K. Yahashi, T. Kubota, M. Omura, K. Matsuo, I.
Mizushima, K. Okano, H. Kawasaki,T. Izumida, T. Kanemura, N. Aoki, A. Kinoshita,
J. Koga, S. Inaba, K. Ishimaru, Y. Toyoshima, H. Ishiuchi, K. Suguro, K. Eguchi,
Y.tsunashima, “High-Performance FinFET with Dopant-Segregated Schottky
Source/Drain,” Technical Digest - International Electron Devices Meeting, p.1-p.4
(2006).
[1.11] S. Migita, Y. Morita, W. Mizubayashi and H. Ota, “Epitaxial NiSi2 Source and
Drain Technology for Atomic-Scale Junction Control in Silicon Nanowire MOSFETs,”
International Workshop on Junction Technology (2010).
[1.12] X. V. Li, M. K. Husain, M. Kiziroglou, and C.H. de Groot, “Inhomogeneous
Ni/Ge Schottky barriers due to variation in Fermi-level pinning” Microelectronic
Engineering, 86, p.1599-p.1602 (2009).
[1.13] Q. Zhang, N. Wu, T. Osipowicz, L. K. Bera, and C. Zhu, “Formation and
Thermal Stability of Nickel Germanide on Germanium Substrate,” Japanese Journal
of Applied Physics, 44, L1389-L1391 (2005).
[1.14] A. Dimoulas, P. Tsipas, and A. Sotiropoulos, “Fermi-level pinning and charge
neutrality level in germanium,” Applied Physics Letters, 89, 252110 (2006).
[1.15] L. Lin, Y. Guo and J. Robertson, “Metal silicide Schottky barriers on Si and Ge
show weaker Fermi level pinning” Applied Physics Letters, 101, 052110 (2012).
12
[1.16] M. Kobayashi, A. Kinoshita, K. Saraswat, H.S.P. Wong and Y. Nishi, “Fermi
level depinning in metal/Ge Schottky junction for metal source/drain Ge metal-oxide-
semiconductor field-effect-transistor application” Journal of Applied Physics, 105,
023702 (2009).
[1.17] R. R. Lieten, S. Degroote, M. Kuijk, and G. Borghs, “Ohmic contact formation
on n-type Ge,” Applied Physics Letters, 92, 022106 (2008).
[1.18] N. Tomonori, K. Koji and T. Akira, “A Significant Shift of Schottky Barrier
Heights at Strongly Pinned Metal/Germanium Interface by Inserting an Ultra-Thin
Insulating Film,” Applied Physics Express, 1, 051406 (2008).
[1.19] D. Connelly, C. Faulkner, D. E. Grupp and J. S. Harris, “A New Route to Zero-
Barrier Metal Source/Drain MOSFETs,” IEEE Transactions on Nanotechnology, 3,
p.98-p.104 (2004).
[1.20] M. Iyota, Y. Yamamoto, D. Wang, H. Yang and H.Nakashima, “Ohmic contact
formation on n-type Ge by dierect deposition of TiN,” Applied Physics Letters, 98,
192108 (2011).
13
Chapter 2
Experiment setup
2 Experimental setup
2.1 Device fabrication
2.1.1 Radio frequency magnetron sputtering.....................................14
2.1.2 Rapid thermal annealing.........................................................15
2.1.3 Vacuum evaporation...................................................................15
2.2 Four-point method.....................................................................16
2.3 Transmission electron microscopy................................................16
2.4 J-V characteristics
2.4.1 Thermionic emission theory...............................................18
2.4.2 Image-force-induced barrier lowering..............................18
2.5 Atomic force microscope...............................................................19
2.6 X-ray photoelectron spectroscopy.................................................20
2.7 Back-side secondary ion mass spectrometry...........................21
2.8 Circular transmission line method.............................................22
References
14
2.1 Device fabrication
2.1.1 Radio frequency magnetron sputtering
Thin films are the subject of matter for many applications and have got significant
importance in physical sciences and engineering. Sputtering is one important
technique used for thin film deposition. Radio frequency (RF) magnetron sputtering is
an enhanced sputter method which enables a higher deposition rate at low operating
pressure together with the possibility to obtain high quality films at low as well as high
substrate temperatures. In this study, the surface contact metals were deposited by RF
magnetron sputtering using the Ar gas. In the chamber filled with the Ar gas, the high
voltage is applied in high frequency between the target side and the sample side. The
surface atoms of target material are removed and deposited on a substrate by
bombarding the target with the ionized Ar atoms. The magnet, located behind the target,
enhances ionization and effectively directs the sputtered atoms towards the substrate,
and the samples are not damaged by the plasma. Schematic diagram of this method is
shown in fig. 2.1.
Fig. 2.1 Schematic diagram of RF magnetron sputtering.
target
sample
ArAr
magnet
Ar
ion sheath
capacitive
coupling
15
2.1.2 Rapid thermal annealing
Rapid thermal annealing (RTA) was used for produce of Ni-silicide. The heat chamber
was vacuum and filled in nitrogen gas, so that the effect of prevention oxidation of the
sample. The samples were annealed by infrared ray for 1 minute.
2.1.3 Vacuum evaporation
Al was used for backside contact of Schottky diodes. Al was deposited by vacuum
evaporation method which is suitable for deposition of metallic thin films onto cool
surface. A suitable material (the source), in this study using Al, is placed inside the
vacuum chamber with a heater. When the temperature reaches the evaporation
temperature of the source, atoms or molecules start to leave the surface of the source
and travel in a more or less straight path until they reach another surface (substrate,
chamber wall, instrumentation). Since these surfaces are at much lower temperatures,
the molecules will transfer their energy to the substrate, lower their temperature and
condense. The schematic diagram of this method is shown in fig. 2.2.
Fig. 2.2 Schematic diagram of vacuum evaporation.
sampleAl source
16
2.2 Four-point method
In a planar IC technology, it is useful to define a quantity, called the sheet resistivity
(sh). That is because the thickness of conducting regions is uniform and normally
much less than both the length and width of the regions. sh of the sample was
measured by four-point method. In this method, put four probes on the sample in a
straight line, and the resistance is obtained by measuring difference of potential
between the two inner probes when a small current is passed through the two outer
probes as shown fig. 2.3.
Fig. 2.3 Schematic illustration of four-point method.
2.3 Transmission electron microscopy
Transmission electron microscopy (TEM) is one of the electron microscopes. In this
study, observations of silicide cross section surface were using TEM. By irradiating
electrons to the thin sample, some electrons are scattered and others are transmitted.
VI
I
sample
substrate
thickness
17
Because the amount of transmitted electrons depends on the structure or component of
each portion, the image is generated by the interference of the transmitted electrons.
In TEM, the specimen shape and surface structure in addition to information of the
internal material which is the degree of cohesion, crystalline patterns, presence of
lattice defect, and such as orientation directions of the crystal can be known by
observing the internal structure of the sample. Typically a TEM consists of three stages
of lensing as shown fig. 2.4. The stages are the condenser lenses, the objective lenses,
and the projection lenses. The condenser lenses are responsible for primary beam
formation, whilst the objective lenses focus the beam that comes through the sample
itself. The projection lenses are used to expand the beam onto the fluorescent screen
or other imaging device, such as film.
Fig. 2.4 Organizational illustration of the TEM.
illumination
source
condenser
lens
specimen
objective
lens
projection
lens
image
plane
fluorescent
screen
18
2.4 J-V characteristics
2.4.1 Thermionic emission theory
Current characteristics of Schottky diodes (J-V) were measured by semiconductor
parameter analyzer. In this study, the method of analyzing J-V data used thermionic
emission (TE) theory. Thermionic-field emission (TFE) and generation current from
depletion don’t been considered, as these effects are negligible in the prepared samples
in this study. From the TE theory,
1exp2
nkT
qV
kT
qTAJ
appBn, (2.1)
can be obtained where A* is the effective Richardson constant, T is the absolute
temperature, q is the electronic charge, Bn is the Schottky barrier height, k is the
Boltzmann’s constant, Vapp is the applied voltage, and n is the ideality factor (n-factor)
which is related to the slope. Bn and n-factor can be obtained by fitting of J-V
characteristics. A* can be obtained from temperature characteristics. If the Schottky
diode is applied values of reverse voltage greater than 3kT/q, eq. 2.1 can be reduced to
[2.1]
kT
qTAJ Bn
exp2* (2.2)
2.4.2 Image-force-induced barrier lowering
Image-force is the interaction due to the polarization of the conducting electrodes by
the charged atoms of the sample. The image-force effect cause the energy barrier for
electron transport across a metal-silicon interface to be lowered by
19
Ge
Bn
qE
4 (2.3)
where E is the electric field and Ge is the permittivity of Ge. The actual energy barrier
for electron transport in a Schottky barrier diode is (qBn-qBn) [2.2].
2.5 Atomic force microscope
The atomic force microscope (AFM) belongs to a series of scanning probe
microscopes invented in the 1980s. This series started with the scanning tunneling
microscope (STM), which allowed the imaging of surfaces if conducting and
semiconducting materials [2.3, 2.4]. With the STM it become possible to image single
atoms on flat surface. In parallel the scanning near-field optical microscope (SNOM)
was invented which allowed microscopy with light below the optical resolution limit
[2.5, 2.6]. The last one of the series of the AFM, invited by Binning et al [2.7]. The
AFM such as the magnetic force microscope and the Kelvin probe microscope has
become the most important scanning probe microscope. The AFM allowed the
imaging of the topography of conducting and insulating surfaces, in some cases with
atomic resolution. The principal behind the operation of an AFM is shown fig. 2.5.
The AFM tip is first brought close to the sample surface, and then the scanner makes
a final adjustment in tip-sample distance based on a set point determined by the user.
The tip is then scanned across the sample under the action of a piezoelectric actuator,
either by moving the sample or the tip relative to the other. A laser beam aimed at the
back of the cantilever-tip assembly reflects off the cantilever surface to a split
photodiode, which detects the small cantilever deflections. A feedback loop maintains
constant tip-sample separation by moving the scanner in the z direction to maintain the
20
set point deflection. Without this feedback loop, the tip would crash into a sample with
even small topographic features. By maintain a constant tip-sample separation and
using Hooke’s Law, the force between the tip and the sample is calculated. Finally, the
distance the scanner moves in the z direction is stored in the computer relative to spatial
variation in the x-y plane to generate the topographic image of the sample surface.
Fig. 2.5 Schematic illustration of AFM.
2.6 X-ray photoelectron spectroscopy
X-ray photoelectron spectroscopy (XPS) is one of the most effective method of
determining the elements, which composing the sample. XPS spectra are obtained by
irradiating a material with a beam of X-rays while simultaneously measuring the
kinetic energy and number of electrons that escape from the material being analyzed.
The relation of the energies can be expressed:
bk EEh (2.4)
where h is the energy of the x-ray, Ek is the kinetic energy of the emitted electron and
laser light
tip
split
photodiode
detector
sample
lens
21
Eb is the binding energy of the emitted electron. Because the value of h is constant,
Eb is determined by measuring Ek. The Eb is peculiar to each element and the elements
consisting of the sample is also determined. In this study, the chemical composition of
the sample was measured by hard XPS at Spring-8 BL46XU as shown fig.2.6 [2.8],
and the relative displacement of surface potential was calculated by the measure results.
Fig. 2.6 Diagrammatic illustration of the XPS system.
2.7 Back-side secondary ion mass spectrometry
Secondary ion mass spectrometry (SIMS) is a technique used in materials science and
surface science to analyze the composition of solid surfaces and thin films by
sputtering the surface of the specimen with a focused primary ion beam and collecting
and analyzing ejected secondary ions. For implanted profiles, the knock-on effects
when sputtering from a high concentration to lower concentration region will
sample
vertical
horizontal
polarization
vector
induced
X-ray beam
sensing face
energy
dispersion
directionphotoelectron
normal
sample
analyzer
entrance slit
irradiation
spot
22
significantly degrade the depth resolution. Backside SIMS depth profiling using
primary ion energies >3 keV has been shown to improve the implanted trailing edge
profile [2.9-2.12].The schematic comparing front with back side SIMS is shown in fig.
2.7.
Fig. 2.7 Comparing front with back side SIMS
for high concentration dopant at interface
2.8 Circular transmission line method
Transmission line method (TLM) is often used to determine the specific contact
resistance (c) of ohmic contact systems in semiconductor devise [2.13, 2.14]. Test
pattern of either rectangular or circular geometry is commonly used [2.15], as depicted
in fig. 2.8 and fig. 2.9. In rectangular contacts, the current flow at contact edge can
significantly affect the results of contact resistance measurement unless mesa
structures current flow patterns. In circular test patterns this complication can be totally
avoided without making mesa structures.
substrate
primary
ion beam
high concentration
dopant intensity
front side
SIMS
back side
SIMS
23
Fig. 2.8 Test pattern for ohmic contact characterization: Rectangular pattern
where W is the width of the pads, l is the length of the pads
and d is the contact pad separation.
Fig. 2.9 Test pattern for ohmic contact characterization and using this study: Circular
pattern, where a1 is the radii of the inner circular contact; a2 is
the radii of the outer region; and d is the difference between a1 and a2.
For equal sheet resistances (sh) under the metal and in gap, and for circular TLM
(CTML), the total resistance between the internal and external contacts is [2.16, 2.17]
1
2
21
20
211
10
1
ln2 a
a
LaK
LaK
a
L
LaI
LaI
a
LR
T
TT
T
TTshT
(2.5)
where I and K denote the modified Bessel function of the first order, and LT is transfer
length. LT is related to c of the metal/semiconductor contact and sh of the
semiconductor, as given by
W
l d
24
sh
cTL
(2.6)
For a2 ≫ 4LT, the Bessel function ratios 10 II and 10 KK tend to unity and RT
becomes
1
2
21
ln11
2 a
a
aaLR T
shT
(2.7)
For L ≫ d, Eq. (2.7) simplifies to
CLdL
R Tsh
T 22
(2.8)
where C is the correction factor [2.18]
1
2
12
1 lna
a
aa
aC
(2.9)
It can be seen from Eq. (2.8) that there is a linear relationship between RT and d. Thus,
LT and sh, can be obtained as shown below:
LT = (y-interception /slope) × 2 (2.10)
sh = (Slope) × 2a2 (2.11)
Using Eq. (2.6), Eq. (2.10) and Eq. (2.11), the value of c, can then be obtained:
shTc L 2
(2.12)
25
References
[2.1] S. M. SZE and KWOK K. NG: “PHYSISCS OF SEMICONDUCTOR DEVICS’’,
third edition, WILEY-INTERSCIENCE, p.157-p.176 (2007).
[2.2] Y. Taur and T. H. Ning: “Fundamentals of MODERN VLSI DEVICES,”
Cambridge University Press, p.114 (1998).
[2.3] G. Binnig, H. Rohrer, C. Gerber, E. Weibel, “Surface Studies by Scanning
Tunneling Microscopy,” Physical Review Letters, 49, p.57-P.61 (1982) .
[2.4] G. Binnig, H. Rohrer, C. Gerber, E. Weibel, “7×7 Reconstruction on Si(111)
Resolved in Real Space,” Physical Review Letters, 50, p.120-p.123 (1983).
[2.5] D.W. Pohl, W. Denk, M. Lanz, “Optical stethoscopy: Image recording with
resolution λ/20,” Applied Physics Letters, 44, 651 (1984).
[2.6] A. Lewis, M. Isaacson, A. Harootunian, M. Muray, “Development of a 500 Å
spatial resolution light microscope: I. Light is efficiently transmitted through λ/16
diameter apertures,” Ultramicroscopy, 13, p.227-p.232 (1984).
[2.7] G. Binnig, C.F. Quate, C. Gerber, “Atomic Force Microscope,” Physical Review
Letters, 56, p.930-p.933 (1986).
[2.8] C. S. Fadley, “X-ray photoelectron spectroscopy: From origins to future
directions,” Nuclear Instruments and Methods in Physics Research A, 601, p.8-p.31
(2009).
[2.9] K.Wittmaack, D. B. Poker, “Interface broadening in sputter depth profiling
through alternating layers of isotopically purified silicon: I. Experimental results,”
Nuclear Instruments and Method B, 47, p.224-p.235 (1990).
[2.10] J. R. Shappirio, R. T. Lareau, R. A. Lux, J. J. Finnegan, D. D. Smith, L. S. Heath
and M. Taysing-Lara, “Metal penetration and dopant redistribution beneath alloyed
26
Ohmic contacts to n-GaAs,” Journal of Vacuum Science & Technology A, 5, p.1503-
P.1507 (1987).
[2.11] V. Parguel, P. N. Favennec, M. Gauneau, Y. Rihet, R. Chaplain, H. L’Haridon
and C. Vaudry, “Gold diffusion in InP,” Journal of Applied Physics, 62, p.824-P.827
(1987).
[2.12] J. G. M. van Berkum, E. J. H. Collart, K. Weemers, D. J. Gravesteijn, K. Iltgen,
A. Benninghoven and E. Niehuis, “Secondary ion mass spectrometry depth profiling
of ultralow-energy ion implants: Problems and solutions,” Journal of Vacuum Science
& Technology B, 16, p.298-p.301 (1998).
[2.13] A. J. Willis and A. P. Botha, “Investigation of ring structures for metal-
semiconductor contact resistance determination,” Thin Solid Films, 146, p.15–p.20
(1987).
[2.14] G. K. Reeves and H. B. Harrison, “Obtaining the Specific Contact Resistance
from Transmission Line Model Measurements,” IEEE Electron Device Letters, 3,
p.111-p.113 (1982).
[2.15] G. S. Marlow and M. B. Das, “The effects of contact size and non-zero metal
resistance on the determination of specific contact resistance,” Solid-State Electronics,
25, p.91-p.94 (1982).
[2.16] S.S. Cohen and G.Sh. Gildenblat, “Metal-Semiconductor Contacts and Devices,”
VLSI Electronics, 13, p.424 (1986).
[2.17] M. Ahmad and B.M. Arora, “Investigation of AuGeNi Contacts Using
Rectangular and Circular Transmission Line Model,” Solid-State Electronics, 35,
p.1441-p.1445 (1992).
27
[2.18] D. Schroder, “Semiconductor Material and Device Characterization,” third
edition, WILEY-INTERSCIENCE, p.144-p.145 (2006).
28
Chapter 3
Composition
and morphology
of Ni-silicide films
3 Composition and morphology of Ni-silicide films
3.1 Process of Ni-silicide.......................................................................29
3.2 Measurement of sheet resistance and roughness.........................29
3.3 Analysis of the chemical composition............................................31
3.4 J-V characteristics of stacked silicide diode.................................31
3.5 Conclusions......................................................................................34
References
29
3.1 Process of Ni-silicide
The wafers used in this study were n-type Ge(100) with a doping density of 4×1016
cm-3. A set of Si/Ni(1.9nm/0.5nm) was cyclically stacked [3.1] for 8 times was
deposited by RF magnetron sputtering system after HF treatment of the substrates as
shown fig. 3.1. The values of Si/Ni layers thickness correspond to atomic
concentration of 2 to 1. The concept of this process is to suppress the interface reaction
between Ni and Ge substrate by Si deposition in addition to Ni.
Fig. 3.1 Schemes for Ni-silicide process of sputtered
cyclic deposition of Si/Ni layers.
3.2 Measurement of sheet resistance and roughness
The samples of deposition film were annealed in nitrogen gas at annealing
temperature ranging from 200 to 750 oC for 1 minute. Figure 3.2 and figure 3.3 show
sheet resistance (sh) and surface roughness of the films on annealing temperature,
respectively. For the sample with 5.5-nm-thick Ni layer, sh showed a large decrease
over 250 oC, which is attributed to the formation of NiGe. When the annealing
temperature is over 400 oC, the sh showed a large increase due to agglomeration of
the germanide which is shown in figure 3.2. On the other hand, for the sample with
stacked NiSi2, a gradual reduction in the sh was observed over 300 oC, and the value
became stable at annealing temperatures from 350 to 700 oC, which gives process
n-Ge(100) sub.
Si(1.9nm)
/Ni(0.5nm)
8 set of
Si/Ni layers
Annealing
NiSi2
n-Ge(100) sub.
30
compatibility for dopant activation in Ge devices.
Fig. 3.2 Annealing-temperature dependence of sheet resistance of stacked NiSi2 on
Ge substrate. 5.5-nm-thick Ni films on Ge substrates are also shown as references.
Fig. 3.3 Annealing-temperature dependence of surface roughness of
stacked NiSi2 on Ge substrate.
3.3 Bonding states of NiSi2 on Ge substrates
0
50
100
150
200
250
300
350
400
0 100 200 300 400 500 600 700
Annealing temperature (oC)
asdepo.
Ni (5.5nm)
StackedNiSi2
(10nm) agglomeration
wide processwindow
Sheet re
sis
tance (
/sq
.)rm
sR
ou
gh
ness (
nm
)
Annealing temperature (oC)
asdepo.
200 300 400 500 600 7000
2.0
4.0
6.0
31
The chemical bonding states of NiSi2 on Ge substrates were analyzed by XPS. Ni 2p3/2
spectra of the samples annealed at 500 oC and 800 oC are shown in figure 3.4. From
peak assignment, NiSi2 phase is confirmed when annealed at 500 oC, whereas at high
temperature annealing, NiGe phase start to appear. To obtain an abrupt NiSi2/Ge
interface, the process temperature should be maintained below 500 oC.
Fig. 3.4 Ni 2p3/2 XPS measurement of NiSi2 on Ge substrate.
3.4 J-V characteristics of stacked silicide diode
Fig. 3.5 shows the fabrication flow of Schottky diodes. Schottky diodes were
fabricated on HF-last n-type Si (100) substrates with a doping density of 4×1016 cm-3.
The surface contact metals were sputtered as shown in fig. 3.5. An Al film was formed
851852853854855856857
Binding energy (eV)
Inte
nsity (
a.u
.)
NiGeNiSiNiSi2
500 oC800 oC
Ni 2p3/2
h=7940 eV
TOA=80o
32
as a backside contact using vacuum evaporation after resist was eliminated.
Fig. 3.5 Experimental procedure of Schottky diode process
Fig.3.6 shows current-voltage characteristics of the stacked silicide and 5.5-nm-thick
Ni films on Ge substrates, which are also shown as references, at various annealing
temperature from 400 to 600 oC, including as-sputtered diodes. And J-V characteristics
of the Schottky diodes on various annealing temperature were extracted Bn and n-
factor as shown in fig. 3.7. Here, thermionic emission model was used for the
extraction with the effective Richardson constant A* was 143 A/cm2K2 in this study.
Bn determined for NiGe formed on Ni 5.5-nm-film and stacked NiSi2 annealed up to
500 C were within 0.54~0.57 eV and 0.57~0.58 eV, respectively. The ideality factor
of NiGe showed values of more than 2.0 when annealed over 500 oC. Meanwhile,
n-Ge substrate (4x1016 cm-3)
HF treatment
Diode patterning
Deposition by RF sputtering in Ar
Backside Al contact
Annealing
{Ni(0.5nm)+Si(1.9nm)} x 8
33
owing to thermal stability of NiSi2 films, ideality factor lower than 1.2 could be
maintained up to 500 oC, but the values of ideality factor were scattered at 600 oC.
Therefore, stacked NiSi2 diode achieved ideally stable interface until 500 oC.
Fig. 3.6 J-V characteristics of the stacked-silicide diodes.
Cu
rrent density (
A/c
m2)
30
20
10
0
-10
-20
-30
Anode voltage (V)
0 0.5 1.0-0.5-1.0
asdepo.
400oC
500oC600oC
n-Ge (100)(Nd=4x1016cm-3)
Si(1.9nm)/Ni(0.5nm)
n-Ge sub.
34
Fig. 3.7 (a) Bn and (b) ideality factors of Ge Schottky diodes with
stacked NiSi2 and 5.5-nm-thick Ni film.
3.5 Conclusions
NiSi2 with cycles of Si/Ni stacked films on Ge substrate showed stable sheet resistance
in the temperature range from 350 oC to 700 oC. This temperature range is wider than
the corresponding temperature range obtained for NiGe formed on Ni 3- and 5.5-nm-
thick films. Bn determined for Ge Schottky diode with stacked NiSi2 exhibit stable
values within 0.57~0.58 eV even after annealing at temperature up to 500 oC.
Furthermore, the ideality factors of this diode indicated less than 1.2 even after
annealing at temperature up to 500 oC.
asdepo. 400 500 600
Annealing temperature (oC)
Stacked NiSi21.0
2.0
3.0
Ide
alit
y fa
cto
r
Stacked NiSi2
Ni(5.5nm)0.50
0.55
0.60
0.45
B
n(e
V)
(a)
(b) Ni(5.5nm)
35
References
[3.1] A. Ishizaka and Y. Shirali, “Solid-phase epitaxy of NiSi2 layer on Si(111)
substrate from Si/Ni multi-layer structure prepared by molecular beam deposition,”
Surface Science, 174, p.671-p.677 (1986).
36
Chapter 4
Schottky barrier
height lowering with
P incorporation
4 Schottky barrier height lowering with P
incorporation
4.1 Incorporation P atoms...................................................................37
4.2 Observation of cross-section surface.............................................37
4.3 Analysis of concentration distribution.......................................40
4.4 Measurement of J-V characteristics..................................41
4.5 Extraction of contact resistance................................................42
4.6 Extraction of Schottky barrier height......................................44
4.7 Observance of band bending........................................................46
4.8 Conclusions......................................................................................51
References
37
4.1 Incorporation P atoms
Fig. 4.1 shows schematic illustration of inserting P at the silicide/substrate interface
of the sample. In P case, a 0.68-nm-thick-Ni3P layer was deposited instead of the first
Ni layer. The 0.68-nm-thick-Ni3P corresponded to the same Ni atomic concentration
of a 0.5-nm-thick-Ni. An Al film was formed as a backside contact using vacuum
evaporation after resist was eliminated.
Fig. 4.1 P incorporation scheme for stacked-silicide process.
4.2 Observation of cross-section surface
As shown in fig. 4.2, TEM images of silicide/Ge interface formed NiSi2 after
annealing at 500 oC (Fig. 4.2(a)) and 800 oC (Fig. 4.2(b)) for 1 min in N2 ambient to
form NiSi2. TEM images revealed the formation of 10-nm-thick stacked silicide,
atomically flat interface and surface at 500 oC because consumption of Ge from
substrate is limited to the first Ni layer. Furthermore, NiSi2/Ge interface could be find
n-Ge(100) sub.
Si(1.9nm)
/Ni(0.5nm)
Ni3P(0.68nm)
Si(1.9nm)
7 set of
Si/Ni layers
38
the thin heterogeneous layer. On the other hand, at 800 oC annealing, interface and
surface came to uneven because of agglomeration and reaction to substrate.
Fig. 4.2 TEM images of stacked silicidation process at
(a) 500 oC and (b) 800 oC annealing.
Using energy dispersive X-ray spectroscopy (EDX) analyzed each layer of TEM
images at 500 oC annealing. At the bulk of NiSi2 layer, the EDX detected C, O, Ar, Ge,
Si, and Ni in shown fig. 4.3. At the bright thin layer of NiSi2/Ge interface, the EDX
detected P in addition to C, O, Ar, Ge, Si, and Ni in shown fig. 4.4. At the substrate
near NiSi2/Ge interface, the EDX detected C, O, Ge, and Si in shown fig. 4.5. Those
indicate that the bright thin layer is mixing layer of Ni, Si, P and Ge. The mixing layer
10nmGe sub.
100nm Ge sub.
500oC 500oC
NiSi2
800oC
100nm
(a)
(b)
39
Fig. 4.4 TEM image and EDX spectrum of the bulk of NiSi2.
Fig. 4.5 TEM image and EDX spectrum of the bright layer at NiSi2/Ge interface.
0 2 4 6 8 10
Energy (keV)
0
50
100
150
200
250
300
Counts
C
O
Ni
Ge
Si
Ar
Ni
NiGe
10nmGe sub.
500oC
NiSi2
0 2 4 6 8 100
50
100
150
200
250
300
Energy (keV)
Cou
nts
C
O
Ni
Ge Si
P Ar
Ni
Ni
Ge10nmGe sub.
500oC
NiSi2
40
Fig. 4.5 TEM image and EDX spectrum of the substrate near NiSi2/Ge interface.
4.3 Analysis of concentration distribution
Concentration distribution of incorporated P were examined at as-sputtered diodes
and 500 oC annealing with backside SIMS measurement as shown in fig. 4.9. It showed
that incorporated P atom diffused to the substrate and NiSi2 and remained NiSi2/Ge
interface owing to thermal annealing. Therefore, impurity position can be controlled
because stacked silicidation process can be suppressed interface reaction.
0 2 4 6 8 10
Energy (keV)
0
50
100
150
200
250
300
Co
unts
C
O
Ge
Si
Ge
10nmGe sub.
500oC
NiSi2
41
Fig. 4.9 Incorporated P profiles of backside SIMS
measured with 500 oC annealing.
4.4 Measurement of J-V characteristics
Fig. 4.6 shows the J-V characteristics of diode with P incorporation with annealing
temperature from 400oC up to 600oC as a parameter. Incorporation of P atoms at
NiSi2/Ge interface followed by annealing exhibits ohmic characteristic. It is speculated
that the change in J-V characteristic results from Bn lowering due to the configuration
of induced dipoles at the interface by a P atom at substitutional sites of a Ge atom
located very closely to the interface in the similar case of NiSi/Si junction [4.1].
0 4010 5020 6030
Depth (nm)
1016
1017
1018
1019
1020
1021
1022
NiSi2 Ge sub.
after 500 oC
annealing
before
P c
on
ce
ntr
atio
n (
cm
-3)
42
Fig. 4.6 J-V characteristics of the stacked-silicide diodes with P incorporation.
4.5 Extraction of contact resistance
Electrical characterization of P-incorporated NiSi2 on n-Ge substrates was performed
with CTLM with proper correction factor. Fig. 4.7 shows current-voltage
characteristics of NiSi2 electrodes with P atom incorporation at various annealing
temperature from 200 to 800 oC, including as-sputtered diodes. A small current
obtained from as-sputtered diode, due to double Schottky diode facing each other, was
found to markedly increase over 300 oC annealing, and the current showed gradual
increase with higher temperature. When annealed at 700 oC, non-linear behavior was
observed, presumably due to formation of NiGe at interface. The extracted specific
contact resistance (c) on annealing temperature is shown in fig. 4.8, where an order
of 10-3 cm2 was obtained. Considering the doping density of 1016 cm-3, the obtained
Anode voltage (V)
0 0.5 1.0-0.5-1.0
Curr
ent density (
A/c
m2)
30
20
10
0
-10
-20
-30
asdepo.
600oC500oC
400oC300oC
Si(1.9nm)/Ni(0.5nm)
n-Ge sub.
Ni3P(0.68nm)
n-Ge (100)(Nd=4x1016cm-3)
43
value can be understood either by extreme shallow doping of P atoms at very surface
of the Ge substrate or by Schottky barrier height modulation.
Fig. 4.7 Current-voltage characteristics of CTLM pattern.
60mm
30mm
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
Cu
rre
nt
(mA
)
-1.0 -0.5 0.0 0.5 1.0
Voltage (V)
as depo.
200oC
700oC
600oC
300oC
800oC
44
Fig. 4.8 Extracted contact resistance on annealing temperature.
4.6 Extraction of Schottky barrier height
The c, is determined by field emission (FE) and thermionic-field emission (TFE), in
addition to the standard thermionic emission (TE). The most widely accepted model
for FE and TFE is given by Padovani and Stratton [4.2, 4.3] and is used in this work.
Yu had utilized this theory to calculate c [4.4] but the tunneling effective mass used
was only a variable, rather than a real value (the tunneling effective mass is important
since the tunneling probability is exponential with mass). There is a useful term E00
defined as
sm
NqE
200
(4.1)
200 300 400 500 700
10-1
10-2
10-3
Conta
ct
resis
tance (
cm
2)
Annealing temperature (oC)
600
n-Ge (4x1016cm-3)
45
where m* is the effective mass, N is the doping level, and s is the permittivity. In this
work, 𝐸00 ≈ｋ𝑇 based on E00 = 1.74×10-22 J. Hence, in the medium doping regime,
TFE dominates, and
kT
E
kT
E
qTqA
Ek
nBn
c000000
cothcosh
kT
q
kTEE
q nnBn
0000 cothexp
(4.2)
where A* is the effective Richardson constant. In this work, A* = 143 A/cm2K2. In the
case that Nd = 4×1016 cm-3, calculated c as (2.7) at various Bn were shown in fig. 4.9.
In the situation that c = 8.0×10-3 cm2 asfig. 4.8, Bn = 0.4 eV. This indicates lowering
Bn for compared to Bn = 0.58 eV of NiSi2/Ge diodes without incorporation as shown
in fig.3.7 (a).
Fig. 4.8 Calculated contact resistance
on Schottky barrier heights at Nd = 4×1016 cm-3.
Co
nta
ct
resis
tan
ce
(
cm
2)
100
102
10-2
10-4
101
10-1
10-3
10-5
Schottky barrier height Bn (eV)
0.2 0.3 0.4 0.5 0.6
Nd ＝ 4x1016cm-3
46
4.7 Observance of band bending
Fig. 4.10 shows Ge 2p3/2 spectra with and without P atom incorporation at 500 oC
annealing by XPS with an x-ray energy of 8 keV. During measurement, NiSi2
electrodes and Ge substrates are electrically connected, so as to fix the Fermi level
throughout NiSi2/Ge system.
Fig. 4.10 Ge 2p3/2 spectra of NiSi2/Ge with and without P incorporation.
Assuming a potential profile of 𝜓(𝑧), where z is the distance from the surface of the
film or bulk, the total photoelectrons at a binding energy (BE), J(E), from a core level
can be written as
dzzEEIeEJ
z
)(sin)( 00
sin
(4.3)
where I(E−E0) is a typical spectrum with a peak energy of E0. , , and E0 are the
inelastic mean free path (IMFP), take-off angle measured from the sample surface and
without
incorporation
P incorporation
1219 1218 1217
Binding energy (eV)
1216
Inte
nsity (
a.u
.)
Ge 2p3/2 spectrah=7940 eV
TOA=80o
500 oC 1min
0.3 eV
47
BE of electrically neutral region, respectively. In the case of germanium substrate,
potential profiles of depletion condition are approximated as
2
21)(
z
qNz
sGe
bs
(4.4)
where 𝜓𝑠 , 𝜀𝐺𝑒 , q, and Nb are the surface potential at z = 0, the permittivity of
germanium , the electronic charge, and the concentration of either donor or acceptor,
respectively [4.5]. The core energy level also bends along with the potential profile at
the surface. Therefore, the measured spectrum consist of photoelectrons with different
peak energies as shown in fig. 4.11.
Fig. 4.11 Band bending of Ge surface results in a spectra broadening.
By deconvolution of the spectrum, the bending profile
as well as the surface potential can be derived.
Deconvolution of the spectrum enables to extract the bending profile in the substrate
as well as the surface potential. With an x-ray energy of 8 keV, the IMFP of Ge
Energy
Energy
Ge 2p
VB
CBBn
3/2
48
becomes as large as 10 nm, so that photoelectrons coming from as deep as 30 nm can
be collected. Fig. 4.12(a) and fig. 4.13(a) show the fitting Ge 2p3/2 spectrum of
NiSi2/Ge without and with P atom incorporation at 500 oC annealing, respectively, and
the spectrum was calculated composition of Ge substrate phase and NiGe phase. Fig.
4.12(b) and fig. 4.13(b) show deconvolution of Ge substrate without and with P atom
incorporation, respectively. The BE of the peak intensity along with the depth shifts to
higher energy direction owing to the bend up, as expected by .43 eV. The BE of the
peak intensity along with the depth shifts to lower energy direction owing to the bend
down, as expected 0.14 eV. A clear shift toward higher binding energy indicates
downward band bending of the substrate to increase the surface potential, which
implies un-pinned contact as shown in fig. 4.14.
49
Fig. 4.12 (a) Fitting Ge spectrum 2p3/2 of NiSi2/Ge without P incorporation.
(b) Deconbolution of the spectrum of Ge substrate.
NiGeGe sub.
Inte
nsity (
a.u
.)In
ten
sity (
a.u
.)
1220 1218 1216
Binding energy (eV)
Ge 2p3/2
h=7940 eV
TOA=80o
500 oC 1min
deconvolutioninterface
bulk
NiSi2 only
(a)
(b)
50
Fig. 4.13 (a) Fitting Ge spectrum 2p3/2 of NiSi2/Ge with P incorporation.
(b) Deconbolution of the spectrum of Ge substrate.
NiGeGe sub.
Inte
nsity (
a.u
.)In
ten
sity (
a.u
.)
1220 1218 1216
Binding energy (eV)
deconvolution
bulk
interface
P incorporation
Ge 2p3/2
h=7940 eV
TOA=80o
500 oC 1min
(a)
(b)
51
Fig. 4.14 Schematic illustration of assumed band bending of stacked silicide films
with and without P incorporation.
4.8 Conclusions
A novel NiSi2 electrode with P atom incorporation to obtain Ohmic characteristics on
n-Ge has been performed. Incorporation of P atoms has been found to increase the
surface potential to effectively tune the Schottky barrier height. From electrical
characteristics, Ohmic contact with resistance less than 10-2 cm2 has been achieved
with low temperature process as low as 300 oC. XPS has revealed surface potential
shift, which indicates that the metal/germanium interface has been un-pinned.
BE
s
Z
distance from surface Ge
(3~36nm)0
s,P with P incorporation
NiSi2 only
Ge 2p3/2
(3~30nm)
52
References
[4.1] T. Yamauchi, Y. Nishi, Y. Tsuchiya, A. Kinoshita, J. Koga and K. Kato, “Novel
doping technology for a Inm NiSi/Si junction with dipoles comforting Schottky (DCS)
barrier,” IEDM Electron Devices Meeting, p.963-p.966 (2007)
[4.2] F. A. Padovani and R. Stratton, “Field and thermionic-field emission in Schottky
barriers,” Solid-State Electronics, 9, p.695-p.707 (1966).
[4.3] F. A. Padovani, “The voltage–current characteristic of metal–semiconductor
contacts,” Semiconductors and semimetals, 7, p.75-p.146 (1971).
[4.4] A. Y. C. Yu, “Electron tunneling and contact resistance of metal-silicon contact
barriers,” Solid-State Electronic, 13, p.239-p.247 (1970).
[4.5] Y. Taur and T. H. Ning: “Fundamentals of MODERN VLSI DEVICES,”
Cambridge University Press, p.63-p.78 (1998).
53
Chapter 5
Conclusions
54
NiSi2 with cycles of Si/Ni stacked films on Ge substrate showed stable sheet resistance
in the temperature range from 350 oC to 700 oC. This temperature range is wider than
the corresponding temperature range obtained for NiGe formed on Ni 3- and 5.5-nm-
thick films. Bn determined for Ge Schottky diode with stacked NiSi2 exhibit stable
values within 0.57~0.58 eV even after annealing at temperature up to 500 oC.
Furthermore, the ideality factors of this diode indicated less than 1.2 even after
annealing at temperature up to 500 oC. Insertion of P atoms at silicide/germanium
interface has effectively changed the diode characteristics to Ohmic with resistance
less than 10-2 cm2 one even at low temperature annealing as low as 300 oC and up to
600 oC. The contact resistance extracted Bn which is 0.40 eV lowering than 0.58 eV
as NiSi2/Ge Schottky diode without P incorporation. This indicated electrically
lowering Bn. And XPS has revealed surface potential shift, which indicates that the
metal/germanium interface has been un-pinned. The above un-pinned process gives
further insights into low contact resistance process as well as interface researches.
55
Publications and Presentations
[Publications]
[1] Ryo Yoshihara, Yuta Tamura, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “Thermally stable NiSi2 for Ge contact with Schottky
barrirer height modulation capability”, to be published in ECS Transactions, 50,
p.217-p.222 (2012)
[International Presentations]
[1] Ryo Yoshihara, Yuta Tamura, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “Thermally stable NiSi2 for Ge contact with Schottky
barrirer height modulation capability”, 222th ECS Meeting, Hawaii, October
(2012).
[2] Ryo Yoshihara, Yuta Tamura, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, and Hiroshi Iwai, “A Novel Ohmic Contact Process for n-Ge Substrates”,
WIMNACT 37, Tokyo, February (2013).
56
[Domestic Presentations]
[1] Ryo Yoshihara, Yuta Tamura, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, Hiroshi Iwai, “NiSi2 for Ge contact with Schottky barrier height
modulation capability”, 73th JSAP Autumn Meeting, Yamagata University,
September (2012).
[2] Ryo Yoshihara, Yuta Tamura, Kuniyuki Kakushima, Parhat Ahmet, Yoshinori
Kataoka, Akira Nishiyama, Nobuyuki Sugii, Kazuo Tsutsui, Kenji Natori, Takeo
Hattori, Hiroshi Iwai, “Observation of surface band bending of P incorporated
NiSi2/n-Ge using hard x-ray photoelectron spectroscopy”, 60th JSAP Spring
Meeting, Waseda University, March (2013).
57
Acknowledgments
First of all, I would like to express my gratitude to my supervisor Associate Prof.
Kuniyuki Kakushima for his continuous encouragement and advices for my study. He
also gave me many chances to attend conferences. The experiences are precious for
my present and future life.
I deeply thank to Prof. Yoshinori Kataoka, Prof. Akira Nishiyama, Prof. Nobuyuki
Sugii, Prof, Hitoshi Wkabayashi, Prof. Kazuo Tsutsui, Prof. Kenji Natori, and Prof.
Hiroshi Iwai for useful advice and great help whenever I met difficult problem.
I would like to thank Prof. Hiroshi Nohira of Tokyo City University for XPS
observation and Park Systems Japan Inc. for AFM observation.
I also thank research colleagues of Iwai Lab. for their friendship, active many
discussions and many of encouraging words.
I would like to appreciate the support of secretaries, Ms. Nishizawa and Ms.
Matsumoto.
Finally, I would like to thank my parents Hidenori and Kazue and my brother Itsuki
and Kei for their endless support and encouragement.
Ryo Yoshihara
February, 2014
