Interface Para Armar Con Pic AN2295

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Freescale Semiconductor

Application Note

Document Number: AN2295Rev. 8, 08/2006

Contents

Freescale Semiconductor, Inc., 2006. All rights reserved.

1 Project Objectives

The developers serial bootloader for M68HC08 andHCS08 microcontroller units (MCUs) allows in-circuitreprogramming of Freescale SemiconductorsM68HC08 and HCS08 FLASH devices using standardcommunication media such as a serial asynchronous

port. As soon as the MCU is programmed with thebootloader, the MCU memory can be modified in-circuit.Because of its ability to modify MCU memory in-circuit,the serial bootloader is a utility that may be useful indeveloping applications.

This application note is for embedded-softwaredevelopers interested in alternative reprogrammingtools. The developers serial bootloader is not intended tocompete with existing MON08 development tools; it is acomplementary utility for either demo purposes or

applications originally developed using MMDS andrequiring minor modifications to be done in-circuit. Theserial bootloader offers a zero-cost solution to

1 Project Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 FC Protocol Description. . . . . . . . . . . . . . . . . . . . . . . . . . 33 FC Protocol, Version 1, M68HC908 Implementation. . . 12

4 FC Protocol, Version 2, HC9S08 Implementation . . . . . 18

5 FC Protocol, Version 3, Large M68HC08Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

6 MCU Slave Software . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7 PC Bootloader Master Software . . . . . . . . . . . . . . . . . . 41

8 Bootloading Procedure Demonstration . . . . . . . . . . . . . 469 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Developers Serial Bootloaderfor M68HC08 and HCS08 MCUsby: Pavel Lajsner

Freescale Czech System CenterRosnov p.R., Czech Republic


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Developers Serial Bootloader for M68HC08 and HCS08 MCUs, Rev. 8

Project Objectives

Freescale Semiconductor2

applications already equipped with a serial interface and SCI pins available on a connector. This documentalso describes other programming techniques:

FLASH reprogramming using ROM routines

Simple software SCI

Use of the internal clock generator

PLL clock programming EEPROM programming (AS/AZ HC08 families)

Figure 1. Top Level View

1.1 Project Goals

Freescale Semiconductor M68HC08 MCUs use a standard monitor-mode interface for FLASH

programming. Configuration of monitor mode requires a specific clock and high voltage (monitor-mode

entry voltage VTST = VDD+ 2.5 = 8 V) applied to the IRQ pin upon MCU startup. Also, establishingmonitor-mode communication uses a few pins. If the application already uses a standard serial SCIinterface for communication, a different code (the bootloader) can be used to communicate with the PCusing the same interface used for reprogramming.

The bootloader can be used for only reprogramming, not for in-circuit debugging. The bootloader is alow-cost, in-circuit programming solution.

1.2 Bootloader Application Requirements

Low memory useThe bootloader must use as little memory as possible. Other versions ofbootloaders use more than 1 KB of memory, which is unacceptable on devices with 3 KB of

memory available (such as the MC68HC908JK3). The solution described in this documentimplements all features as simply as possible, excluding checksums, etc. The target size is less than500 B.

Low pin-count This bootloader uses standard (already implemented) means of communication(typically SCI on boards primarily intended for communication). The standard SCI uses two wires(RxD, TxD). No additional wires are used to start bootloader.

Windows or Linux PCHC08 embedded application

(under development

or under re-configuration)


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FC Protocol Description


Freescale Semiconductor 3

Transparency with respect to the user S19 file The complete application should betransparent to the user code S19 file. This means no adjustments are required in the S19 file. OtherM68HC08 and HCS08 bootloader applications require modification to interrupt vectors or othermodifications to the S19 file for it to accept the bootloader.

1.3 Demo Features of Bootloader Application

This document describes several different M68HC(S)08 bootloader implementations that vary mainly

because the target M68HC(S)08 MCUs have different features. Several features of the M68HC(S)08Family are also demonstrated, making this document useful to a wider audience than those who requireonly the bootloader. The different M68HC(S)08 implementations also demonstrate the following features:

Use of built-in ROM routines for FLASH self-programming (see also AN1831/D, AN2545/D and

AN2635/D in References).

User implementation of in-circuit reprogramming routines on ROM-less MCUs such as theMC68HC908GPFamily or the MC9S08GB/GTFamily

Use of different implementations of the FLASH block protection technique (MC68HC908GP,

MC68HC908GR, MC68HC908EY, vs. MC68HC908JK/JLFamilies) Implementation of software SCI on SCI-less MCUs, such as the MC68HC908JK/JLFamily

Use of the internal clock generator and its trimming (for the MC68HC908KXFamily), for HCS08Families (MC9S08GB/GT)

EEPROM programming (for the MC68HC908AB/AS/AZFamily)

USB communication implementation on USB2.0 Full-speed HS08 MCUs, such as theMC68HC908JWFamily

2 FC Protocol Description

As described in Bootloader Application Requirementsan implementation must be as simple as possibleand use as little memory as possible. Therefore, the protocol running between the master PC and slaveMCU is also very simple. It is called FC protocol because one significant character (the acknowledge, or

ACK) $FC or 11111100b is used.

This section describes the protocol used to communicate between the PC and target MCU to reprogramthe MCU. An explanation of family-specific implementation features follows a general description.

Figure 2is a simplified state diagram that shows separate states of the bootloader, which this document

describes.


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Figure 2. Simplified Flow Diagram of the Bootloader Application

2.1 Initial-Hook Up

Several methods exist to enter bootloader mode. Several other solutions use a certain level on certainpinmethod. An example of this: If logic 0 appears on an IRQ pin during MCU startup, the bootloadercode starts. Otherwise, the user code starts.

Because the developers serial bootloader application must use the lowest number of pins, a certaincharacter at a certain time method is used. This means that the MCU sends out an ACK character throughthe serial interface and waits for an answer. If no character is received within the specified time (hook-uptime-out), the process continues with the user code.

If this becomes a limitation for any reason, the user may modify the bootloader code to meet theapplication needs (e.g., an additional simple IRQ pin test at startup can be implemented). See more inM68HC08 System Limitations.

2.2 Clock Source

FC protocol allows two scenarios, depending on whether the MCU runs on a known and exact frequencyor uses an RC (resistor, capacitor) clock or an internal clock (or any clock unknown at compile time).

2.2.1 Unknown MCU Communication Speed

If the frequency is uncertain (unknown at compile time), the MCU will not check if an incoming ACKcharacter conforms only to the $FC pattern. Because of the MCU clock tolerance, several characters canbe interpreted differently instead of the original $FC sent out by the PC (Figure 3). The $FC pattern checkon the MCU side can be eliminated completely, which saves MCU memory.

RESET

COMMANDS

CALIBRATION

HOOK-UPCOMMUNICATION

READ

WRITE

ERASE

IDENT

QUIT

RESET SOURCE

TEST

CODE

USER

POWER-ON

TIME-OUT


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Figure 3. Matching Different Communication Speeds

Table 1shows the characters that can be correctly received (i.e., without framing or noise errors) iftransmit and receive speeds are not equal..

If the MCU transmits to the PC at an unmatched data rate, the PC receives (and accepts) characters thatare different from the $FC character. The PC accepts all characters from the mentioned set ($FF, $FE, $FC,$F8, $F0, $E0, $C0, $80, $00). If a character is received, an ACK is immediately sent back to the MCU.After the MCU recognizes this answer, it enters the next phase, Slave Frequency Calibration.

Table 1. PC to MCU Transmiss ion Unmatched Data Rate

PC Data Rate MCU Data RateCharacterReceivedin Binary

CharacterReceived

in Hex

9600 9600*1/3 11111111b $FF

9600 9600*2/3 11111110b $FE

9600 9600*3/3 11111100b $FC

9600 9600*4/3 11111000b $F8

9600 9600*5/3 11110000b $F0

9600 9600*6/3 11100000b $E0

9600 9600*7/3 11000000b $C0

9600 9600*8/3 10000000b $80

9600 9600*9/3 00000000b $00

D0 D1 D2 D3 D4 D5 D6 D7 STOPSTARTIDLEBOTH MCU AND PC

DATA RATES ARE EQUAL

MCU RECEIVES 0XFC

MCU CLOCK IS

3 TIMES FASTER

MCU RECEIVES 0X00

MCU CLOCK IS

3 TIMES SLOWER

MCU RECEIVES 0XFF

TIME

D0D1D2D3D4D5D6D7

STOP

START

IDLE

D0 D1STARTIDLE

PC TRANSMITS 0XFC CHARACTER AT PROPER DATA RATE:


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2.2.2 Known MCU Communicat ion Speed

If the frequency is certain (known at compile time), the MCU will be configured to match exactly thecommunication speed of the PC. All characters are received correctly and without distortion.

The MCU sends $FC to the PC, which immediately sends an ACK to the MCU. After the ACK is received,the MCU also (formally) enters the Slave Frequency Calibrationphase.

2.3 Slave Frequency Cal ibrat ion

During this phase, the MCU clock is calibrated. Until now, the PC has communicated with the MCU at a

speed that could be from 33% to 300% tolerance. During this phase, the MCU communication speed mustbe adjusted to match the PC communication speed.

After the PC enters the calibration phase, the no-break time-out starts. If a correct ACK character ($FC) isnot received within this period, a break character is sent at the communication data rate.

A break character consists of 10 consecutive logical zeros. For example, at a 9600 baud data rate, its

high-low-high pulse lasts 10 x 104 s = 1.04 ms.

The MCU then measures the break character length and determines whether its clock is too fast or too slow.The MCU then makes an adjustment to its system clock (or an adjustment of receive routines if, forexample, software serial communication is used). This can be repeated as many times as needed for the

MCU to achieve the proper clock speed.

After the MCU is calibrated to the correct clock (or after the receive routines are calibrated), the ACKcharacter is sent to the PC to stop sending calibration characters (Figure 4).


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Figure 4. Start-Up Communication with Calibration

If the MCU is operating at the correct data rate (no calibration is possible or needed, and the MCU clockis crystal driven), the PC can immediately send an ACK, skipping the calibration phase entirely(Figure 14).

MCU PC

ACK

ACK

HOOK-UPTIME-OUT

NO-BREAKTIME-OUT

break

break

ACK

CALIBRATION UNSUCCESSFULOR ONLY ROUGH CORRECTION DONE

CALIBRATION SUCCESSFUL

ACK IS SENT AT CORRECT DATARATE

ACK IS SENT AT UNCERTAIN DATA RATE

FROM NOW ON, THE COMMUNICATION IS AT THE CORRECTLY SPECIFIED DATA RATE

ONLY 0XFC CHARACTER CAN BE RECEIVED

NO

-BREAKTIME-OUT


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Figure 5. Start-Up Communication Without Calibration

2.4 Interpret ing MCU Commands

After communication between the MCU and the PC is established, the MCU enters the main commandinterpreter loop. The MCU executes simple commands to reprogram its own nonvolatile memory. Thecommunication is conducted on a master-slave mechanism: the PC issues the commands, the MCUexecutes them and acknowledges the completion of each command, either by data or by a single ACKcharacter.

The minimal set of commands is comprised of:

Ident Command

Quit Command

Two more basic commands are implemented for pure reprogramming:

Erase Command Write Command

If the user needs a verification feature, one additional (read) command must be compiled into the MCUcode. For pure reprogramming purposes (minimal configuration), it is not required.

Read Command

MCU PC

ACK

ACK

ACK

NO CALIBRATION REQUIRED

ACK IS SENT AT CORRECT DATA RATE

ACK IS SENT AT SPECIFIED DATA RATE

CORRECT $FC CHARACTER IS RECEIVED WITHIN TIME-OUT

HOOK-UPTIME-OUT

NO-BREAKTIME-OUT


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Figure 6. Typical Command and Response

2.4.1 Ident Command

The indent command (coded as I, $49) has no additional fields.

This command is immediately issued by the PC after communication is established. The purpose of theindent command is to let the PC know several basic properties of the MCU being programmed. All

multi-byte fields are sent with MSB first. Version number and capability table 1 byte

Figure 7. Version Number and Capabili ty Table

RCS Read Command Supported Flag

The RCS flag informs the PC if the read command is supported (implemented). If not, all calls to the readroutine are ignored by the MCU and no response is sent back to the PC. The PC software warns the userthat no read capabilities are available.

Supported

Not supported (usually due to memory constraints)

RSVD Reserved

These bits are reserved for future use, unused, and should be set to 0.

VER Protocol Version

2.4.2 FC Protocol Version 1 (M68HC08)

Version 1 of the protocol is for M68HC08 MCUs. In version 1, additional fields are defined as:

Start address of reprogrammable memory area 2 bytes

End address of reprogrammable memory area + 1 2 bytes

COMMAND ADDRESS DATA TO MCU

DATA FROM MCU

* Dashed fields are not always implemented, data from the MCU may contain only an ACK character instead.

PC TO MCU COMMAND

MCU TO PC RESPONSE

LENGTH

7 6 5 4 3 2 1 0

RCS RESERVED VERSION NUMBER

BIT


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Address of Bootloader User Table 2 bytes

Start address of MCU interrupt vector table 2 bytes

Length of MCU erase block 2 bytes

Length of MCU write block 2 bytes

Bootloader data (specific bootloader info, see device-specific implementation; compared in

Table 2) 8 bytes Identification string, zero terminated bytes

Figure 8. Ident Command (FC Protocol Version 1, M68HC08)

2.4.3 FC Protocol Version 2 (HCS08) and FC Protocol Version 3 (largeM68HC08)

Version 2 of the protocol is for HCS08 MCUs; version 3 is for large M68HC08 (HC08 with two or more FLASH memory banks). In both versions, additional fields

are defined as:

System device Identification register content 2 bytes (unused in protocol version 3, coded as$FFFF)

Number of reprogrammable memory areas (N) 1 byte

Start address of reprogrammable memory area #1 2 bytes

End address of reprogrammable memory area #1 + 1 2 bytes

Start address of reprogrammable memory area #2 2 bytes

End address of reprogrammable memory area #2 + 1 2 bytes

...

Start address of reprogrammable memory area #N 2 bytes

End address of reprogrammable memory area #N + 1 2 bytes

Address of relocated interrupt vector table 2 bytes

Start address of MCU interrupt vector table 2 bytes

Length of MCU erase block 2 bytes

Length of MCU write block 2 bytes

Identification string, zero terminated bytes

I ($49)

VERSION

PC TO MCU COMMAND

MCU TO PC RESPONSE

START

MEM

END

MEM

BOOTLOADER

USER TABLE

INTERRUPT

VECTOR TABLE

ERASE

BLOCK SIZE

WRITE

BLOCK SIZEID STRING 0

CAPS.

BOOTLOADER

DATAAND


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Figure 9. Ident Command (FC Protocol Versions 2 and 3, HCS08)

2.4.4 Erase Command

The erase command (coded as E, $45) has only an address field, no length or data fields. The start addressis a 2-byte field, MSB first.

The MCU erases the address block where the specified address resides. The length of block to be erased

is equal to the erase-block size (typically dependent on hardware).

After the MCU completes execution of the command, the ACK ($FC) character is sent back to the PC. Theerase commands minimum and maximum execution times are not specified.

Figure 10. Erase Command

2.4.5 Write Command

The write command (coded as W, $57) has both address and data fields. The address contains the firstaddress to be programmed. The first byte is the length followed by the number of bytes to be programmed.The start address is a 2-byte field, MSB first. The length is a 1-byte field.

After the MCU completes execution of the command, the ACK ($FC) character is sent back to the PC. Thewrite commands minimum and maximum execution times are not specified.

Figure 11. Write Command

I ($49)

VERSION

PC TO MCU COMMAND

MCU TO PC RESPONSE

START

MEM #1

END

MEM #1

RELOCATED

VECTOR TABLE

INTERRUPTVECTOR TABLE

ERASEBLOCK SIZE

WRITEBLOCK SIZE

ID0

CAPS.STRING

#

OF MEM...SDIDAND

E ($45)

ACK

PC TO MCU COMMAND

MCU TO PC RESPONSE

START

ADDRESS

COMMAND EXECUTION

W ($57)

ACK

PC TO MCU COMMAND

MCU TO PC RESPONSE

BINARY DATALENGTHSTART

ADDRESS

COMMAND EXECUTION


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FC Protocol, Version 1, M68HC908 Implementation


2.4.6 Read Command

The read command (coded as R, $52) has address and data fields. The address contains the first addressto be programmed; the single byte is the length of data to be read. The start address is a 2-byte field, MSBfirst. The length is a 1-byte field.

The MCU sends this number of read bytes back to the PC.

Figure 12. Read Command

2.4.7 Quit Command

The quit command (coded as Q, $51) has no address or data fields. Execution of bootloader code is

finished immediately, and the user code is started. No ACK ($FC) character is sent back to the PC.

Figure 13. Quit Command

2.4.8 Boot loader User Table

The bootloader user table is a reprogrammable memory area intended for storage of bootloader-specificdata. This memory area is unavailable for the user program. For this tables memory allocation refer to FCProtocol, Version 1, M68HC908 Implementation.

3 FC Protocol, Version 1, M68HC908 ImplementationThis section describes features specific to the M68HC908 bootloader implementation. The memoryallocation is heavily MCU specific, so the meaning of all variables is explained in this section in detail.

Figure 2shows the typical memory allocation for M68HC908 MCUs with the bootloaderpre-programmed. For example, the MC68HC908KX8 MCU memory map includes:

7680 bytes of FLASH memory ($E000$FDFF)

R ($52)

PC TO MCU COMMAND

MCU TO PC RESPONSEBINARY DATA

LENGTHSTART

ADDRESS

Q ($51)

PC TO MCU COMMAND

MCU TO PC RESPONSE


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192 bytes of random-access memory (RAM) ($0040$00FF)

36 bytes of user-defined vectors ($FFDC$FFFF)

Figure 14. Simplified Example of Memory Allocation in MC68HC908KX8

3.1 Memory Allocation

The bootloader code occupies the top end of FLASH memory (the highest memory address space). Thisplacement allows an effective use of the FLASH block-protection technique (see the specific MCU datasheet for details).

3.2 FLASH Block Protection Register (FLBPR)

By setting a FLBPR (FLASH block-protection register), all address space above this address is protectedfrom intentional and unintentional erasing/re-writing. After both bootloader and FLBPR register areprogrammed into memory, the bootloader code is protected from unintentional modification by user code.

NOTE

Some M68HC908 MCUs have an FLBPR register in RAM instead ofFLASH (e.g., the MC68HC908JK/JL Families). The bootloader code setsthis register properly but the user code can eventually modify FLBPR anderase/write the bootloader code. See FLBPR Not Usable (in Some

M68HC08 Family MCUs).

INTERRUPT VECTOR TABLE

UNIMPLEMENTED AREA

BOOTLOADER CODE

BOOTLOADER USER TABLE

FREE MEMORY AREA

FOR USER CODE

UNIMPLEMENTED AREA

RAM

I/O REGISTERS

0xFFDC

0xFFFF

0xFE00

0xFCC0

0xFC80

0xE000

0x0100

0x0040

0x0000

FLASH MEMORY AVAILABLE

FOR USER CODE


ON MC68HC908KX8 MCU

THIS AREA OF FLASH IS PROTECTED

USING FLBPR REGISTER


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For example, the MC68HC908KX8 bootloader to the PC memory allocation is:

$01 Version 1, read command not implemented (bit 7)

$E000 Start address of reprogrammable memory area

$FC80 End address of reprogrammable memory area + 1

$FC80 Address of Bootloader User Table

$FFDC Start address of MCU interrupt vector table

$0040 Length of MCU erase block

$0020 Length of MCU write block

0,0,0,0,0,0,0,0 Bootloader data. No strictly defined syntax; different M68HC08

implementations provide different values (e.g., the sixth value in the MC68HC908KX8implementation is the value of the internal clock generator [ICG] trim register after calibration).All these bootloader data are then programmed back into the bootloader user table and can beretrieved during all subsequent starts (e.g., to trim the MCUs ICG to the best-known value beforeuser code start).

KX8-IR,0 Identification string, zero terminated. Information to be displayed on PC screen.

3.3 Interrupt Vector Table Relocation

Because the FLASH block-protection technique also protects the interrupt vector table from beingoverwritten, some method must be used to relocate these vectors to the different locations. To do this, thebootloader user table is used. It is a part of memory notprotected by the FLBPR, but it is unavailable tothe user program. All standard interrupt vectors are pointing to this table where JMP instructions areexpected to be stored for each interrupt. The only exception is the reset vector that points to the bootloadercode start.When an interrupt occurs, the vector is fetched from protected memory and directs execution

to continue at the corresponding JMP instruction in the bootloader user table.

Figure 15shows interrupt vector table relocation for M68HC08 MCUs. Note that in a standard interruptvector table, each record is 2 bytes long (each vector is a 16-bit address). This is different from thebootloader user table, for which each record is 3 bytes long a JMP opcode ($CC) plus a 16-bit address.


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Figure 15. Interrupt Vector Table Relocation (M68HC08 MCUs)

3.3.1 S19 File

Because the bootloader operation must be transparent to the user S19 file, another piece of intelligence isbuilt into the PC master code (instead of the MCU slave). The relocation works like this:

If the data from an S19 record corresponds to an address in the interrupt vector table, the value is relocated

into the corresponding area in the bootloader user table, including a JMP instruction (opcode $CC). Forexample, if the user S19 file contains #3 interrupt vector $E123 at address $FFE8, such a vector is


BOOTLOADER USER TABLE

0xFFDC

0xFCC0

0xFC80

...

...

RESET VECTOR

INTERRUPT VECTOR 1

INTERRUPT VECTOR 2

INTERRUPT VECTOR 3

INTERRUPT VECTOR 16

INTERRUPT VECTOR 17

BOOTLOADER CODE

0xFD00

0xFE00

START

EXIT

BOOTLOADER DATA

0xFC88

0xFFDE

0xFFE0

0xFFE8

0xFFEA

0xFFEC

0xFFFE

0xFC8B

0xFC8E

0xFC81

0xFC84

0xFCB8

0xFCBB

JMP USER RESET VECTOR

JMP USER INT. VECT. 1





...

USER CODE

START (RESET)

INTERRUPT ROUTINE 1

INTERRUPT ROUTINE 2

INTERRUPT ROUTINE 16


...


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relocated into the sequence $CC, $E1, $23 (JMP $E123) programmed to the $FC81 address in thebootloader user table.

Using this method, the user S19 file does not need to be modified, but the lower address of the end of

FLASH memory must be considered. Also, this JMP instruction (3T) delays every interrupt, as explainedin Each Interrupt 3T Delayed.

3.4 User Code Start

The user code is started in an unusual way to provide a register setup similar to how it appears after MCUreset.

3.4.1 Software Reset

If the bootloader must quit and run user code, an illegal operation is intentionally executed (M68HC08

illegal opcode $32). This causes an illegal operation reset, and the MCU restarts. During bootloaderstartup, the system integration module (SIM) reset status register (SRSR) is tested. If a power-on-reset isnot detected, the user code is started instead of the bootloader code. This allows the transparent operationof all other resets (such as illegal address, etc.) with only a short additional delay caused by testing theSRSR register and executing associated jump instructions.

3.4.2 Hardware Reset

In some implementations, a pin reset (caused by external reset pin) is also included as a valid source ofreset for the bootloader to start. This allows remote in-circuit reprogramming in embedded applicationsable to drive the M68HC08 reset pin.

Another test has been added to the real bootloader application: if no reset source is detected (i.e., if theSRSR register is 0), the bootloader is selected by default. This may happen when an external pin causes

reset, but the reset pulse is shorter than specified. In that case, the minimum length of reset pulse that willcause reset is shorter than the length needed for the proper propagation of the external reset flag to the

SRSR register.

Because the SRSR register is one-time readable (it clears after read), no subsequent reads of this registerprovide a valid value. See M68HC08 System Limitationsfor details.

3.5 M68HC08 System Limitat ions

This section summarizes limitations that must be considered when using the bootloader with the userapplication.

3.5.1 Memory Occupied

One of the most important requirements is to use the smallest code possible. Typical M68HC908implementations are between 300 and 500 bytes, including the bootloader user table. If the targetM68HC08 MCU is capable of FLASH programming using internal ROM routines, the memoryconsumption is near the lower limit. Larger M68HC08 MCUs (which are not usually equipped with ROM


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code for FLASH programming) will require approximately 500 bytes of FLASH of the total 32 KB (as isthe case with the MC68HC908GP32).

The bootloader is placed at the upper end of FLASH memory; therefore, the only modification required in

the user code is in the memory mapping (typically found in the linker parameter file).

The M68HC08 MCU signals the actual available FLASH addresses. The PC Bootloader software will not

allow programming if the user code overlaps with bootloader code.

3.5.2 Time Delay Upon Start-Up and Initial Communication

The number of pins with specific meanings during bootloader start-up must be as small as possible.Especially in communication systems (e.g., those using a standard serial port), pin overhead is zero and acertain level character at a certain timemethod is used. So, the bootloader waits a certain amount oftime to receive an answer from the PC at startup. If none is received, the user code starts. The typical delayis in the range of several hundred milliseconds.

If this start-up delay becomes an issue for the final application, the user may modify the bootloader code

and use a certain level on a certain pinmethod instead. A simple test of the voltage level on the IRQ pin(or any other input pin) can be used to indicate whether the bootloading sequence is required.

3.5.3 Each Interrupt 3T Delayed

Every interrupt call is delayed by 3T bus clocks required to execute the JMP instruction stored in thebootloader user table. This interrupt vector relocation (as described in Interrupt Vector Table Relocation)has been chosen as the best solution for achieving user code transparency and security of the bootloader

code.

The interrupt latency is about 10 to 15T (assuming that no interrupt is being executed), so this additionaldelay is not significant for the most applications.

3.5.4 FLBPR Not Usable (in Some M68HC08 Family MCUs)

The bootloader uses a FLASH block protection technique to protect itself from being overwritten (whereapplicable; see FLASH Block Protection Register (FLBPR)for details).

Some M68HC08 MCUs (such as the KX, GP, and GR devices) have this FLASH block-protection registerstored in FLASH, so it cannot be modified in user mode. The FLBPR can be erased or programmed onlywith an external voltage, VTST, present on the IRQ pin (normal monitor mode). Because this feature iscompletely dedicated to bootloader code protection, it is unavailable to the user application code. If thevalue for FLPBR appears in the user S19 code, a warning is displayed. Such an occurrence should be

omitted from user S19 code.Some families have the FLASH block protection register stored in RAM instead (the MC68HC908JK/JLFamilies are like this). The bootloader sets the correct value at the beginning of its execution to protectitself. However, user code can modify this register and protect its own memory areas as needed. This alsoimplies that the bootloader is not 100% protected from user code.

See the specific MCU data sheet for a detailed explanation.


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FC Protocol, Version 2, HC9S08 Implementation


3.5.5 SRSR Register Unusable

The bootloader uses an SRSR register (as described in User Code Start) to recognize the reset source todetermine whether the user code will run. Because the SRSR register is one-time readable (i.e., it is resetafter first read), the user code does not have access to the SRSR value (if the bootloader is present in thememory and makes the first read after each reset). There is no simple remedy for this situation. After the

SRSR register is read by the bootloader, it is stored in one RAM location. Unfortunately, its memorylocation may differ from one implementation to another. If the application requires the SRSR register andbootloader, the user must redirect the SRSR reading to this specific RAM location. This location can beobtained from the bootloaders MAP file.

4 FC Protocol, Version 2, HC9S08 Implementation

This section describes features that are specific to the HC9S08 bootloader implementation. The memoryallocation is heavily MCU specific so the meaning of variables is explained in this section.

Figure 16shows the memory allocation typical to the HC9S08 devices with the bootloaderpre-programmed. For example, the MC9S08GB/GT60 device memory map includes:

60 Kbytes of FLASH memory ($1080$17FF, $182C$FFAF)

4 Kbytes of random-access memory (RAM) ($0080$107F)

16 bytes of nonvolatile registers ($FFB0$FFBF)

64 bytes of user-defined vectors ($FFC0$FFFF)

Figure 16. Simplif ied Example of Memory Allocation in MC9S08GB/GT60


NONVOLATILE REGISTERS

BOOTLOADER CODE

FLASH 58772 BYTES

HIGH PAGE REGISTERS

FLASH 1920 BYTES

RAM

I/O REGISTERS

0xFFC0

0xFFFF

0xFFB0

0xFE00

0x182C

0x1800

0x1080

0x0080

0x0000


FOR USER CODE


ON MC9S08GB/GT60 MCU

THIS AREA OF FLASH IS PROTECTED

RELOCATED VECTOR TABLE0xFDC0


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4.1 Memory Allocation

The bootloader code occupies the top end of FLASH memory (the highest memory address space). Thisplacement allows an effective use of the FLASH protection technique (see specific MCU data sheet for

details).

4.2 FLASH ProtectionBy setting a FLASH protection register, all address space above this address is protected from bothintentional and unintentional erasing/re-writing. After the bootloader and the FLASH protection registerare programmed into memory, the bootloader code is protected from unintentional modification by usercode.

NOTE

See FLASH Protection Technique Not Usablefor limitations.

4.3 Example Memory Al locat ion

For example, the MC9S08GB/GT60 bootloader to the PC memory allocation is:

$82 Version 2, read command implemented (bit 7)

$r002 System device identification register (SDIDR) content ($002 for GB/GT Family, r (fourtop bits) is chip revision number reflecting current silicon level

$02 Number of reprogrammable memory areas

$1080 Start address of reprogrammable memory area #1

$1800 End address of reprogrammable memory area #1 + 1

$182C Start address of reprogrammable memory area #2

$FDC0 End address of reprogrammable memory area #2 + 1

$FDC0 Address of relocated interrupt vector table

$FFC0 Start address of MCU interrupt vector table

$0200 Length of MCU erase block

$0040 Length of MCU write block

GB/GT60,0 Identification string, zero terminated. Information to be displayed on PC screen

4.4 Interrupt Vector Table Relocation

If FLASH protection is enabled, the reset and interrupt vectors would be protected. Vector redirection

(HCS08 hardware feature) allows the user to modify memory allocation of interrupt vector information.

Vector redirection is enabled by programming the NVOPT (nonvolatile option) register. For redirection tooccur, at least some portionbut not allof the FLASH memory must be block-protected by

programming the NVPROT (nonvolatile protection) register. All of the interrupt vectors (memorylocations $FFC0$FFFD) are redirected, but the reset vector ($FFFE:FFFF) is not.


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For example, if 512 bytes of FLASH are protected, the protected address region is from $FE00 through$FFFF. The interrupt vectors ($FFC0$FFFD) are redirected to the locations $FDC0$FDFD.

If an SPI interrupt is takenfor examplethe values in the locations $FDE0:FDE1 are used for the vector

instead of the values in the locations $FFE0:FFE1. This allows the user to reprogram the unprotectedportion of the FLASH with new program code, including new interrupt vector values while leaving the

protected area, which includes the unchanged default vector locations.

4.4.1 S19 File

Because bootloader operation must be transparent to the user S19 file, another piece of intelligence is built

into the PC master code (instead of the MCU slave). If the record in the interrupt vector table is detectedin the user S19 file, the vector is relocated into the corresponding area in the relocated interrupt vectortable. For example, if the user S19 file contains #2 interrupt vector at address $FFEA, such a vector isrelocated to the $FDEA address in the relocated interrupt vector table.

Using this method, the user S19 file does not need to be modified, but the lower address of the end ofFLASH memory must be considered.

Figure 17illustrates HC9S08 interrupt vector table relocation.


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Figure 17. Interrupt Vector Table Relocation Explanation (HCS08)

4.5 User Code Start

To provide a register setup similar to how it appears after MCU reset, the user code is started in an unusual

way.

4.5.1 Software Reset

If the bootloader must quit and run user code, an illegal operation is intentionally executed (HCS08 illegalopcode $8D). This causes an illegal operation reset and the MCU restarts. During bootloader startup, the

system reset status register (SRS) is tested. If a power-on-reset is not detected, the user code starts instead


0XFFC0

RESET VECTOR (bootloader start) BOOTLOADER CODE

0XFD00

0XFFB0

START

EXIT

original interrupt vector table

0XFFFE

USER CODE

START (RESET)

INTERRUPT ROUTINE 1

INTERRUPT ROUTINE 2



...

RELOCATED INTERRUPT VECTOR TABLE

0XFDC0

...

RESET VECTOR

INTERRUPT VECTOR 1

INTERRUPT VECTOR 2

INTERRUPT VECTOR 3

INTERRUPT VECTOR 30

INTERRUPT VECTOR 31

0XFDC2

0XFDC4

0XFDE8

0XFDEA

0XFDEC

0XFDFE

is empty (unused)

its content is relocated


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of the bootloader code. This allows the transparent operation of all other resets (such as illegal address,etc.) with only a short additional delay caused by testing of the SRSR register and executing associatedjump instructions.

4.5.2 Hardware Reset

In some implementations, a pin reset (caused by external reset pin) is a valid source of reset for thebootloader to start. This allows remote in-circuit reprogramming in embedded applications that are able todrive the HCS08 MCU reset pin.

4.6 HCS08 System Limitations

This section summarizes limitations that must be considered when using the bootloader with the userapplication.

4.6.1 Memory Occupied

One of the strongest requirements is to use the smallest code possible. Typical HC9S08 implementationsare 432 bytes (minimal memory size that can be protected) plus another 64 bytes page for relocated

interrupt vector table.

The bootloader is placed at the upper end of FLASH memory, therefore, the only modification required inthe user code is in the memory mapping (typically found in the linker parameter file).

The HCS08 MCU signals the actual FLASH addresses available. The PC Bootloader software will warn

before programming if the user code overlaps with bootloader code.

4.6.2 Time Delay Upon Start-Up and Initial Communication

The number of pins with specific meaning during bootloader start-up must be as small as possible.Especially in communication systems (e.g., those using a standard serial port), pin overhead is zero and acertain character at a certain time method is used. So, the bootloader waits a certain amount of time toreceive an answer from the PC at startup. If none is received, the user code starts. The typical delay is therange of several hundred milliseconds.

If this start-up delay becomes an issue for the final application, the user may modify the bootloader codeand use a certain level on certain pin method instead. A simple test of the voltage level on the IRQ pin(or any other input pin) can be used to decide whether the bootloading sequence is required.

4.6.3 FLASH Protection Technique Not Usable

The bootloader uses a FLASH block protection technique to protect itself from being overwritten,therefore, this feature is not available for the user code. This includes FLASH memory security-relatedregisters (namely NVPROT, NVOPT, and NVBACKKEY) used for protection and interrupt-vectorrelocation by bootloader.


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FC Protocol, Version 3, Large M68HC08 Implementation



5 FC Protocol, Version 3, Large M68HC08Implementation

This section describes features specific to the protocol version 3 of bootloader. It is intended for largeHC08s (with two or more FLASH memory banks or, more precisely, with two or more separated FLASH

memory areas). The format of the Ident Commandfrom version 2 is used; the rest remains the same aswith protocol version 1 (HC08) namely the Interrupt Vector Table Relocation.

6 MCU Slave Software

This section provides a detailed description of the three typical M68HC(S)08 bootloader implementations.All code is written in assembly language. Several selected targets and different features are described as

shown in Table 2.

.

Table 2. Target Implementation Comparison

MCU Family

FLASH

MemoryUs

e

(inBytes)

Clock SourceROM

Routines

Usage

Calibration

Conducted

SCI

FLASHErase

Page Size(in Bytes)

FLASHProgram

Page Size(in Bytes)

MC68HC908APAP8/AP16/AP32/AP64

59232768 Hz XTAL

or external clock.

Yes,differentversion

No Hardware 512 64

MC68HC908AB/AS/AZAB32/AS32/AZ32AS60/AZ60

640 4.9152MHz XTAL No No Hardware 128 64

MC68HC908EY

EY16

384 ICG Yes Yes Hardware 64 32

MC68HC908GPGP32

51232768 Hz XTAL

or external clock.No No Hardware 128 64

MC68HC908GRGR4/GR8/GR16GR8A/GR16A

320

32768 Hz XTALor external clock;

8MHz XTAL(A Family)

Yes No Hardware 64 32

MC68HC908GTGT8/GT16


MC68HC908GZGZ8/GZ16

512 8 MHz XTAL Yes No Hardware 64 32

MC68HC908GZGZ60 512 8 MHz XTAL No No Hardware 128 64

MC68HC908JK/JLJK1/JL1/JK3/JL3

395XTAL, RC

oscillator or ext.source

Yes YesSoftware,

single-wirepossible

64 32

MC68HC908JK/JLJK8/JL8

384 4.9152MHz XTALYes,

differentversion

No Hardware 64 32


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6.1 MC68HC908KX

The M68HC908KX Family has an internal clock generator (ICG) module. This allows a very effective

implementation of the bootloader without a crystal.

MC68HC908JWJW32

1968 4MHz or 6MHzXTAL or resonator

Yes N/A USB2.0 512 64

MC68HC908LBLB8

384 ICG Yes YesSoftware,

single-wirepossible

64 32

MC68HC908LJLJ12/LJ/LK24

32432768 Hz XTAL

or external clock.

Yes,differentversion

No Hardware 128 64

MC68HC908KXKX2/KX8


MC68HC908MRMR8

461PLL with XTAL

(4 MHz)No No Hardware 64 32

MC68HC908MRMR16/MR32

461PLL with XTAL

(4 MHz)No No Hardware 128 64

MC68HC908QBQB4/QB8

362/302 QB/QC ICG Yes Yes/No Hardware 64 32

MC68HC908QCQC8/QC16

387/323 QB/QC ICG Yes Yes/No Hardware 64 32

MC68HC908QT/QYQT1/QT4/QY1/QY4

320 Simpler ICG Yes YesSoftware,

single-wirepossible

64 32

MC68HC908SRSR12

512 32768 Hz XTAL No No Hardware 128 64

MC9S08AWHCS08AW32/48/64

576 HCS08 ICG No Yes Hardware 512 64

MC9S08GB/GTHCS08GB/GT32HCS08GB/GT60

576 HCS08 ICG No Yes Hardware 512 64

MC9S08QGHCS08QG4/8

576 HCS08 ICG NoNo (HW)Yes (SW)

HardwareSoftware

512 64

MC9S08RxHCS08RD/RG/RE8HCS08RD/RG/RE16HCS08RD/RG/RE32HCS08RD/RG/RE60

335 16MHz XTAL No No Hardware 512 64

Table 2. Target Implementation Comparison (continued)

MCU Family

FLASH

MemoryUse

(inBytes)

Clock SourceROM

Routines

Usage

Calibration

Conducted

SCI

FLASHErase

Page Size(in Bytes)

FLASHProgram

Page Size(in Bytes)


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MCU Slave Software



The on-chip FLASH programming routines simplify the bootloader and improve memory use. Thecommunication between the MCU and PC uses a standard serial channel (SCI).

Figure 18. MC68HC908KX Bootl oader Flowchart

RESET

SRSR RESETSOURCE TEST

MCU CONFIGICG, SCI INIT

WAIT FOR COMMAND

SEND IDENT DATA RECEIVE ADDRESS RECEIVE ADDRESS

RECEIVE LENGTH

RECEIVE DATA

CALL WRITEROUTINE IN ROM

CALL ERASEROUTINE IN ROM

RECEIVE ADDRESS

RECEIVE LENGTH

SEND DATA

SEND ACK

EXECUTE ILLEGAL

OPERATIONSEND ACK AND

WAIT FOR ANSWER

YES

YES

USER CODE

START

POR CAUSED RESET

DISABLE SCI

MEASURE BREAK

WAIT FOR HI-LO EDGE

TRIM ICG, ENABLE SCI

IDENT? ERASE? WRITE? READ? QUIT?

YES YES YES

YESNO NO NO NO

NO

1

2

2

1

2

2

2

TIMEOUT EXPIRED

NO

NOT POR

?


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MCU Slave Software


6.1.1 Internal Clock Generator (ICG) Initialization

The ICG is simple to initialize. Because the ICG is active and the clock monitor is disabled after reset, theonly action required is the modification of the ICG multiply register. Then, the ICGS flag (bit 2) of theICG control register indicates whether the ICG is stable after the frequency change.

ICGMRINIT EQU $20

MOV #ICGMRINIT,ICGMR ; set 9.8304MHz BUS clockLOOP: BRCLR 2,ICGCR,LOOP ; wait until ICG stable

6.1.2 Internal Clock Generator Trimming

Even though the trimming routine is in ROM, a small bug renders this code unusable; therefore, the sourcecode has been taken and inserted in the bootloader code.

Although AN1831/D provides the procedure for calculating the trim factor from the measured CPU speed,the code itself omits the final doubling of the number of cycles.

* FOLLOWING LOOP IS EXECUTED UNTIL THE END OF THE BREAK SIGNAL. THE BREAK* SIGNAL LASTS 10 BIT TIMES. IF COMMUNICATING AT f OP /256 BPS, THEN 10 BIT* TIMES IS 2560 CYCLES. EACH TIME THROUGH THE LOOP IS 10 CYCLES, SO WE* EXPECT TO EXECUTE THE LOOP 256 TIMES IF THE KX8 IS IN SYNC SERIALLY WITH* THE HOST. IF WE STAY IN THE LOOP FOR > 256 LOOP CYCLES, THEN THE KX8* MUST BE RUNNING FASTER THAN EXPECTED, AND NEEDS TO BE SLOWED DOWN. IF WE* STAY IN THE LOOP FOR < 256 LOOP CYCLES THEN THE KX8 MUST BE RUNNING SLOWER* THAN EXPECTED AND NEEDS TO BE SPEEDED UP. THE AMOUNT THAT WE CHANGE THE* CPU SPEED IS EQUAL TO THE NUMBER OF LOOP CYCLES OVER OR UNDER 256. SO IF* WE GO THROUGH THE LOOP 240 TIMES, THEN WE ARE RUNNING* (256-240)/256 = 6.25% FAST. EACH INCREMENTAL CHANGE WE MAKE TO THE TRIM REGISTER* (ICGTR) WILL MAKE A 0.195% CHANGE TO THE INTERNAL CLOCK. THAT IS, INCREMENTING* THE REGISTER BY ONE OVER THE DEFAULT VALUE OF $80 STORED THERE WILL* DECREASE THE INTERNAL CLOCK BY 0.195%, AND VICE VERSA.

* NOW EACH EXECUTION OF THE LOOP OVER OR UNDER WHAT IS EXPECTED (256 TIMES)* REPRESENTS AN ERROR OF 1/256 = .391% ERROR. SO WE'LL NEED TO DOUBLE THE* NUMBER OF LOOP CYCLESAND USE THIS NUMBER TO CORRECT THE TRIM REGISTER.* OUR PRECISION FOR TRIMMING IS THEREFORE 0.391%.

The actual code adds anASLAinstruction which doubles the trim factor before the actual write to the ICGtrim register.

ICGTRIM: CLRX CLRH

MONPTB4: BRSET 4,PTB,MONPTB4 ;WAIT FOR BREAK SIGNAL TO START

CHKPTB4: BRSET 4,PTB,BRKDONE ;(5) GET OUT OF LOOP IF BREAK IS OVER AIX #1 ;(2) INCREMENT THE COUNTER BRA CHKPTB4 ;(3) GO BACK AND CHECK SIGNAL AGAINBRKDONE: PSHH PULA ;PUT HIGH BYTE IN ACC AND WORK WITH A:X TSTA ;IF MSB OF LOOP CYCLES = 0, THEN BREAK TAKES TOO


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MCU Slave Software



TXA ;FEW CYCLES THAN EXPECTED, SO TRIM BY SPEEDING BEQ SLOW ;UP f OP .FAST: CMP #$40 ;SEE IF BREAK IS WITHIN TOLERANCE BGE OOR ;DON'T TRIM IF OUT OF RANGE ASLA ;multiply by two to get right range ADD #$80 ;BREAK LONGER THAN EXPECTED, SO SLOW DOWN f OP BRA ICGDONESLOW: CMP #$C0 ;SEE IF BREAK IS WITHIN TOLERANCE BLT OOR ;DON'T TRIM IF OUT OF RANGE ASLA ;multiply by two to get right range SUB #$80ICGDONE: STA ICGTROOR: RTS

The complete explanation of the trimming procedure can be found in AN1831/D. See References.

6.2 MC68HC908JK/JL

MC68HC908JK/JL MCUs are among the least expensive in the M68HC08 Family, and they have nohardware SCI. Therefore, a software SCI must be implemented. This allows the unrestricted selection of

which pins are used for serial communication (the provisions are made in the code so an IRQ pin can alsobe used as an input serial line).

The MC68HC908JK/JL Family has a RC version (an RC oscillator is used instead of a crystal). Thebootloaders calibration compensates for any speed variation. If the desired clock frequency is outside thespecified range covered by the calibration system, the code must be modified.

The MC68HC908JK/JL Family has on-chip FLASH programming routines. Using FLASH programmingsaves memory.

The main program flowchart (Figure 19) is very similar to the previous case.


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MCU Slave Software


Figure 19. MC68HC908JK/JL Bootloader

RESET


MCU CONFIG...

WAIT FOR COMMAND


RECEIVE LENGTH

RECEIVE DATA

CALL WRITE

ROUTINE IN ROM

CALL ERASE

ROUTINE IN ROM

RECEIVE ADDRESS

RECEIVE LENGTH

SEND DATA

SEND ACK

EXECUTE ILLEGAL

OPERATIONSEND ACK ANDWAIT FOR ANSWER

YES

YES

USER CODE

START

POR CAUSED RESET

...

MEASURE BREAK

WAIT FOR HI-LO EDGE

CALIBRATE SOFT-SCI


YES YES YES

YESNO NO NO NO

NO

1

2

1

1

2

2

2

TIMEOUT EXPIRED

NO

NOT POR

?


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MCU Slave Software



6.2.1 Software-SCI Transmit Char Routine

A detailed description of the software-SCI transmit and receive subroutines is provided in this section.They both are based on a 16-bit timer and the output-compare event is polled in the background loop.

Figure 20. Soft-SCI Transmit Char Routine

The two routines souce code is shown in Figure 21. Other than a few counters, a 16-bit ONEBITvariableis used. It contains the actual length of 1 bit at the current communication speed in 16-bit timer clockcycles. This variable is initialized during the calibration phase (Slave Frequency Calibration).

ENTER

TEST CARRYINITIALIZE, FEED AND

RUN 16-BIT TIMER

WAIT FOR

TXD PIN LOW

SET BIT COUNTERTO 9

TIMER FLAG

SHIFT-OUT TRANSMITCHAR INTO CARRY FLAG

TXD PIN LOW

TXD PIN HIGH

CLEAR TIMER FLAG

DECREMENTBITS AND TEST

TXD PIN HIGH

CLEAR TIMER FLAG

SET

CLEAR

STOP TIMER

EXIT= 0

0

TIMER FLAGRECEIVED?

WAIT FOR

TIMER FLAG

TIMER FLAGRECEIVED?

NO

YES

NO

YES


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MCU Slave Software


;*******************************************************************************************SCITX: PSHH PSHX

BCLR 7,TSC ; and clear TOF LDHX ONEBIT

STHX TMOD BSET 4,TSC ; clear timer BCLR 5,TSC ; run timer

TXDCLR

MOV #9,BITS ; number of bits + 1 BRA SCITX1 ; jump to loop

SCITX2: LSRA ; shift out lowest bit BCC DATALOW

TXDSET

SKIP2 ; skip next two bytesDATALOW: TXDCLR

BCLR 7,TSC ; and clear TOFSCITX1: BRCLR 7,TSC,SCITX1 ; wait for TOF

DBNZ BITS,SCITX2 ; and loop for next bit

SCISTOP: TXDSET

BCLR 7,TSC ; and clear TOFSCITX3: BRCLR 7,TSC,SCITX3 ; wait for TOF

EPILOG: BSET 5,TSC ; stop timer

PULX PULH RTS

Figure 21. Software-SCI Transmit Char Routine Source Code

6.2.2 Software-SCI Receive Char Routine

The software-SCI receive routine is similar to software-SCI transmit. When the 16-bit output-compareevent is polled, the value of the receive pin is scanned. No provisions are made for stop-bit checking,

framing check, noise detection, etc., mainly because of memory restrictions. Figure 22shows thesoftware-SCI receive routine flowchart, and the source code is provided in Figure 23.


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MCU Slave Software



Figure 22. Software-SCI Receive Char Routine

ENTER

RXD PIN IS

INITIALIZE AND FEED

16-BIT TIMER

SET BIT COUNTERTO 9

SHIFT-IN RECEIVECHAR AND CLEAR MSB

SET MSB

DECREMENTBITS AND TEST?

SET

CLEAR

STOP TIMER

EXIT

WITH 1.5 BIT TIME

RUN TIMER

FEED 16-BIT TIMERWITH 1 BIT TIME

WAIT FOR

TIMER FLAG

TIMER FLAGRECEIVED?

NO

YES

WAIT FOR

RXD LOW

RXD LOW?

NO

YES

SET OR CLEAR?

CLEAR TIMER FLAG

= 0

0


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MCU Slave Software


;*******************************************************************************************SCIRX: BRRXDLO SCIRX ; loop until RXD high (idle)

SCIRXNOEDGE: PSHH PSHX

BCLR 7,TSC ; and clear TOF

LDX ONEBIT LDA ONEBIT+1 LSRX RORA STX TMODH STA TMODL

BSET 4,TSC ; clear timer

SCIRX1: BRRXDHI SCIRX1 ; loop until RXD low (wait for start bit)

BCLR 5,TSC ; run timer MOV #9,BITS ; number of bits + 1

SCIRX2: BRCLR 7,TSC,SCIRX2 ; wait for TOF

LSRA ; shift data right (highest bit cleared) BRRXDLO RXDLOW ; skip if RXD low ORA #$80 ; set highest bit if RXD high

RXDLOW: LDHX ONEBIT STHX TMOD

BCLR 7,TSC ; and clear TOF DBNZ BITS,SCIRX2 ; and loop for next bit

BRA EPILOG

Figure 23. Software-SCI Receive Char Routine Source Code

6.2.3 Macros

Several macros are defined across the two code listings. They improve the readability or memoryconsumption (Figure 24).


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MCU Slave Software



SKIP1 MACRO DC.B $21 ; BRANCH NEVER (saves memory) ENDM

SKIP2 MACRO DC.B $65 ; CPHX (saves memory) ENDM

BRRXDLO MACRO

IFNE RXDISIRQ IFNE SCIRXINV

BIH \1 ; branch if RXD low ELSE

BIL \1 ; branch if RXD low ENDIF ELSE ; RXD uses normal I/O pin IFNE SCIRXINV

BRSET RXDPIN,RXDPORT,\1 ; branch if RXD low ELSE

BRCLR RXDPIN,RXDPORT,\1 ; branch if RXD low ENDIF ENDIF

ENDM

BRRXDHI MACRO

IFNE RXDISIRQ IFNE SCIRXINV

BIL \1 ; branch if RXD hiELSEBIH \1 ; branch if RXD hi

ENDIF ELSE ; RXD uses normal I/O pin IFNE SCIRXINV

BRCLR RXDPIN,RXDPORT,\1 ; branch if RXD hi ELSE

BRSET RXDPIN,RXDPORT,\1 ; branch if RXD hi ENDIF ENDIF

ENDM

TXDCLR MACRO

IFNE SCITXINV BSET TXDPIN,TXDPORT ; clr bit ELSE BCLR TXDPIN,TXDPORT ; clr bit ENDIF

ENDM

TXDSET MACRO

IFNE SCITXINV BCLR TXDPIN,TXDPORT ; set bit

ELSE BSET TXDPIN,TXDPORT ; set bit ENDIF

ENDM

Figure 24. Software-SCI Macros Source Code


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MCU Slave Software


6.3 MC68HC908GP

MC68HC908GP MCUs have no on-chip FLASH programming routines available. Therefore, all FLASHprogramming must be done by the bootloader, as demonstrated in this section.

MC68HC908GP MCUs are primarily targeted for use with a low-cost 32.768 kHz crystal. Because the

frequency of the crystal is known, no calibration is performed, which saves MCU memory. Therefore, thisMCU uses the Known MCU Communication Speedmethod.

Figure 25is a flowchart of the MC68HC908GP bootloader process.


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MCU Slave Software



Figure 25. MC68HC908GP Bootloader Flowchart

6.3.1 FLASH Programming Rout ines

The main code is similar to the previous implementation with the calibration phase omitted. The FLASH

programming by the bootloader is shown in Figure 26. Three main subroutines are defined:

CPY_PRG copies the selected routine into RAM

RESET


MCU CONFIGICG, SCI INIT

WAIT FOR COMMAND


RECEIVE LENGTH

RECEIVE DATA

CALL WRITE

ROUTINE IN ROM

CALL ERASEROUTINE IN ROM

RECEIVE ADDRESS

RECEIVE LENGTH

SEND DATA

SEND ACK

EXECUTE ILLEGAL

OPERATIONSEND ACK AND

WAIT FOR ANSWER

YES

YES

USER CODE

START

POR CAUSED RESET


YES YES YES

YESNO NO NO NO

NO

1

2

1

2

2

2

ACK RECEIVED

NO

NOT POR

BEFORE TIMEOUT

COPY WRITEROUTINE TO RAM

COPY ERASEROUTINE TO RAM


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MCU Slave Software


ERASE_ALG whole FLASH erase routine

WR_ALG whole WRITE erase routine

Because the flow is straightforward, no flowchart is provided. Basically, the sequence of events is executed

according to FLASH erasing/programming specifications.

;*******************************************************************************************

CPY_PRG: TSX ; STHX STACK ; copy stack for later re-call

LDHX SOURCE ; LOAD WRITE ALGORITHM TO RAMTXSLDHX #PRG

CPY_PRG_L1:PULASTA XAIX #1DBNZ STAT,CPY_PRG_L1

LDHX STACK

TXS ; restore stack RTS;*******************************************************************************************ERASE_ALG:

LDA #%00000010 STA FLCR ; ERASE bit on LDA FLBPR ; dummy read FLBPR

LDHX ADRS ; write anythingSTA X ; to desired range

D_US #T10US ; wait 10us

LDA #%00001010

STA FLCR ; set HVEN, keep ERASED_MS #T1MS ; wait 1ms

LDA #%00001000STA FLCR ; keep HVEN, ERASE offD_US #T5US ; wait 5us

CLRASTA FLCR ; HVEN offD_US #T1US ; wait 1us

JMP SUCC ; finish with ACKERASE_ALG_END:;*******************************************************************************************WR_ALG: LDA #%00000001 STA FLCR ; PGM bit on LDA FLBPR ; dummy read FLBPR

LDHX ADRS ; prepare addresses STA X ; and write to desired range D_US #T10US ; wait 10us


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MCU Slave Software



LDA #%00001001STA FLCR ; set HVEN, keep PGMD_US #T5US ; wait 5us

LDHX #DAT ; prepare addressesTXSLDHX ADRSMOV LEN,POM

WR_ALG_L1:PULASTA XAIX #1D_US #T30US ; wait 30usDBNZ POM,WR_ALG_L1 ; copy desired block of data

LDA #%00001000STA FLCR ; keep HVEN, PGM offD_US #T5US ; wait 5us

CLRA

STA FLCR ; HVEN offD_US #T1US ; wait 1us

JMP RETWR ; finish with ACK (& restore STACK before)WR_ALG_END:END

Figure 26. FLASH Programming Routines Source Code

For improved readability, two timing macros (D_USand D_MS) are used in the code (Figure 27).

;*******************************************************************************************D_MS: MACRO

LDA \1 ; [2] ||\@L2: CLRX ; [1] ||

\@L1: NOP ; [1] |DBNZX \@L1 ; [3] | 256*4 = 1024TDBNZA \@L2 ; [3] || (1024+4)*(arg-1) + 2 TENDM

D_US: MACROLDA \1 ; [2]

\@L1: NOP ; [1]DBNZA \@L1 ; [3] 4*(arg-1) + 2 TENDM

Figure 27. FLASH Programming Macros Source Code

6.4 MC68HC908GRMC68HC908GR MCUs are smaller members of the MC68HC908GP Family equipped with ROM

memory with on-chip FLASH programming routines available in the user mode.


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MCU Slave Software


MC68HC908GP and MC68HC908GR MCUs are primarily targeted for use with a low-cost 32.768 kHzcrystal. Because the frequency of the crystal is known, no calibration is performed, which saves MCUmemory. Therefore, these MCUs use the Known MCU Communication Speedmethod.

6.5 MC68HC908MR

MC68HC908MR MCUs are motor-control oriented members of the M68HC08 Family. TheMC68HC908MR MCUs have no on-chip FLASH programming routines available. Therefore, all FLASH

programming must be done by the bootloader.

The MC68HC908MR Family has a PLL (phase-locked loop) circuit that can multiply the crystalfrequency. Typically, a 4-MHz XTAL is used as the reference frequency. This implementationdemonstrates how the PLL circuit is initialized for 8 times the crystal frequency. Therefore, the source PLL

frequency is 32 MHz, and the bus frequency is 8 MHz.

Because the frequency of the crystal is known, no calibration is performed, which saves MCU memory.Therefore, these MCUs use the Known MCU Communication Speedmethod.

6.6 MC68HC908GT

6.7 MC68HC908EY

The code for MC68HC908GT and MC68HC908EY MCUs is similar to MC68HC908KXcode, except forthe memory maps and ROM routine locations. One minor difference is that the MC68HC908GT Familycannot use the CGMXCLK clock as the SCI module source. Therefore, the bus clock is the only possibleclock source.

6.8 MC68HC908QT/QY

MC68HC908QT/QY MCUs are the smallest members of the M68HC08 Family. They have a simple ICGmodule (running on fixed frequency 12.8 MHz 25%). ROM routines are available.

There are several spare FLASH locations (mainly among unused interrupt vectors) also used for storingthe bootloader code.

6.8.1 SCI Application Program Interface (SCIAPI)

Software SCI communication is implemented on MC68HC908QT/QY, MC68HC908JK/JL and

MC68HC908LB MCUs to reduce cost and enable the user code to call the SCI send and receive routines(with certain limitations). The bootloader code now implements so-called SCIAPI, which is the defined

way to call the SCI send and receive routines.The details, implementation notes, and limitations are provided in the sci.hfile (of the QTQY folder).This file is the only resource that must be included in the user C code. The calling convention and overallusage is described in this file, too. The main limiting factor for most applications will be that the SCI

receive routine is a blocking one. This means that routines will not return until an SCI character is received.The 16-bit timer registers are also manipulated. Some applications will use this code without problems.


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MCU Slave Software



6.8.2 Single-Wire Communicat ion

Because of the small number of pins on MC68HC908QT devices, the single-wire SCI version has beendeveloped to keep the number of pins occupied by communication to a minimum. Figure 28illustrates anexample single-wire RS-232 interface. The single-wire option has been ported to MC68HC908JK/JL andMC68HC908LB bootloader because they use a software SCI also.

Figure 28. Example Single-Wire Schematic

The bootloaders master side must be informed that the single-wire communication is used. This can bedone by calling the hc08sprg.exe software. Use the following extended calling convention:

hc08sprg. exe 1: S f i l ename. s19

where 1 specifies which COM port is used for communication, and S stands for single-wire.

Original (old) format: hc08sprg.exe 1 filename.s19

Now defaults to: hc08sprg.exe 1:D filename.s19

where D stands for dual-wire mode. The bootloader master can also detect the presence of a single-wireinterface if called:

hc08sprg. exe 1: ? f i l ename. s19

The detection is only possible if the serial interface (mainly the level shifter) is powered up and workingBEFORE the bootloading process starts. Because this is not usually the case, always specify thebootloading mode by including either a :S or a :D in the parameter.

6.9 MC68HC908LJ

MC68HC908LJ MCUs are members of the M68HC08 Family used to drive LCD displays.MC68HC908LJ MCUs have the ROM on-chip FLASH programming routines available. The callingconvention is slightly different from other M68HC08s (see MC68HC908LJ data sheet, monitor ROM

section).

MC68HC908LJ MCUs are primarily targeted for use with a low-cost 32.768 kHz crystal. Because thefrequency of the crystal is known, no calibration is performed, which saves MCU memory. Therefore,these MCUs use the Known MCU Communication Speedmethod.

TTL/232 SHIFTER

VDD

RS-232CONNECTION

TXD

RXD

MC68HC908QT/QY

10k

MCU


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MCU Slave Software


6.10 MC68HC908AP

MC68HC908AP devices are members of the M68HC08 Family that have two SCIs (the SCI channel mustbe selected at compile time). MC68HC908AP MCUs have ROM on-chip FLASH programming routines

available. The calling convention is slightly different from other M68HC08s (same as MC68HC908LJdevices).

Because of the internal oscillator simplicity, it does not have the accuracy and stability of the RC oscillatoror the XTAL oscillator. Therefore, the internal oscillator is not suitable if an accurate bus clock is requiredand it should not be used as the bus clock source.

A low-cost 32.768 kHz crystal was selected as the default source clock for the bootloader and userapplication. Because the frequency of the crystal is known, no calibration is performed, which saves MCUmemory. Therefore, these MCUs use the Known MCU Communication Speedmethod.

6.11 MC68HC908AB/AS/AZ

MC68HC908AB/AS/AZ devices are members of the M68HC08 Family that also have EEPROM memory.

This code also demonstrates the way how to program these EEPROM cells using AUTO (automatic clearof EEPGM) mode.

Since the memory map is not continuous, FC protocol version 3 needs to be used (it allows the holes in

the memory map, i.e., several separate memory blocks).

6.12 MC9S08GB/GT

MC9S08GB/GT devices are the first members of the HCS08 Family. Because of different hardwarefeatures and FLASH memory allocation, another version of the protocol was required. Theprotocol is detected automatically by the latest hc08sprg.exePC Bootloader software andbecomes invisible to the user.

MC9S08GB/GT MCUs have two SCIs (the SCI channel must be selected at compile time).

These MCUs have no on-chip FLASH programming routines. Therefore, the bootloader must do allFLASH programming, and this implementation demonstrates this (it has been entirely adopted fromHCS08 Family Reference Manual Volume 1 (Freescale Semiconductor order number HCS08RMv1/D; seeReferences).

6.13 MC68HC908JW

HC908JW family has built-in USB 2.0 Full Speed module. It allows a direct connection via true USBinterface with PC. As described in AN3153: Using the Full-Speed USB Module on the MCHC908JW32

application note, the emulation of the serial COM port can be easily designed. This way a fully compatiblebootloader (written in C) for JW32 family has been designed. Once the bootloader is programmed into

JW32 device, the user code can be reprogrammed anytime using native USB connection (serial COM portemulation in Windows).

The installation and usage details are documented in ZSTARRM: Wireless Sensing Triple Axis Referencedesign, chapter 5.5 and 6.1.2, out of which the JW32 USB bootloader has been derived. The PC drivers


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PC Bootloader Master Software



required for USB are also inside JW32 folder of AN2295SW software package. Alternatively the lateston-line version of PC drivers is available on the ZSTAR summary page (RD3152MMA7260Q).

NOTE

Although serial COM emulation on JW32 has been successfully tested inLinux, Linux port of hc08sprg executable of AN2295 bootloader master

was not tested together with JW32 bootloader USB implementation.

7 PC Bootloader Master Software

This section provides a detailed description of the bootloader host computer master software, which isdownloadable as a zip file from the Freescale Semiconductor website, http://www.freescale.com. All codeis written in C language and is compatible with Linuxand Win32platforms.

The bootloader specifications dictate that, as much as possible, intelligence is executed in the hostcomputer instead of by the MCU, minimizing MCU memory consumption. Only primitive functions areimplemented in the MCU.

In this section, portions of the master bootloader code will be described in more detail. All actions requiredfor reprogramming the M68HC(S)08 device are fully described in the slave implementation and protocolsections of this document. The specific master characteristics are emphasized.

The host computer master software design is straightforward and is a sequence of several steps(Figure 29):

Opening serial port

Opening source S19 file

Waiting for reset of MCU

Calibrating MCU

Reading MCU information Remapping MCU interrupt vectors

Checking if source S19 data fits into physical MCU memory

Erasing and programming MCU

Cleaning up, exiting program
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RD3152MMA7260Qhttp://www.freescale.com/http://www.freescale.com/http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=RD3152MMA7260Q


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Figure 29. Bootloader Master Flowchart

7.1 File Structure

The following file structure is set up:

8-Bit MCU Image Operations:

s19.c

UART Manipulations:

serial.h

seriallinux.c (serialw32.c)

System Platform Dependent Files:

sysdep.h

sysdeplinux.h sysdepw32.h

Generic and Main Program Files:

hc08sprg.h

main.c

START

ENOUGH

INIT UART

OK?

SURE?

ARGUMENTS

OPEN S19 FILE

OK?

WAIT (HOOK) FOR

OK?

MCU RESET

CALIBRATE MCU

OK?

X(1) READ MCU INFO

OK?

PRINT MCU INFO

SET UP INTERRUPT

OK?

VECTOR TABLE

X(2)

X(0)

X(3)

X(4)

X(5)

X(6)

CHECK S19IMAGE TO FIT

X($FF)

PROGRAM MCU

OK? X(8)

UNHOOK MCUCLOSE UART

EXIT

NOTE: X(2) MEANS EXIT WITH EXIT CODE

DISPLAY WARNINGIF NOT

NO

NO

NO

NO

NO

NO

NO

NO

NO

YES

YES

YES

YES YES

YES

YES

YES

YES

?


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M68HC(S)08 Specific Programming Files:

prog.c

7.2 8-Bit MCU Image Operat ions

To perform the necessary operations with the code, the master software keeps a binary image of the

memory. Also, the information about whether an actual byte is to be programmed into the MCU is stored.This is done by following structure:

typedef struct {BYTE d[0x10000]; // dataBYTE f[0x10000]; // valid flag 0=empty; 1=usercode; 2=systemcode

} BOARD_MEM;

where imageis the actual variable defined as follows:

BOARD_MEM image;

After the source S19 files are read, this array contains the actual data to be programmed into the MCUirrespective of its original order in the S19 file. The function int read_s19(char *fn)defined in s19.cimplements the S19 file opening, reading, and relocation from S19 hexadecimal format into this binaryarray.

7.2.1 Interrupt Vector Table Relocation

After the ident information is read out of the MCU, the following operations within the image are carriedout:

The code is scanned to determine if any interrupt vectors are present between the MCU interruptvector table address and 0xFFFF (the last existing physical address of the M68HC(S)08 MCU).

If interrupt vectors are present, relocation of these vectors is done as described in Interrupt Vector

Table Relocation. Then, the original address spaces in the interrupt vector table are marked asunused, thus, not being reprogrammed.

These operations are executed in the function int setup_vect_tbl(void)defined in prog.cfile.

7.2.2 Checking Memory Boundar ies

The last check performed before the code is actually programmed into the MCU is to determine if the codefrom the S19 file is in the correct memory locations (between the memory boundaries reported by the

MCU in the ident table).

If any value outside the range of addresses between the start address of reprogrammable memory area and

the end address of reprogrammable memory area is found, a warning is generated.

This check is done in int check_image(void)also defined in the prog.cfile.


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7.3 UART Manipulations

In seriallinux.cor serialw32.c,depending on the platform used, the following UART manipulationfunctions are defined:

int init_uart(char* nm);int close_uart(void);

int send_break10(void);int flush_uart(int out, int in);intwb(const void* data, unsigned len);int rb(void* dest, unsigned len);

The pair int init_uart(char* nm)and int close_uart(void)manage opening (initialization) and

closing of the specified UART port.

The pair intwb(const void* data, unsigned len)and int rb(void* dest, unsigned len)isused for writing and reading blocks of data into/out of UART.

Two additional functions are required for the bootloader to work:, int send_break10(void)and

int flush_uart(int out, int in). The first sends a BREAK character to the UART, the second cleans

up both directions (in/out) of the UART buffers.

7.4 System Platform Dependent Files

The header filesysdep.hincludes either sysdeplinux.h or sysdepw32.h, depending on the platformsoftware being compiled. The platform-specific declarations are then used.

7.5 Generic and Main Program Fi les

The header file hc08sprg.hcontains the rest of the generic declarations needed to compile the application.The file main.ccontains the main program and is shown at the beginning of this section (Figure 29).

7.6 M68HC(S)08 Specific Programming Files

The most important part of the PC Bootloader software is contained in the file prog.cimplements mostof the intelligence of the PC bootloader software as mentioned in previous sections.

Numerous routines are implemented in the prog.cfile:

int hook_reset(void)int could_be_ack(unsigned b)int calibrate_speed(void)int read_mcu_info(void)int setup_vect_tbl(void)int check_image()int read_blk(unsigned adr, int len, BYTE *dest)int erase_blk(unsigned a)int prg_blk(unsigned a, int len)int prg_area(unsigned start, unsigned end)int prg_mem(void)int unhook(void)


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7.6.1 Initial Hook (Waiting for MCU Reset)

Immediately after all initializations are done in the PC, a loop starts to wait for communication from theMCU. The int hook_reset(void) routine implements all necessary steps to establish initialcommunication with the MCU.

7.6.2 Checking ACK

A routine int could_be_ack(unsigned b)checks if a received character fits the possible set ofcharacters that can be received due to a communication speed mismatch (See Unknown MCUCommunication Speed).

7.6.3 Speed Calibration

A speed calibration loop, implemented in the int calibrate_speed(void)routine, follows the scenario

described in Slave Frequency Calibration. If no ACK is received from the MCU, another break characteris sent.

7.6.4 MCU Info Reading

Immediately after the calibration is successfully completed, the PC requests the Ident Command, to whichthe MCU responds with information about itself. This is achieved in the int read_mcu_info(void)routine.

7.6.5 Image Manipulations

The two functions, int setup_vect_tbl(void) and int check_image(), are described in 8-Bit MCUImage Operations.

7.6.6 Block Operations

Three main data exchange operations are performed:

Erase block

Read block

Write (program) block

These basic operations are implemented in the functions:

i nt erase_blk( unsi gned a)int read_blk(unsigned adr, int len, BYTE *dest)

int prg_blk(unsigned a, int len)

The actual implementation is straightforward and follows the rules described in Interpreting MCUCommands.


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Bootloading Procedure Demonstration


7.6.7 Main Programming Loop

The core of the bootloaders programming capabilities is implemented in the function int

prg_area(unsigned start, unsigned end). This routines task is to read data from an image and splitthe data into appropriately sized blocks (minimum erase/write block sizes). Then the erase block and writeblock routines are called, in that order.

The routine also prints the progress information to the standard I/O (e.g., block boundary addresses,progress indicator).

One additional auxiliary function, int prg_mem(void), is included. It retrieves the lowest and highestmemory addresses that must be programmed because those addresses are used for calling the intprg_area(unsigned start, unsigned end) function.

7.6.8 Final Unhook

Function int unhook(void) sends out the Quit Command.

8 Bootloading Procedure DemonstrationThe bootloader binary code (S19 file) is loaded in the MCU like any other regular 8-bit MCU (usingMON08 serial programmer or other, for HCS08 using BDM interface). Then the MCU is soldered, orsocketed, in the application.

Using the bootloader pre-programmed into the MCU, the user can download the 8-bit MCU userapplication code via SCI interface using the bootloader utility.

8.1 Bootloading Operation

Open a command promptin the Linux or Windows directory where the copy of hc08sprgexecutableand S19 files are.

Assuming the serial board is connected to, for example, a second serial port (COM2, /dev/ttyS1) and is not

yet powered on, invoke the bootloader using following sequence: hc08sprg.exe 2:D test.s19


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Figure 30. Bootloader Invocation

The bootloader now expects the ACK command to be received from the MCU bootloader-enabledapplication. Then turn the power onfor serial board and if all connections are OK, the MCU beginscommunication with the PC. The calibration procedure does not occur (the bootloader version with knowncommunication speed is used), followed by IDENT command. The information that is acquired from theMCU is then displayed on the screen (Figure 31).


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Figure 31. First Stage of Bootloading

Confirm by pressing yand bootloading (FLASH reprogramming) will continue. The user application

will then start.


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Figure 32. Bootloading Completed

8.1.1 Memory Boundary Overlap Example

If the user tries to bootload an application that will not fit in the actual MCU memory, a warning isdisplayed. The user may decide to continue, but some memory locations would likely be programmedincorrectly (the user code is either out of available FLASH memory or it overlaps with the bootloader

code).


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References


Figure 33. Memory Boundary Overlap Example

9 References

For additional information, refer to these documents from the Freescale Semiconductor website,http://www.freescale.com

AN2295SW: Contains all of the software files for this application note in a zip file.

HCS08RMv1:HCS08 Family Reference Manual Volume 1 AN1831: Using MC68HC908 On-Chip FLASH Programming Routines

AN2140: Serial Monitor for MC9S08GB/GT

AN2498:Initial trimming of the MC68HC908 ICG

AN2504: On-Chip FLASH Programming API for CodeWarrior Software

AN2508: Generating Clocks for HC908 MCU Families

AN2545: On-Chip FLASH Programming Routines for MC68HC908GR/GZ

AN2637: Software SCI MC68HC908QT/QY MCU

AN2635: On-Chip FLASH Programming Routines for LB8 and other FLASH-based MCUs

AN2874: Using M68HC908 ROM-Resident Routines AN3153: Using the Full-Speed USB Module on the MCHC908JW32

ZSTARRM: Wireless Sensing Triple Axis Reference design
http://www.freescale.com/http://www.freescale.com/


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Europe, Middle East, and Africa:Freescale Halbleiter Deutschland GmbHTechnical Information CenterSchatzbogen 781829 Muenchen, Germany+44 1296 380 456 (English)+46 8 52200080 (English)+49 89 92103 559 (German)+33 1 69 35 48 48 (French)[email protected]

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