Interrupts Interrupts Resets Resets Low Power Modes Low Power Modes Drop everything and get your Drop everything and get your priorities straight! priorities straight! Alan Claghorn Chris Golder Raja Shah Outline Outline Interrupts Interrupts • Why use interrupts? Why use interrupts? • Types of interrupts Types of interrupts • Interrupt Flow Interrupt Flow • Priorities Priorities Resets Resets Low Power Modes Low Power Modes • Wait Wait • Stop Stop Real World Applications Real World Applications
Transcript
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InterruptsInterruptsResetsResets
Low Power ModesLow Power ModesDrop everything and get your Drop everything and get your
priorities straight!priorities straight!
Alan Claghorn
Chris Golder
Raja Shah
OutlineOutlineInterruptsInterrupts•• Why use interrupts?Why use interrupts?•• Types of interruptsTypes of interrupts•• Interrupt Flow Interrupt Flow •• PrioritiesPriorities
ResetsResetsLow Power ModesLow Power Modes•• WaitWait•• StopStop
Real World ApplicationsReal World Applications
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HistoryHistoryUnivac 1103/1103A (1953/1956) Univac 1103/1103A (1953/1956) --Typically cited as first CPU with interrupts. Typically cited as first CPU with interrupts. Current instruction stored in memory Current instruction stored in memory location and program counter loaded with location and program counter loaded with a fixed address.a fixed address.
But earlier examples include:But earlier examples include:UNIVAC (1951) UNIVAC (1951) –– first exception handlingfirst exception handlingIBM (1954) IBM (1954) –– first to use interrupt first to use interrupt maskingmaskingNBS DYSEAC (1954) NBS DYSEAC (1954) –– first with I/O first with I/O interruptsinterrupts
IntroductionIntroductionInterrupts Interrupts –– What are they good for?What are they good for?
To modify or do additional instructions based on To modify or do additional instructions based on internal requests and/or external devicesinternal requests and/or external devices
Provide a means for suspending current Provide a means for suspending current instructions for more important tasksinstructions for more important tasks
Hardware interrupts (e.g. power on reset, Hardware interrupts (e.g. power on reset, keyboard, and printer)keyboard, and printer)
Software interrupts (e.g. timer resets, timer Software interrupts (e.g. timer resets, timer interrupts, and traps)interrupts, and traps)
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Methods of informing CPUMethods of informing CPU
Polling Polling –– constantly checks external constantly checks external devices for data by iterationdevices for data by iteration•• similar to picking up a phone when similar to picking up a phone when
waiting for a call because the ringer waiting for a call because the ringer doesn’t workdoesn’t work
•• Why is this so bad…?Why is this so bad…?Interrupts Interrupts –– method of performing standard method of performing standard
operations until the computer is informed to do operations until the computer is informed to do something elsesomething else
InterruptsInterruptsCommunication between CPU and I/OCommunication between CPU and I/Odevices is established with the issue of andevices is established with the issue of aninterrupt request interrupt request
NOTE: Request can be issued at any timeNOTE: Request can be issued at any time
Suspends normal execution and completesSuspends normal execution and completesinstruction in the Interrupt Service Routineinstruction in the Interrupt Service Routine(ISR)(ISR)
Returns to normal program as if no changeReturns to normal program as if no changehas been madehas been made
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1. POR of RESET pin2. Clock monitor reset3. COP watchdog reset4. XIRQ interrupt5. Illegal opcode interrupt6. Software interrupt (SWI)
Types of InterruptsTypes of Interrupts15 15 MaskableMaskable interrupts:interrupts: 6 non6 non--maskablemaskable interuptsinterupts::
Types of InterruptsTypes of InterruptsThe 15 The 15 MaskableMaskable Interrupts:Interrupts:
Two types of MaskingTwo types of Masking•• Local Local -- Interrupt enable bitInterrupt enable bit•• Global Global -- II--bit in CCR bit in CCR
Follows a default priorityFollows a default priorityarrangement. Any onearrangement. Any oneinterrupt can be promoted interrupt can be promoted for higher priority using for higher priority using HPRIO (see previous slide)HPRIO (see previous slide)
Sets I bit in CCR when Sets I bit in CCR when servicedserviced
The 6 NonThe 6 Non--maskablemaskable Interrupts:Interrupts:
Follows the default prioritiesFollows the default priorities
Not subject to global maskingNot subject to global masking
Set I and X bit in CCR when Set I and X bit in CCR when servicedserviced
IRQE Bit in the OPTION control used to specify IRQE Bit in the OPTION control used to specify IRQ pin configurationIRQ pin configuration•• IRQE = 0 Low level SensitiveIRQE = 0 Low level Sensitive•• IRQE = 1 lowIRQE = 1 low--going edge sensitive (single source only)going edge sensitive (single source only)
Interrupts from Internal PeripheralSubsystems • Global masking using I-bit in CCR • Flag bit, which requests service • Interrupt enable bit, which enables flag
to generate interrupt service • Programmer determines whether to use
polling/interrupts for each source
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MaskableMaskable Interrupt: IInterrupt: I--BitBitGlobal Masking by the IGlobal Masking by the I--BitBitBit 4 in the CCRBit 4 in the CCRWhen IWhen I--bit is 0, allows interrupt servicing when bit is 0, allows interrupt servicing when calledcalledWhen IWhen I--bit is 1, inhibits interrupt service bit is 1, inhibits interrupt service (pending)(pending)Set by reset to allow minimum system Set by reset to allow minimum system initializationinitializationSet upon entry in interrupt service routine (ISR)Set upon entry in interrupt service routine (ISR)Can be set by software to inhibit further Can be set by software to inhibit further maskablemaskable interruptsinterrupts•• SEI (Set Interrupt Mask)SEI (Set Interrupt Mask)
Automatically cleared by the RTI instructionAutomatically cleared by the RTI instructionCan be cleared by softwareCan be cleared by software•• CLI (Clear Interrupt Mask)CLI (Clear Interrupt Mask)
Generates interrupt request to the Generates interrupt request to the illegal opcode vectorillegal opcode vectorReinitialize stack pointer once Reinitialize stack pointer once interrupt service is completedinterrupt service is completedLeft Left uninitializeduninitialized, illegal opcode , illegal opcode vector can cause an infinite loop vector can cause an infinite loop causing stack underflowcausing stack underflow
Software instruction, thus cannot beinterrupted until completedUninhibited by global mask bits in the CCRSimilar to other interrupts, sets the I-bit upon servicing
Enabled by TAP instruction by clearing XEnabled by TAP instruction by clearing X--bit upon system initializationbit upon system initializationAfter being cleared, software cannot set After being cleared, software cannot set the Xthe X--bit, thus XIRQ is nonbit, thus XIRQ is non--maskablemaskableHigher priority than any source Higher priority than any source maskablemaskableby the Iby the I--bitbitBoth the X and I bits are automatically set Both the X and I bits are automatically set by hardware after stacking the CCRby hardware after stacking the CCRRTI restores X and I bit to preRTI restores X and I bit to pre--interrupt interrupt statesstates
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Interrupt Flow Interrupt Flow Interrupt condition
Is met
Global Masking
Local Masking
Check flag if cleared
Store all registers on the stack
Complete currentinstruction
A
A
Analyze Priority
Set the (I) or (X)To prohibit another
Interrupt
Standard interrupt table
Load address inProgram counter
B
B
ISR instruction
Clear I or X bitin CCR
Restore registersw/ org. values
RTI
ContinueProgram
yes
no
yes
no
yes
no
no
yes
Note: Flag must be cleared prior to performing RTI
Interrupt Stack PointerInterrupt Stack Pointer
The stack pointer register holds the The stack pointer register holds the location of the top of the stack at all location of the top of the stack at all times.times.When the CPU detects an interrupt, When the CPU detects an interrupt, the contents of the registers are the contents of the registers are pushed on the stack.pushed on the stack.After completion of the interrupt the After completion of the interrupt the saved registers are retrieved form saved registers are retrieved form the stack in a first in last out order.the stack in a first in last out order.
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Stacking OrderStacking Order
CRRSP-8
ACCBSP-7
ACCASP-6
IXHSP-5
IXLSP-4
IYHSP-3
IYLSP-2
PCHSP-1
PCLSP
CPU RegistersMemory Location
First Pushed In Last Pulled Out
Last Pushed In First Pulled Out
Interrupt TypesInterrupt Types
NonNon--Maskable InterruptsMaskable Interrupts•• 6 Non6 Non--Maskable Interrupts.Maskable Interrupts.•• Always interrupts program execution.Always interrupts program execution.•• Has priority over maskable interrupts.Has priority over maskable interrupts.
Maskable InterruptsMaskable Interrupts•• 15 Maskable Interrupts.15 Maskable Interrupts.•• Can be disabled by setting I bit of the CCRCan be disabled by setting I bit of the CCR•• The Priority Level of Maskable Interrupts can The Priority Level of Maskable Interrupts can
Located at $103CLocated at $103CCan be changed at any time during a Can be changed at any time during a program as long as I bit is set.program as long as I bit is set.Bits 0Bits 0--3 are used to set high priority 3 are used to set high priority to one of the maskable interrupts.to one of the maskable interrupts.Default is IRQDefault is IRQ
When a NonWhen a Non--Maskable interrupts Maskable interrupts come in:come in:•• X bit is set to 1, blocking further nonX bit is set to 1, blocking further non--
maskable interrupts.maskable interrupts.•• I bit is set to 1, blocking maskable I bit is set to 1, blocking maskable
interrupts.interrupts.
When a Maskable Interrupt comes When a Maskable Interrupt comes in: in: •• I bit is set to 1, blocking further I bit is set to 1, blocking further
maskable interrupts.maskable interrupts.
Interrupt ProceduresInterrupt Procedures
When executing instructions and a When executing instructions and a nonnon--maskable interrupt comes in:maskable interrupt comes in:
1.1. Finishes current instruction.Finishes current instruction.2.2. Set the X and I bit.Set the X and I bit.3.3. Executes the interrupt.Executes the interrupt.4.4. Return to instructions.Return to instructions.
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Interrupt ProceduresInterrupt Procedures
A maskable interrupt is currently running A maskable interrupt is currently running and a nonand a non--maskable interrupt comes in:maskable interrupt comes in:
1.1. Finishes current instruction of the Finishes current instruction of the maskable interrupt.maskable interrupt.
2.2. Sets the X bit to 1, I bit is already set Sets the X bit to 1, I bit is already set due to the maskable interrupt.due to the maskable interrupt.
3.3. Executes the nonExecutes the non--maskable interrupt.maskable interrupt.4.4. Executes the next interrupt of highest Executes the next interrupt of highest
priority.priority.
Interrupt VectorsInterrupt Vectors
When an interrupt takes place, the When an interrupt takes place, the CPU is directed by the interrupt CPU is directed by the interrupt vector.vector.The address for each interrupt The address for each interrupt source depends on the condition of source depends on the condition of ROMON.ROMON.Each vector is itself an address when Each vector is itself an address when ROMON is enabledROMON is enabled
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Interrupt VectorsInterrupt Vectors
Each interrupt has it’s own vector, If:Each interrupt has it’s own vector, If:ROMON DisabledROMON Disabled•• Vector addresses are not occupied by Buffalo.Vector addresses are not occupied by Buffalo.•• The starting line address of the vector must be The starting line address of the vector must be
programmed into Buffalo.programmed into Buffalo.
ROMON EnabledROMON Enabled•• The jump command ($7E) to the first byte of The jump command ($7E) to the first byte of
the vector address must be in the program.the vector address must be in the program.•• In the remaining two bytes the starting In the remaining two bytes the starting
location of the ISR is written.location of the ISR is written.
Interrupt Vector Table: ROMON DisabledInterrupt Vector Table: ROMON DisabledVector Address Interrupt Source CCR Mask Bit Local Mask
FFC0, C1 – FFD4, D5 Reserved - -FFD6, D7 SCI receive data register full
SCI receiver overrunSCI transmit data register empty
SCI transmit completeSCI idle line detect
I
RIERIETIE
TCIEILIE
FFD8, D9 SPI serial transfer complete I SPIEFFDA,DB Pulse accumulator input edge I PAIIFFDC, DD Pulse accumulator overflow I PAOVIFFDE, DF Timer overflow I TOIFFE0, E1 Timer IC4/OC5 I I4/O5IFFE2, E3 Timer output compare 4 I OC4IFFE4, E5 Timer output compare 3 I OC3IFFE6, E7 Timer output compare 2 I OC2IFFE8, E9 Timer output compare 1 I OC1IFFEA, EB Timer input capture 3 I IC3IFFEC, ED Timer input capture 2 I IC2IFFEE, EF Timer input capture 1 I IC1IFFF0, F1 Real-time interrupt I RTIIFFF2, F3 IRQ (external pin) I NoneFFF4, F5 XIRQ pin X NoneFFF6, F7 Software interrupt None NoneFFF8, F9 Illegal opcode trap None NoneFFFA, FB COP failure None NOCOPFFFC, FD Clock monitor fail None CMEFFFE, FF RESET None None
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Interrupt Vector Table: ROMON EnabledInterrupt Vector Table: ROMON EnabledVector Address Interrupt Source CCR Mask Bit Local Mask
- -00C4-00C6 SCI receive data register full
SCI receiver overrunSCI transmit data register empty
SCI transmit completeSCI idle line detect
I
RIERIETIE
TCIEILIE
00C7-00C9 SPI serial transfer complete I SPIE00CA-00CC Pulse accumulator input edge I PAII00CD-00CF Pulse accumulator overflow I PAOVI00D0-00D1 Timer overflow I TOI00D3-00D5 Timer IC4/OC5 I I4/O5I00D6-00D800D9-00DB
Timer output compare 4 I OC4ITimer output compare 3 I OC3ITimer output compare 2 I OC2ITimer output compare 1 I OC1I
00E2-00E4 Timer input capture 3 I IC3I00E5-00E7 Timer input capture 2 I IC2I00E8-00EA Timer input capture 1 I IC1I00EB-00ED Real-time interrupt I RTII00EE-00EF IRQ (external pin) I None00F1-00F3 XIRQ pin X None00F4-00F6 Software interrupt None None00F7-00F9 Illegal opcode trap None None00FA-00FC COP failure None NOCOP00FA-00FF Clock monitor fail None CME
00DF-00E100DC-00DE
ResetsResetsWhy do we need them?Why do we need them?
•• Lost track of what bits are set whereLost track of what bits are set where
Compare and Contrast to interruptsCompare and Contrast to interrupts
Start with a clean slateStart with a clean slate
•• Initial ConditionsInitial Conditions
Sources of ResetsSources of Resets
Internal vs. ExternalInternal vs. External
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Resets Resets –– What do They Do?What do They Do?Forces HC11 to assume set of initial Forces HC11 to assume set of initial
conditionsconditions
Orderly software startOrderly software start--up from up from
Like interrupts, they share concept of Like interrupts, they share concept of
vector fetching to force a new starting vector fetching to force a new starting
point for further CPU operationspoint for further CPU operations
Unlike interrupts they don’t save any Unlike interrupts they don’t save any
statesstates
System Initial ConditionsSystem Initial ConditionsCPUCPU
Upon reset, CPU fetches restart vector from Upon reset, CPU fetches restart vector from $FFFE, $FFFF during the first 3 cycles and begins $FFFE, $FFFF during the first 3 cycles and begins executing instructionsexecuting instructions
Stack pointer and other CPU registers are Stack pointer and other CPU registers are indeterminate immediately after resetindeterminate immediately after reset
X and I interrupt mask bits in the CCR are set to X and I interrupt mask bits in the CCR are set to mask any interrupt requestsmask any interrupt requests
X= 1 I=1X= 1 I=1
S bit is also set in CCR to disable stop modeS bit is also set in CCR to disable stop mode
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System Initial ConditionsSystem Initial ConditionsMemory MapMemory Map
INIT register initialized to $01INIT register initialized to $01•• Puts 256 bytes of RAM at $0000Puts 256 bytes of RAM at $0000--$00FF$00FF•• Puts control registers at $1000Puts control registers at $1000--$103F$103F
Parallel Input/Output (I/O)Strobe A Flag (STAF), strobe A interrupt Strobe A Flag (STAF), strobe A interrupt (STAI), and handshake (HNDS) control (STAI), and handshake (HNDS) control bits in parallel I/O control register are bits in parallel I/O control register are clearedcleared•• Prevents interrupt from being enabledPrevents interrupt from being enabledAll other A All other A –– E registers set back to block E registers set back to block diagram in reference manual diagram in reference manual
System Initial ConditionsSystem Initial ConditionsTimerTimer
Initialized to count of $0000Initialized to count of $0000All output compare (OC) registers are All output compare (OC) registers are initialized to $FFFFinitialized to $FFFF•• Use OC to program an action to occur at Use OC to program an action to occur at
a specific time (when counter matches a specific time (when counter matches OC register, task is executed)OC register, task is executed)
Input capture registers are Input capture registers are indeterminateindeterminate•• IC records the time that an external IC records the time that an external
event takesevent takes
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Effects of ResetsEffects of Resets
Real Time Interrupt flag is cleared to allow for Real Time Interrupt flag is cleared to allow for other RTI’s to followother RTI’s to follow•• This interrupt exists to establish a heartbeat you can use This interrupt exists to establish a heartbeat you can use
to watch time passto watch time pass
Memory MapMemory Map
Pulse AccumulatorPulse Accumulator•• PAI pin defaults to a general purpose inputPAI pin defaults to a general purpose input
COP Watchdog (more detail later)COP Watchdog (more detail later)•• Enabled if NOCOP control bit in CONFIG register is clear Enabled if NOCOP control bit in CONFIG register is clear
Reset changes even moreReset changes even moreSerial Communications Interface (SCI)Serial Communications Interface (SCI)•• Baud rate must be reestablishedBaud rate must be reestablished•• Transmitter and receiver are disabledTransmitter and receiver are disabledSerial Peripheral Interface (SPI)Serial Peripheral Interface (SPI)•• Disabled by resettingDisabled by resettingAnalogAnalog--toto--Digital Converter (A/D)Digital Converter (A/D)•• Conversion complete flag is cleared by resetConversion complete flag is cleared by reset•• ADPU bit is cleared, disabling A/D systemADPU bit is cleared, disabling A/D systemMode of operationMode of operation•• Determined by bits set in the HPRIO registerDetermined by bits set in the HPRIO register•• Can be found on page 167 of reference manualCan be found on page 167 of reference manual
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RememberRemember
Don’t assume what is set where, Don’t assume what is set where, check all necessary register control check all necessary register control bits, so less errors are encounteredbits, so less errors are encountered
When reset condition sensed, pin is When reset condition sensed, pin is driven low for 4 Edriven low for 4 E--clock cycles, then clock cycles, then releasedreleasedPin is sampled 2 EPin is sampled 2 E--clock cycles laterclock cycles later•• If still low: system assumes external If still low: system assumes external
reset has occurredreset has occurred•• Else: reset was initiated by COP Else: reset was initiated by COP
watchdog or clock monitorwatchdog or clock monitor
RESET pin usageRESET pin usage
Should be held low (by external Should be held low (by external circuit) while Vcircuit) while VDDDD is below minimum is below minimum operating level to protect EEPROM operating level to protect EEPROM from corruptionfrom corruptionThis minimum level should exceed This minimum level should exceed 4.6 V to prevent accidental 4.6 V to prevent accidental overwriting of EEPROMoverwriting of EEPROM
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PowerPower--on Reset (POR)on Reset (POR)
Used only for powerUsed only for power--up conditions to up conditions to initialize MCU internal circuitsinitialize MCU internal circuitsApplying VApplying VDDDD to the MCU triggers the to the MCU triggers the POR circuit, initiates a reset POR circuit, initiates a reset sequence, and starts an internal sequence, and starts an internal timing circuittiming circuitA 4064 clock cycle delay after the A 4064 clock cycle delay after the oscillator becomes active, allows the oscillator becomes active, allows the clock generator to stabilizeclock generator to stabilize
COP Watchdog Timer ResetCOP Watchdog Timer Reset
The COP is a constantly decreasing The COP is a constantly decreasing timer that is never supposed to timer that is never supposed to reach zero reach zero Reset occurs when watchdog times Reset occurs when watchdog times out (counter gets to zero)out (counter gets to zero)Intended to detect software Intended to detect software processing errorsprocessing errorsProgrammer must periodically restart Programmer must periodically restart the watchdog timer the watchdog timer
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Servicing the COP TimerServicing the COP Timer
1. Write $55 to COPRST register to arm 1. Write $55 to COPRST register to arm the clearing mechanismthe clearing mechanism2. Write $AA to the COPRST register2. Write $AA to the COPRST registerAny number of instructions can be Any number of instructions can be performed between the above 2 stepsperformed between the above 2 stepsMust be performed in the correct Must be performed in the correct sequence before the timer times outsequence before the timer times outRates are set by bits CR1 and CR0 in Rates are set by bits CR1 and CR0 in COPRST registerCOPRST register
Clock Monitor Reset (CMR)Clock Monitor Reset (CMR)Detects a slow or stopped E clockDetects a slow or stopped E clockAn EAn E--clock frequency below 10 kHz is clock frequency below 10 kHz is detected as a clock monitor errordetected as a clock monitor errorEnabled by setting the CME bit in OPTIONEnabled by setting the CME bit in OPTIONUseful as a backup for COP watchdog Useful as a backup for COP watchdog because CMR requires no clock while COP because CMR requires no clock while COP does does CMR also provides additional level of CMR also provides additional level of protection by generating a system reset if protection by generating a system reset if the MCU clocks are accidentally stoppedthe MCU clocks are accidentally stopped
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Process Flow out of Resets When Process Flow out of Resets When TriggeredTriggered
Vector fetch (program counter Vector fetch (program counter loaded with contents of specified loaded with contents of specified address)address)S, X, and I bits set in the CCRS, X, and I bits set in the CCRMCU hardware resetMCU hardware resetChecks for interruptsChecks for interrupts
Low Power Modes (LPM)Low Power Modes (LPM)
To reduce power consumption of the To reduce power consumption of the controllercontrollerTemporarily stops CPU operations Temporarily stops CPU operations until a reset or interrupt occursuntil a reset or interrupt occurs2 modes2 modes•• WAITWAIT•• STOPSTOP
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LPM: Wait ModeLPM: Wait ModeCommand: WAICommand: WAICPU always shut down during wait modeCPU always shut down during wait modeCPU registers are stackedCPU registers are stackedProgram is suspended until interruptedProgram is suspended until interruptedOnOn--chip crystal oscillator remains activechip crystal oscillator remains activePower conservation depends on number of Power conservation depends on number of peripheral systems shut downperipheral systems shut down•• A/D, SPI, and SCI can be shut down by A/D, SPI, and SCI can be shut down by
Stop ModeStop ModeCommand: STOP + S bit of CCR is clearCommand: STOP + S bit of CCR is clearLowest possible power consumptionLowest possible power consumptionAll clocks are stopped (crystal oscillator too)All clocks are stopped (crystal oscillator too)Data in internal RAM is retained as long as Data in internal RAM is retained as long as VVDDDD power is maintainedpower is maintainedExit using RESET, XIRQ, or unmasked IRQExit using RESET, XIRQ, or unmasked IRQXIRQ has 2 recover methodsXIRQ has 2 recover methods•• If X is set, returns to command following STOPIf X is set, returns to command following STOP•• If X is clear, stacking sequence that leads to If X is clear, stacking sequence that leads to
normal XIRQ requestnormal XIRQ request
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UsesUses
Important eventsImportant events•• Prepare system for shutdownPrepare system for shutdown•• Power supply switched to battery backupPower supply switched to battery backup
Infrequent events Infrequent events •• Warning light in carWarning light in car•• Activate switch when temperature gets too Activate switch when temperature gets too
highhigh
Slow eventsSlow events•• Can use end of conversion bit to signal reading Can use end of conversion bit to signal reading
of data because A/D converter is slowof data because A/D converter is slow
Real World ApplicationsReal World Applications
Cell phonesCell phonesPause button on VCRPause button on VCRInput capture of optical encoder for Input capture of optical encoder for DC motor labDC motor labOptical sensorsOptical sensorsSet a light to go on in a certain timeSet a light to go on in a certain timeCompiler recognizes an error (illegal Compiler recognizes an error (illegal opcode trap)opcode trap)
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Example ProgramExample ProgramWrite a routine to interrupt the HC11 after 10 Write a routine to interrupt the HC11 after 10 msecmsec of elapsed time (Assume E=1Mhz, of elapsed time (Assume E=1Mhz,
PrescalarPrescalar = 1) using OC3.= 1) using OC3.ORG $C000ORG $C000SEISEI /* Set I bit in CCR. Stops /* Set I bit in CCR. Stops maskablemaskable interrupts interrupts
from from occuringoccuring */*/LDAA #BIT5HI LDAA #BIT5HI /* BIT5HI = %00100000 *//* BIT5HI = %00100000 */STAA TFLG1STAA TFLG1 /* Clear previously set OC3 Flag *//* Clear previously set OC3 Flag */STAA TMSK1STAA TMSK1 /* Enable OC3 Interrupt *//* Enable OC3 Interrupt */LDAB #$30LDAB #$30 /* $30 = %00110000 *//* $30 = %00110000 */STAB TCTL1STAB TCTL1 /* OC3 (PA5) will be high for a successful compare *//* OC3 (PA5) will be high for a successful compare */LDAA #JUMPLDAA #JUMP /* JUMP = $07E *//* JUMP = $07E */STAA FIRSTAD STAA FIRSTAD /* FIRSTAD = $00D9 *//* FIRSTAD = $00D9 */LDX #OC3ISRLDX #OC3ISR /* OC3ISR = $D000, 2 bytes /* OC3ISR = $D000, 2 bytes –– beginning address beginning address
of interrupt service routine */of interrupt service routine */STX SECONDAD STX SECONDAD /* SECONDAD = $00DA. High byte (DO) stored in /* SECONDAD = $00DA. High byte (DO) stored in
location $00DA and low byte (00) stored in location $00DA and low byte (00) stored in $00DB */$00DB */
LDD TCNTLDD TCNT /* TCNT = $100E *//* TCNT = $100E */ADDD #DLYIOMSADDD #DLYIOMS /* DYLIOMS = $2710 = 10000 cycles or 10 /* DYLIOMS = $2710 = 10000 cycles or 10 msecmsec */*/STD TOC3STD TOC3 /* If not done elsewhere *//* If not done elsewhere */
LDAA #$00LDAA #$00 /* Clears CCR including I and X bits. Lets /* Clears CCR including I and X bits. Lets maskablemaskable and nonand non--maskablemaskable interrupts occur.interrupts occur.
TAPTAP TAP transfers Accumulator A to CCR */TAP transfers Accumulator A to CCR */
Ex. Program Technical DataEx. Program Technical Data
00000100Program:
00000000Reset:
Read:Write: IC3FIC2FIC1FI4/O5FOC4FOC3FOC2FOC1F
0123456BIT 7
Result of writing 1 to OC3F (Bit 5) clears the flag. Flag is setResult of writing 1 to OC3F (Bit 5) clears the flag. Flag is set when clock matches output compare 3.when clock matches output compare 3.
If the OC3I enable bit is set when the OC3F flag bit is set, a hIf the OC3I enable bit is set when the OC3F flag bit is set, a hardware sequence is requestedardware sequence is requested
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Ex. Program Technical DataEx. Program Technical Data(continued)(continued)
Code bit pairs are encoded to specify the action taken after a sCode bit pairs are encoded to specify the action taken after a successful uccessful OCxOCx compare.compare.
Address:Address: $1020$1020 Timer Control Register 1 (TCTL1)Timer Control Register 1 (TCTL1)
Ex. Program Technical DataEx. Program Technical Data(continued)(continued)
