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7/21/2019 Intro to Computer Architecture
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CS 136, Advanced Architecture
Class Introduction
7/21/2019 Intro to Computer Architecture
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CS 136 2
Outline
• Computer science at a crossroads
• Computer architecture vs. instruction-setarchitecture
• A few course details
• What computer architecture brings to table
7/21/2019 Intro to Computer Architecture
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CS 136 3
Crossroads: Conventional Wisdom
• Old conventional wisdom: – Power is free
– Transistors are expensive
• New conventional wisdom: “Power wall” – Power expensive
– Transistors “free”(Can put more on chip than can afford to turn on)
7/21/2019 Intro to Computer Architecture
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CS 136 4
Conventional Wisdom (cont‟d)
• Old conventional wisdom: – Instruction-level parallelism gives performance advances
» Compilers
» Innovation• Out-of-order execution
• Speculation
• Very long instruction words (VLIW)
• New conventional wisdom: “ILP wall” – Law of diminishing returns on more HW for ILP
7/21/2019 Intro to Computer Architecture
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CS 136 5
Conventional Wisdom (cont‟d)
• Old conventional wisdom: – Multiplies are slow
– Memory access is fast
• New conventional wisdom: “Memory wall” – Memory slow
(200 clock cycles to DRAM memory) – Multiplies fast
(4 clocks)
7/21/2019 Intro to Computer Architecture
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CS 136 6
Conventional Wisdom (cont‟d)
• Old conventional wisdom: – Uniprocessor performance doubles every 1.5 yrs
• New conventional wisdom: – Power Wall + ILP Wall + Memory Wall = Brick Wall
7/21/2019 Intro to Computer Architecture
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CS 136 7
The End of Conventional Wisdom
• Uniprocessor performance now doubles every5(?) yrs
⇒ Sea change in chip design: multiple “cores”(2X processors per chip every ~2 years)
• More but simpler processors⇒ More power efficient
7/21/2019 Intro to Computer Architecture
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CS 136 8
1
10
100
1000
10000
1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002 2004 2006
P e r f o r m a n c e ( v
s .
V A X - 1 1 / 7 8 0 )
25%/year
52%/year
??%/year
Crossroads: Uniprocessor Performance
• VAX : 25%/year 1978 to 1986• RISC + x86: 52%/year 1986 to 2002• RISC + x86: ??%/year 2002 to present
From Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4th
edition, October, 2006
7/21/2019 Intro to Computer Architecture
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CS 136 9
Sea Change in Chip Design
• Intel 4004 (1971): 4-bit processor,
2312 transistors, 0.4 MHz,10 micron PMOS, 11 mm2 chip
• Processor is the new transistor?
• RISC II (1983): 32-bit, 5 stagepipeline, 40,760 transistors, 3 MHz,3 micron NMOS, 60 mm2 chip
• 125 mm2 chip, 0.065 micron CMOS= 2312 RISC II+FPU+Icache+Dcache
– RISC II shrinks to ~ 0.02 mm2 at 65 nm
– Caches via DRAM or 1 transistor SRAM (www.t-ram.com) ? – Proximity Communication via capacitive coupling at > 1 TB/s ?
(Ivan Sutherland @ Sun / Berkeley)
7/21/2019 Intro to Computer Architecture
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CS 136 10
Déjà vu All Over Again?
• Multiprocessors imminent in 1970s, „80s, „90s, … “… today‟s processors … are nearing an impasse as
technologies approach the speed of light..”
David Mitchell, The Transpu ter: The Time Is Now (1989)
• Transputer was premature
Custom multiprocessors strove to lead uniprocessors Procrastination rewarded: 2X sequential perf. / 1.5 years
“We are dedicating all of our future product development tomulticore designs. … This is a sea change in computing”
Paul Otellini, President, Intel (2004)• Difference is all microprocessor companies switch to
multiprocessors (AMD, Intel, IBM, Sun; all new Apples 2 CPUs) Procrastination penalized: 2X sequential perf. / 5 yrs Biggest programming challenge: 1 to 2 CPUs
7/21/2019 Intro to Computer Architecture
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CS 136 11
Problems with Sea Change
• Algorithms, Programming Languages, Compilers,Operating Systems, Architectures, Libraries, … notready to supply thread-level or data-level parallelismfor 1000 CPUs / chip (or even tens)
•
Architectures not ready for 1000 CPUs / chip• Unlike instruction-level parallelism, can‟t be solved just by
computer architects and compiler writers alone
• Also can‟t be solved wi thout participation of computer architects
• This edition of CS 136 (and 4th Edition of textbook
Computer Architecture: A Quantitative Approach)explores shift from instruction-level parallelism tothread-level / data-level parallelism
7/21/2019 Intro to Computer Architecture
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CS 136 12
Outline
• Computer science at a crossroads
• Computer architecture vs. instruction-setarchitecture
• A few course details
• What computer architecture brings to table
7/21/2019 Intro to Computer Architecture
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CS 136 13
Instruction Set Architecture:Critical Interface
•
Properties of a good abstraction – Lasts through many generations (portability)
– Used in many different ways (generality)
– Provides convenient functionality to higher levels
– Permits an efficient implementation at lower levels
instruction set
software
hardware
7/21/2019 Intro to Computer Architecture
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CS 136 14
Instruction Set Architecture
“... the attributes of a [computing] system as seen by
the programmer, i.e. the conceptual structure andfunctional behavior, as distinct from the organizationof the data flows and controls the logic design, andthe physical implementation.”
– Amdahl, Blaauw, and Brooks, 1964
SOFTWARE-- Organization of Programmable
Storage
-- Data Types & Data Structures:Encodings & Representations
-- Instruction Formats
-- Instruction (or Operation Code) Set
-- Modes of Addressing and Accessing Data Items and Instructions
-- Exceptional Conditions
7/21/2019 Intro to Computer Architecture
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CS 136 15
Example: MIPS32
0r0r1°°°r31
PClo
hi
Programmable storage
2^32 x bytes31 x 32-bit GPRs (R0=0)
32 x 32-bit FP regs (paired DP)
HI, LO, PC
Data types ?
Format ?
Addressing Modes?
Arithmetic/Logical
ADD, ADDU, SUB, SUBU, AND, OR, XOR, NOR, SLT, SLTU,
ADDI, ADDIU, SLTI, SLTIU, ANDI, ORI, XORI, LUI
SLL, SRL, SRA, SLLV, SRLV, SRAV
Memory Access
LB, LBU, LH, LHU, LW, LWL,LWR
SB, SH, SW, SWL, SWR
Control
J, JAL, JR, JALR
BEQ, BNE, BLEZ,BGTZ,BLTZ,BGEZ,BLTZAL,BGEZAL
32-bit instructions on word boundary
7/21/2019 Intro to Computer Architecture
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CS 136 16
ISA vs. Computer Architecture
• Old definition of computer architecture= instruction set design
– Other aspects of computer design called implementation
– Insinuates implementation is uninteresting or less challenging
• Our view is computer architecture >> ISA
• Architect‟s job much more than instruction setdesign; technical hurdles today more challengingthan those in instruction set design
• Since instruction set design not where action is,
some conclude computer architecture (using olddefinition) is not where action is – We disagree on conclusion
– Agree that ISA not where action is (ISA in CA:AQA 4/e appendix)
7/21/2019 Intro to Computer Architecture
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CS 136 17
Comp. Arch. is anIntegrated Approach
• What really matters is the functioning of thecomplete system
– Hardware, runtime system, compiler, operating system, andapplication
– In networking, this is called the “End-to-End argument”
• Computer architecture is not just abouttransistors, individual instructions, or particularimplementations
– E.g., original RISC projects replaced complex instructionswith a compiler + simple instructions
7/21/2019 Intro to Computer Architecture
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CS 136 18
Computer Architecture isDesign and Analysis
Design
Analysis
Architecture is an iterative process:• Searching the space of possible designs• At all levels of computer systems
Creativity
Good Ideas
Mediocre Ideas
Bad Ideas
Cost /Performance
Analysis
7/21/2019 Intro to Computer Architecture
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CS 136 19
Outline
• Computer science at a crossroads
• Computer architecture vs. instruction-setarchitecture
• A few course details
• What computer architecture brings to table
7/21/2019 Intro to Computer Architecture
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CS 136 20
CS136: AdministriviaInstructor: Geoff Kuenning
Office: Olin 1240
E-mail: [email protected]
AIM: ProfKuenning
Office Hours: See web page
Class: MW, 2:45-4:00
Text: Compu ter Arc hitecture: A Quanti tat ive Appro ach,
4th Edit ion (Oct, 2006)
Web page: http://www.cs.hmc.edu/~geoff/cs136
First reading assignment: Chapter 1 for today and Monday
7/21/2019 Intro to Computer Architecture
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CS 136 21
Graded Work
• Still somewhat in flux
• Rough plan: – Written homeworks for each chapter (~20%)
– Occasional announced quizzes (~10%)
– One midterm (~30%)
–
Final project (~40%) – Participation (~10%)
– Yes, I know this doesn‟t add up!
7/21/2019 Intro to Computer Architecture
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CS 136 22
Graded Work
• Still somewhat in flux
• Rough plan: – Written homeworks for each chapter (~20%)
– Occasional announced quizzes (~10%)
– One midterm (~30%)
–
Final project (~40%) – Participation (~10%)
7/21/2019 Intro to Computer Architecture
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CS 136 23
CS 136 Course Focus
Understanding the design techniques, machinestructures, technology factors, evaluationmethods that will determine the form ofcomputers in 21st Century
Technology ProgrammingLanguages
OperatingSystems History
Applications Interface Design(ISA)
Measurement &Evaluation
Parallelism
Computer Architecture:• Organization • Hardware/Software Boundary
Compilers
7/21/2019 Intro to Computer Architecture
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CS 136 24
Project Options
• Recreate results from research paper to see – If they are reproducible
– If they still hold
• Survey research papers on chosen topic – Compare and contrast
–
Conclude which approach is better• Propose and evaluate new design element
• Detailed review of an architecture – Interesting choices
– Mistakes that were made
• Propose your own project that is related tocomputer architecture
7/21/2019 Intro to Computer Architecture
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CS 136 25
Project Details
• Individual or pair (prefer pair; must get approval
to work alone)
• Project must be approved by instructor
• Preliminary results due as term goes along
• Final presentation and reports
7/21/2019 Intro to Computer Architecture
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CS 136 26
Outline
• Computer science at a crossroads
• Computer architecture vs. instruction-setarchitecture
• A few course details
• What computer architecture brings to table
7/21/2019 Intro to Computer Architecture
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CS 136 27
What Computer Architecture Brings to Table
• Other fields often borrow ideas from architecture
• Quantitative Principles of Design1. Take Advantage of Parallelism
2. Principle of Locality
3. Focus on the Common Case
4. Amdahl‟s Law
5. The Processor Performance Equation• Careful, quantitative comparisons
– Define, quantify, and summarize relative performance
– Define and quantify relative cost
– Define and quantify dependability
–
Define and quantify power• Culture of anticipating and exploiting advances in
technology
• Culture of well-defined interfaces that are carefullyimplemented and thoroughly checked
7/21/2019 Intro to Computer Architecture
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CS 136 28
1) Taking Advantage of Parallelism
• Increasing throughput of server computer via
multiple processors or multiple disks
• Detailed HW design – Carry-lookahead adders use parallelism to speed up computing
sums from linear to logarithmic in number of bits per operand
– Multiple memory banks searched in parallel in set-associativecaches
• Pipelining: overlap instruction execution to reducethe total time to complete an instruction sequence.
– Not every instruction depends on immediate predecessorexecuting instructions completely/partially in parallel possible
– Classic 5-stage pipeline:1) Instruction Fetch (Ifetch),2) Register Read (Reg),3) Execute (ALU),4) Data Memory Access (Dmem),5) Register Write (Reg)
7/21/2019 Intro to Computer Architecture
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CS 136 29
Pipelined Instruction Execution
Ins
tr.
Ord
er
Time (clock cycles)
Reg A L U
DMemIfetch Reg
Reg A L U
DMemIfetch Reg
Reg A L U
DMemIfetch Reg
Reg A L U
DMemIfetch Reg
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 6 Cycle 7 Cycle 5
7/21/2019 Intro to Computer Architecture
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CS 136 30
Limits to Pipelining
In
str.
Order
Time (clock cycles)
Reg A L U
DMemIfetch Reg
Reg A L U
DMemIfetch Reg
Reg A L U
DMemIfetch Reg
Reg A L U
DMemIfetch Reg
•
Hazards prevent next instruction from executingduring its designated clock cycle – Structural hazards: attempt to use the same hardware to do
two different things at once
– Data hazards: Instruction depends on result of priorinstruction still in the pipeline
– Control hazards: Caused by delay between the fetching ofinstructions and decisions about changes in control flow(branches and jumps).
7/21/2019 Intro to Computer Architecture
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CS 136 31
2) The Principle of Locality
• The Principle of Locality: – Program access a relatively small portion of the address space at
any instant of time.
• Two Different Types of Locality: – Temporal Locality (Locality in Time): If an item is referenced, it will
tend to be referenced again soon (e.g., loops, reuse)
– Spatial Locality (Locality in Space): If an item is referenced, itemswhose addresses are close by tend to be referenced soon(e.g., straight-line code, array access)
• Last 30 years, HW relied on locality for memory perf.
P MEM$
L l f th M Hi h
7/21/2019 Intro to Computer Architecture
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CS 136 32
Levels of the Memory Hierarchy
CPU Registers100s Bytes
300 – 500 ps (0.3-0.5 ns)
L1 and L2 Cache10s-100s K Bytes~1 ns - ~10 ns$1000s/ GByte
Main MemoryG Bytes80ns- 200ns~$100/ GByte
Disk10s T Bytes, 10 ms(10,000,000 ns)~$1 / GByte
CapacityAccess TimeCost
Tapeinfinitesec-min~$1 / GByte
Registers
L1 Cache
Memory
Disk
Tape
Instr. Operands
Blocks
Pages
Files
StagingTransfer Unit
prog./compiler1-8 bytes
cache cntl32-64 bytes
OS4K-8K bytes
user/operatorMbytes
Upper Level
Lower Level
faster
Larger
L2 Cache
cache cntl64-128 bytesBlocks
7/21/2019 Intro to Computer Architecture
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CS 136 33
3) Focus on the Common Case
• Common sense guides computer design – Since it‟s engineering, common sense is valuable
• In making a design trade-off, favor the frequentcase over the infrequent case
– E.g., Instruction fetch and decode unit used more frequentlythan multiplier, so optimize it 1st
–
E.g., If database server has 50 disks / processor, storagedependability dominates system dependability, so optimize it 1st
• Frequent case is often simpler and can be donefaster than the infrequent case
– E.g., overflow is rare when adding 2 numbers, so improveperformance by optimizing more common case of no overflow
– May slow down overflow, but overall performance improved byoptimizing for the normal case
• What is frequent case and how much performanceimproved by making case faster => Amdahl‟s Law
7/21/2019 Intro to Computer Architecture
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CS 136 34
4) Amdahl‟s Law
enhanced
enhancedenhanced
new
oldoverall
SpeedupFraction Fraction
1
ExTime
ExTime Speedup
1
Best you could ever hope to do:
enhancedmaximum Fraction-1
1 Speedup
enhancedenhancedenhancedoldnew Speedup
FractionFractionExTimeExTime 1
7/21/2019 Intro to Computer Architecture
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CS 136 35
Amdahl‟s Law Example
• New CPU 10X faster
• I/O-bound server, so 60% time waiting for I/O
56.1
64.0
1
10
0.4 0.41
1
Speedup
Fraction Fraction1
1 Speedup
enhanced
enhancedenhanced
overall
• Apparently, it‟s human nature to be attracted by 10Xfaster, vs. keeping in perspective it‟s just 1.6Xfaster
7/21/2019 Intro to Computer Architecture
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CS 136 36
Amdahl‟s Law in Reality
• John Ousterhout (of TCL fame): “Why Aren‟t
Operating Systems Getting Faster as Fast asHardware?”, Usenix Summer Conference, 1990
– Conclusion: we‟re I/O-bound
– Note that CS136 doesn‟t really address this issue
•
…and you wonder why I‟m a file systems geek!
CPI
7/21/2019 Intro to Computer Architecture
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CS 136 37
5) Processor Performance Equation
CPU time = Seconds = Instructions x Cycles x Seconds
Program Program Instruction Cycle
Inst Count CPI Clock RateProgram X
Compiler X (X)
Inst. Set. X X
Organization X X
Technology X
inst count
CPI
Cycle time
Big-O StillMatters!
7/21/2019 Intro to Computer Architecture
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CS 136 38
What‟s a Clock Cycle?
• Old days: 10 levels of gates• Today: determined by numerous time-of-flight
issues + gate delays – Clock propagation, wire lengths, drivers
Latchor
register
combinationallogic
7/21/2019 Intro to Computer Architecture
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CS 136 39
And in conclusion …
• Computer Architecture >> instruction sets
• Computer Architecture skill sets are different – 5 Quantitative principles of design
– Quantitative approach to design
– Solid interfaces that really work
–
Technology tracking and anticipation• Computer Science at the crossroads from
sequential to parallel computing – Salvation requires innovation in many fields, including
computer architecture
• Read Chapter 1, then Appendix A – P.S. Small bounty for errata; see text for details