Intro to FPGAs
October 11, 2006
Programmable Logic
Implement wide variety of logic functions inone digital chip
Gates: AND, OR, NOT Storage: Flip flop, latch Switches: Mux Larger blocks: Memory, adder
History
Individual chips (esp. 7400 series TTL) ROM as lookup table 1970s: PAL – one-time field programmable, dozens
of gates 1980s: GAL – reprogrammable, hundreds of gates,
CPLD – several thousand gates, FPGA – tens ofthousand gates
1990s: CPLD/FPGA get larger, FPGAs get moreflexibility/features
FPGAs Now
Some one-time programmable, some re-programmable, some in-systemprogrammable
Few thousand to few million gates Few dozen to thousand I/O pins Available with variety of power profiles,
clocking schemes, RAM blocks, DSP blocks,I/O standards
FPGA vs Custom Chip (ASIC)
Advantages Shorter time to market Re-program in field Low NRE costs
Disadvantages Slower Higher power Less complex designs
FPGA vs Software
Advantages Faster for logic (esp. shift operations) Faster for some atypical bit lengths Good control over timing Often more pinouts
Disadvantages Slower for math Less flexible/familiar May be more expensive
Getting Started with an FPGA
Pick a technology Reprogrammable? Power? Security? Speed?
Environment? Pick a manufacturer
Xilinx, Altera, Lattice, Actel Pick an evaluation board or design your own
board Pick a tool set for programming
FPGA for this class
Xilinx Spartan3 XC3S1500-4FG320 1.5 Million Gates Speed: “-4” Package: Fine-pitch ball grid array, 320 pins
(221 user I/O)
Opal Kelly Board: XEM3010
http://www.opalkelly.com/products/xem3010/
Opal Kelly Board: XEM3010
http://www.opalkelly.com/products/xem3010/
Programming an FPGA
Think hardware! Start with a block diagram Describe the circuit, not an algorithm Schematic or VHDL (or Verilog)
Schematic: more precise VHDL: faster to write/change Most people use VHDL, but keep schematic in
mind
Xilinx Design Flow
http://toolbox.xilinx.com/docsan/xilinx7/help/iseguide/html/ise_fpga_design_flow_overview.htm
Getting Started: Create a Project
Xilinx ISE File -> New Project
Careful! ISE doesn’t like spaces Select options for target chip
Design Entry: VHDL
Create new source -> VHDL module Specify inputs and outputs (make sure
names match documentation) Use the “lightbulb” language templates for
help “Synthesis” constructs VHDL also has strong modeling ability, but
these won’t synthesize to a circuit so becareful
Synthesis
Checks code syntax Analyzes design hierarchy Produces Xilinx-specific netlist Can also view produced schematic
Many advanced options, but just leave at default fornow
Read synthesis reports! Understanding anywarnings before proceeding
Implementation
Translates netlists and constraints Maps the design into available resources Places and routes these resources to meet constraints Also generates timing models for more complete
simulation
*.ucf has the pin list. Add and edit the *.ucf file toreflect input and output pins before implementing.
Read the “pad report” to make sure the pins wereassigned as desired
Programming File
Creates a bit stream to download to the chip Use Opal Kelly Front Panel to download this
*.bit to the FPGA
Async vs Sync
Asynchronous logic progresses continuously Pipe analogy AND, OR, NOT…
Synchronous logic progresses on clockedges Valve analogy Flip flops
Flip Flop
Simple storage element Input transferred to output on clock edge Output held until next clock edge Reset to known state (usually async) Clock enable signal to enable/disable
transfers
Sim: Flip flops
RTL Example: Flip flops
VHDL Example: Flip flops
Sim: Counter+1 Counting Reset
RTL example: Counter
VHDL Example : Counter
In Class Today
Make LEDs display repeating pattern Pick pattern (suggestion: binary counting) Control whether pattern is moving or not Use speed where pattern is visible. Better yet,
make it move once per second
Hints
Be careful with active high/low Double-check *.ucf file Use Xilinx help as needed (lightbulb)