Intro to Msc51

8/3/2019 Intro to Msc51

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The 8051 MicroController

In this module, we will be discussing the

MCS-51 family of microcontroller, in

particular the 8051, which is the generic ICrepresentative of this family.


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Important 8051 Features

4K bytes ROM

128 bytes RAM

Four 8-bit I/O ports

Two 16-bit timers

Serial interface 64K external code memory space

64K data memory space


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FIGURE 21 8051 block diagram


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Pin Layout

The 8051 is a 40 pin device, but out of these40 pins, 32 are used for I/O.

24 of these are dual purpose, i.e. they can

operate as I/O or a control line or as part ofaddress or date bus.


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FIGURE 22 8051 pinouts


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Port 0 and Port 1

Port 0 is a dual purpose port, it is located

from pin 32 to pin 39 (8 pins) and is labeled

in the fig.2-2 as AD0 to AD7.

Port 1 is a dedicated I/O port from pin 1 to

pin 8. It is generally used for interfacing to

external device thus if you need to connectto switches or LEDs, you could make use of

these 8 pins.


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Port 2 and Port 3

Like port 0, port 2 is a dual-purpose port. It can beused for general I/O or as the high byte of theaddress bus for designs with external codememory.

Port 3 is also dual purpose but designers generallyavoid using this port unnecessarily for I/O becausethe pins have alternate functions which are relatedto special features of the 8051. Indiscriminate useof these pins may interfere with the normaloperation of the 8051.


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_____

PSEN (Program Store Enable)This is a dedicated control line on pin 29 and is

used to enable external program (code)

memory. This pin usually connects to an

EPROMs Output Enable (OE) pin.This is a logic low pin as represented by the bar

above the word PSEN, this means that during a

fetch stage involving an instruction stored in

external memory, the pin will be pulsed

LOW.


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ALE ( Address Latch Enable)

This pin is used to demultiplex the address and

data lines.Remember that port 0 has 2 functions. As the

low byte of the address bus and as the data bus.In designs with external memory, port 0 is

connected to both the address and data lines ofthe external RAM thus during the part of thefetch cycle where the address is supplied, theALE is pulsed to enable the G (gate) control pin

of the latch IC thus the data goes to RAM andis interpreted as an address. (see fig 2-10 and 2-11).


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___

EA (External Access)

If you need to connect to external ROM then

this pin must be tied LOW (0V).

This pin must be tied high (+5V) if the

programs executes from internal ROM.


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RST (Reset)

This is pin 9 of the IC and is used as themaster reset for the 8051. In order for the

8051 to recognise that a reset has occurred,

this pin must be brought HIGH for at least

two machine cycles. During normal

operation, this pin must be at logic LOW.

This will be discussed in more detail later.


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Oscillator ( clock) Input

The 8051 is typically driven by a crystaloscillator connected to pin 18 and 19 as

shown in fig.2-3.

The words XTAL is short for crysTAL.


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FIGURE 23 Driving the 8051 from a TTL oscillator


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Power Connections

The 8051 requires a +5V input on its Vcc input

(pin 40) and Vss connection is on page 20.


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I/O Port Structure

The internal circuitry for the I/O port is shown infig 2-4.

If you want to read in from a pin, you must first

give a logic 1 to the port latch to turn off the

FET otherwise the data read in will always be

logic 0.

When you write to the port you are actually

writing to the latch e.g. a logic 0 given to the latchwill be inverted and turn on the FET which cause

the port pin to be connected to gnd (logic 0).


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FIGURE 24 Circuitry for I/O ports


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Machine Cycle and Clock Cycle

12 clock cycles make one machine cycle as

shown in fig 2-5.

E.g. if we use a 12 MHz oscillator, eachclock cycle will have a time period of

1/12MHz. Twelve of these make one

machine cycle so 12 x (1/12 MHz) = 1microsecond. Thats the time of 1 machine

cycle.


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FIGURE 25 Relationship between oscillator clock cycles, states, and the machine cycle


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Memory Structure

While most microprocessors implement a sharedmemory space for data and code (programs),microcontrollers has limited memory and the

program is usually stored in ROM.

In the 8051, both code and data may be internalbut they are stored in separate memories, namelythe internal ROM and RAM. Expandable to amax of 64K using external memory.

The next page shows the 8031 which has nointernal ROM.


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FIGURE 26 Summary of the 8031 memory spaces


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FIGURE 27 Summary of the 8051 on chip data memory


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Register Banks

4 Register BanksBank0, Bank1, Bank2and Bank3

Each Bank consists ofR0, R1, R2, R3,

R4, R5, R6, R7 Bank 0 is the default upon power up of the

microcontroller

Other banks can be selected byprogramming PSW register.


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General Purpose RAM

The general purpose RAM area is fromaddress 30H to 7FH. The locations from

address 20H to 2FH can also be used as

general purpose RAM although theseaddresses have very specific role given in

the next section.


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Bit-Addressable RAM

The 8051 contains 210 bit-addressablelocations of which 128 are at byte address

20H through 2FH as shown in fig 2-7.

This is the powerful feature of mostmicrocontroller because individual bits can

be set, cleared, ANDed, ORed etc. with a

single instruction instead of having to read abyte and modify


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Example

we could issue a simple instruction

SETB 67H

This would set the bit at address 67H to logic HIGH.

Bit 67H is bit 7(most significant bit) of byte location

2CHIn order to achieve the same result, a microprocessor

would need to do this:

MOV A, 2CHORL A,#10000000B

MOV 2CH,A


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Special Function Registers

Above 7FH, there is another block ofmemory 80H to 0FFH in all the version of

MCS51 uP

this 128 bytes of memory are reserved forSpecial Function Register (SFR). There are

21 SFRs. Refer to fig 2-7.


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SFRs

SFR are usually addressed by name Memory location 0F0H is given a name calledRegister B, similarly 80H is called P0.

Not all memory location has a name memory location 35H has no name

Some locations between the SFRs have no namesas well e.g. 91H. Such locations should not beused to store any data. If you do it then your datamay be lost.

Some important or commonly used SFRs will bediscussed while others will be explained when youneed to use them in your projects.


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Program Status Word (PSW)

This is a very important register because itcontains status bits which indicates the currentstate of the cpu.

PSW.7 CarrY (CY)

PSW.6 Aux Carry (AC) PSW.5 Flag 0 (F0)

PSW.4 Register Bank Select 1

PSW.3 Register Bank Select 0

PSW.2 Overflow(OV) PSW.1 reserved

PSW.0 Even Parity Flag (P)


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Commonly used SFRs

Accumulator, it has two names, A andACC. Many instruction make use of the

accumulator, eg: mov A,R0, push acc

SP, always pointing to the top of the stack,increasing by 1 before write to stack,

decreasing by 1 after read from stack


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Input/Output

(I/O) Ports In the SFR, register P0,

P1, P2, P3 are

connected to the

physical pin on the uP

P1.45

P1.56

7P1.6

8P1.7

AD3 P0.3

AD4 P0.4

AD5 P0.5

AD6 P0.6

36

35

34

33

RST9

P3.0 RXD10

11P3.1 TXD

12P3.2 INT0

AD7 P0.7

EA/VPP

ALE/PROG

PSE

N

3231

30

29

P3.3 INT113

P3.4 T014

15P3.5 T1

16

P3.6 WR

A15 P2.7

A14 P2.6

A13 P2.5

A12 P2.4

28

27

26

25

P3.7 RD17

XTAL218

19XTAL1

20VSS

A11 P2.3

A10 P2.2

A9 P2.1

A8 P2.0

24

23

22

21

P1.01

P1.12

3P1.2

4P1.3

VCC

AD0 P0.0

AD1 P0.1

AD2 P0.2

40

39

38

37

80C31

Fig 3-0 B

Pin Configuratio

PORT 0addressed by name

PO, individual pin

P0.0 to P0.7


P1, individual pin

P1.0 to P1.7


P2, individual pin

P2.0 to P2.7


P3, individual pin

P3.0 to P3.7

Some of the Port pin

serve an alternative

function


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Accessing External Code Memory

If the design involves external codememory, both P0 and P2 should not be used

as general purpose I/O since P2 is now the

Higher address bus while P0 is themultiplexed Lower address bus and the data

bus.

_____

As stated earlier, the PSEN pin must be

used. See fig 2-9


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FIGURE 28 Multiplexing the address bus (low-byte) and data bus


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FIGURE 29 Accessing external code memory


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An opcode fetch for 2-byte instruction

Fig.2-10 shows what happens during an

opcode fetch for a 2 byte instruction that

has a time of 1 machine cycle.


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FIGURE 210 Read timing for external code memory


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Accessing External RAM

For designs with external RAM, a typicalconnection is shown in fig.2-12. Note the

control lines that must be used.

MOVX instruction is used to indicate thatthe external RAM is involved.

e.g. MOVX A, @dptr ( a read operation)

e.g. MOVX @dptr, A (a write operation)


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The timing diagram for a read operation is

shown in fig 2-11.


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FIGURE 211 Timing for MOVX instruction


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FIGURE 212 Interface to 1K RAM


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Reset Operation

To reset the 8051, the RST pin must be heldhigh for at least 2 machine cycles.

This can be achieved upon powerup usingan RC network.

Fig.2-16 shows 2 circuits for achieving this,one is a manual reset, the other is a power-on reset.

How does the 2 circuit works?Try to remember capacitor is open during

steady-state.


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FIGURE 216 Two circuits for system reset. (a) Manual reset (b) Power-on reset.

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Intro to Msc51

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