Introduction - Agenda

What is PC?

What is Physical Synthesis?

1995 1998 2001 2004

0.5u 0.25u 0.13u 0.09u

Performance

Gates

Gates (millions)

18

12

6

9

15

3

450

300

150

600

Performance (MHz)

Design Sizes are Increasing Rapidly

� Continuous increase in the number of available gates

� New silicon technologies present challenges to designers and tools

� Designers continue to create larger, faster designs that are stressing current design methodologies

Deep Sub-Micron Design Challenge

1.00 0.75 0.50 0.25 0.13

3.0

2.0

1.0

0.0Microns

Delay

RC Delay

Gate Delay

As the gate delay goes down, the path is swamped by the net delays

For the same length of wire, interconnect delays ar e much longer for two reasons:

• Wires are closer together• Wires are narrower

Synthesiswith Wire Load Models

Place and Route After 1stSynthesis

(WLM)

Num

ber

of T

imin

g E

rror

s

After 1stP&R

After 2ndSynthesis(CWLM)

After 2ndP&R

After 3rdReoptimization

(SDF)

After 3rdP&R

Design Looks Okay, But,...

…after P&R, the timing is bad

Designs Are Not Getting Done on Time

Poor estimates lead to timing closure problems

Synthesis result P&R resultS

DF

SD

F

Netlist

Netlist

WLM Worst-Case Interconnect Delay

0.6 ProcessNet delay = ~1ns~10% of clock periodfor 100MHz design2-3x gate delay

0.25 ProcessNet delay = ~4.5ns~40% of clock periodfor 100MHz design20x gate delay

0.18 Process (Cupper)

Net delay = ~6.0ns~60% of clock periodfor 100MHz design40x gate delayLogical Effort Can’t tell the Story

Wireload vs. physical synthesis

1. Front-end timing (wireload based) is becoming unreliable

2. Placement can change timing dramatically:� After placement, it is obvious that nets with the same

fanout will not have the same interconnect delay

Physical View

Logical View

Placement is The Key!

Physical SynthesisDesign PhaseSynthesis Post Layout

0 %

±100 %

Timing Accuracy (% Error)

WLM

Detail Route

Interconnect ModelsPlacement

Coarse RouteTrack Assignment

� Logic Design is optimized for the current Floorplan

� With Physical Synthesis, designer “sees” more accurate physical effects

� Placement is an Important key

� “Design closure” – timing/area/congestion/power/…

� Drastically reduces iteration between logic synthesis and P&R

� Netlist handoff based on WLM timing can still cause iterations between logic synthesis and physical synthesis

Expectations from Physical Synthesis Results

Output design is a legal fully placed floorplan tha t is router ready:

� Design can be routed with no modifications

� Design is fully optimized for timing and routing co ngestion

PhysicalCompiler

RTL source( .v .vhd )

Placed Gates

Floorplan

Expectations for One Pass Timing Closure

Receiving Gates

RAM

I/O Pad Driver

� No WLM used

� Placement Based Delay

� Individual Net Load estimated

� Macro Cell Placement honored

� Layout Data considered

� Consistent Timing Model

Introduction- Agenda

What is PC?

What is Physical Synthesis?

What is Physical Compiler ?

� Placement knowledgeable synthesis and optimization tool:

� Unifies synthesis and placement

� Concurrently produces an optimized gate-level netlist AND physical cell placement from either

� RTL description

� Existing gate-level netlist

� Net delays are based on actual placement of cells, not wire loadmodels

� Resulting netlist is “router ready”

� Built on top of logic synthesis infrastructure:

� Common database, Tcl interface, constraints, timing engine, synthesis libraries

What is Physical Compiler II ?

Block-Level Designs

DesignTime

Desig

n Com

pile

r

FlexPlace PlacementSynthesis

Timing Calculation

Constraints

RTL or GATES

Logicallibrary

Physicallibrary

PhysicalConstraints

Netlist & Placement

Global Router Congestion

Analysis & Removal

PhysicalCompiler

Synthesis Data (DC)

Physical Data

Familiar Synthesis Process

.db / .ddc Tcl script

DesignCompilerPhysicalCompiler

.pdb / mw(P)DEF, .db.ddc, mw

Gate-Level Netlist

Logical Library Logical Constraints

Physical ConstraintsPhysical Library

Netlist & Placement

(Floorplan)

DesignTime

Physical Compiler - Timing engine

Block-Level Designs

Desig

n Com

pile

r

FlexPlace PlacementSynthesis

Timing Calculation

Constraints

RTL or GATES

Logicallibrary

Physicallibrary

PhysicalConstraints

Netlist & Placement

Global Router Congestion

Analysis & Removal

PhysicalCompiler

Timing Calculations

� Calculations use pin-to-pin “intelligent” Steiner Ro uting

� Each net is calculated individually

� Net Modeling is Elmore Model

� No wire load models are used

Driver

Pin-to-pin timing

Steiner Route

With On-rout flow (physopt –on_route in PCE) Astro route is considered

FlexPlace

Physical Compiler Placement engine

Block-Level Designs

DesignTime

Desig

n Com

pile

r

PlacementSynthesis

Timing Calculation

Constraints

RTL or GATES

Logicallibrary

Physicallibrary

PhysicalConstraints

Netlist & Placement

Global Router Congestion

Analysis & Removal

PhysicalCompiler

Details of FlexPlace

� Linear Wire Length Reduction:� Reduces total Manhattan wire length� 10-15% wire length reduction compared to others� Lowers the burden on the routing resources

� Global Optimization - No Partitioning!� Optimized placement without partitioning� Avoids artificially partitioned regions and placement

constraints� Flexible placement for continuous adjustments

� Direct Quality Measures:� Measures linear versus quadratic wire length for

improvement� Timing measure incorporated in its cost/objective function

Physical Compiler

Block-Level Designs

DesignTime

Desig

n Com

pile

r

PhysicalCompiler

FlexPlace PlacementSynthesis

Timing Calculation

Constraints

RTL or GATES

Logicallibrary

Physicallibrary

PhysicalConstraints

Netlist & Placement

Global Router Congestion

Analysis & Removal

Physical Compiler Flow

Load design dataLoad design data

Place & optimizePlace & optimize

Placed design

Timing & congestionok?

Timing & congestionok?

Test insertionTest insertion

Power optimizationPower optimization

Incremental optimizationIncremental optimization

No

Yes

Physical Compiler Placement+Optimization

Placed & Optimized Design

IP

Gate-Level Netlist

Floorplan

IP

PhysicalOptimization

Physical Compiler Work Flow

Logical Data

Physical Data

Physical Optimization

Analysis

Output

Logical Data

Logical Data

Physical Data

Physical Optimization

Analysis

Output

Gate-Level Netlist(s)

create_clock –period 10 ...set_input_delay –max 1.2 ...set_output_delay –max 2.5 ...set_driving_cell .........

Logical (Timing) Constraints

Logical Libraries.db

link

check_timing

Reading the Gate-Level Netlist

� Physical Compiler reads all netlist formats supported by Design Compiler

� You can read one or many files

read_milkywayread_verilogread_vhdlread_ddc…

read_verilog –netlist file1.v file2.v …

gate-level netlist

Logical Libraries

� Provide timing and functionality information for al l standard cells (and, or, flipflop, …)

� Provide timing information for hard macros (ROM, RAM, …)

� Define drive/load design rules:� Max/Min fanout

� Max/Min capacitance

� Max/Min transition

� Specified as follows:

Logical Libraries.db

set link_library "* gates.db io.db mem.db"

Search all designs in memory

Where does Physical Compiler find files?

� By default, you must specify the complete unix-path for all files

� You may specify where to look for files:

� The above paths will be used by Physical Compiler for reading or accessing files

lappend search_path ./design_data ../libs

*

Resolving References

� Gate-level netlist contains references to standard cells and macros, which are stored in the logical libraries, as well as other logic blocks

� The command link will ensure that all references can be resolved

link risc_core

nand nor inv ff

sdram_if

Gate-Level Netlist(s)

mem.db

gates.db

ip.dbpci_core

Timing Constraints

� Timing Constraints are required to communicate the design’s timing intentions to Physical Compiler

� They should be the same used for synthesis with Design Compiler (preferably SDC compatible)

create_clock –period 10 [get_ports clk]set_input_delay 4 –clock clk \

[get_ports sd_DQ[*]]set_output_delay 5 –clock clk

[get_ports sd_LD]set_load 0.2 [get_ports pdevsel_n]set_driving_cell –lib_cell buf5 \

[get_ports pdevsel_n]...

source timing_constraints.sdc

Timing Check

� Before proceeding, you need to ensure that the design is completely constrained

� Physical Compiler will not optimize paths that are not constrained for timing

� No checking for missing external loads or drive characteristics will be performed!

Completeness does not imply correctness!

check_timing

!

If check_timing reports problems

� check_timing reports all unconstrained paths

� False paths are also considered unconstrained!

� To verify that unconstrained paths are OK:

report_timing_requirements

� Reports false paths set on design

� Compare these paths to the ones reportedby check_timing

Required Physical Data

check_physical_constraints

Constrained andlinked design Physical Libraries

.pdb

Floorplan

IP

Logical Data

Physical Data

Physical Optimization

Analysis

Output

Physical Libraries

� Contain physical information on standard and macro cells necessary for placement

� Contain metal layer technology parameters: � Names

� Capacitance and resistance

� Minimum wire widths and wire-to-wire spacing

� Define placement unit tile

Physical Libraries.pdb

reference point(typically 0,0)

Dimension“bounding box”

Pins(direction, layer

and shape)

VDD

GND

A B

Y

NAND_1

Blockage

Symmetry(X, Y, or 90º) F

Abstract View

FFBUF

INV

NOR

unit tile(site)

Specifying Physical and Target Libraries

� Include only required libraries:

� Along with physical_library , you need to specify the logical library that is used for optimization:

set target_library "gates.db"

set physical_library "tech.pdb gates.pdb"

Usually same as link_library setting

without *

Technology PDB listed first

Floorplan

RAM

Site ArraysArray of placement sites

ClusterHard Boundary

Keepouts &PG nets

Port LocationsSignal I/O

Fixed CellsExample: RAM placement

read_def my_floorplan.def

Check Physical Constraints

� Checks libraries and floorplan:� Physical � Logical library inconsistencies

� Insufficient core placement area

� Warns about narrow placement regions (Chimneys)

� Reports on number of physical_only_cells, available sites and overall utilization

check_physical_constraints

Test for Understanding

1. List the 4 variables that need to be set up to successfully read all design files!

2. Which of the above variables is optional?

3. What is the difference between the link_libraryand the target_library ?

4. Physical Compiler requires a chip-level floorplan including IO PADs. True / False

Summary

Gate-Level Netlist

Logical Library.db

Logical Constraints.sdcsource

read_def

check_timingcheck_physical_constraints

read_verilog/vhdl/ddcset link_library "* sc.db"set target_library sc.db

set physical_libray sc.pdbPhysicalCompiler

Physical ConstraintsDEF

Ready for Placement

Physical Library.pdb

Recommended Setup

lappend search_path ./pdb ./db

set link_library "* sc.db io.db"

set target_library "sc.db"

set physical_library "tech.pdb sc.pdb io.pdb"

read_verilog design.v

...

All setup done first and stored in

.synopsys_dc.setup

Reads all logical and physical

libraries as well

Physical Optimization

Before starting optimization:

� Do not over-constrain the design� Constraints should match design

specification

� Report timing before optimization� Design should meet timing or be close –

check for unrealistic constraints

Logical Data

Physical Data

Physical Optimization

Analysis

Output

Placement and Optimization

� Places the design and optimizes if necessary

� Placement is performed in two steps:

physopt

1. Coarse Placement 2. Legalization

PhysOpt ‘good to knows’: Channels

� Placement can spend a lot of time placing cells close to or between macros causing problems later

RAM1 RAM2 RAM3

RAM4

RAM5

Narrow areas to the core boundary

Narrow channels between macros

Be proactive and prevent placement in such areas

Set Variables to Avoid Cells in the Channels

� Automatic keepout regions prevent placement in critical areas

� Soft and hard keepouts can be specified

RAM1 RAM2 RAM3

RAM4

RAM5

Soft keepout

Hard keepout

PhysOpt ‘good to knows’: Hierarchy

� Design hierarchy is irrelevant for placement, but affects logic optimization

� Placement ���� flat – hierarchy ignored

� Optimization ���� hierarchy applies� May impact timing optimization negatively

� Consider ungrouping design hierarchies to improve optimization

?

PhysOpt ‘good to knows’: High Fanout Nets

� By default, Physical Compiler will� not optimize clock networks (done later by CTS)

� automatically buffer all other high-fanout nets� Reset

� Enable nets

� No need to change the defaults in 90% of cases

Analysis

� Examine the last screen-output of physopt for a design summary:� Utilization

� WNS – Worst Negative Slack

� TNS – Total Negative Slack

� Legality of cell placement

� Timing of every path group (clock group)

� Cell count and area

� Design rule violations

Logical Data

Physical Data

Physical Optimization

Analysis

Output

Analysis

� Generate more detailed reports� Show all violating path end points

� report_constraint –all_violators

� Show details of the worst violating paths� report_timing –delay max (ignore hold time)

� Analyze the routing congestion� report_congestion

� Congestion map (GUI)

Output

� Apply consistent naming

� Save as Verilog

� Save the floorplan only (cell placement)

write_def –output placed.def

write –format verilog \-hierarchy –output placed.v

change_names –hierarchy –rules verilog

Logical Data

Physical Data

Physical Optimization

Analysis

Output

Example “run” Script

lappend search_path ./design_data ../libsset link_library "* gates.db mem.db"set target_library "gates.db"set physical_library "tech.pdb gates.pdb mem.pdb"

read_verilog my_design.vcurrent_design MYDESIGNlinksource my_design.sdccheck_timingread_def my_design.defcheck_physical_constraints

physopt

report_timing –delay max > my_design.timing

set mw_design_library my_design_libset mw_cel_without_fram_tech truewrite_milkyway –o placed

UNIX$ psyn_shell –xg –f run.tcl | tee myrun.log

run.tcl

Usually part of the setup

above

Basic FlowBasic Flow

Physical Compiler Methodology

Good Result?Good Result? Additional Physical Constraints

Additional Physical Constraints

Coarse PlacementCoarse Placement

CongestionOK?

CongestionOK?

Physical SynthesisPhysical Synthesis

Refine Switchesand/or FloorplanRefine Switchesand/or Floorplan

No

Yes

Good Result?Good Result?

DoneDone

No

Yes

Incremental OptimizationIncremental Optimization

No

Yes

Power Net Placement Constraint

Complete Blockagesmetal 2

met

al 1

metal 2

met

al 1

Partial Blockages

set_pnet_options –complete {metal1 metal2}set_pnet_options -partial {metal1 metal2}

Related Cells Placement Constraints

� Constrain the placement of selected cells� Move bound: location-based

� Group bound: floating-based (default)

create_bounds –coordinate {765 400 793 551} \–name SD_IF –type soft [get_cells I_SDRAM_IF/sd_mux_dq_out*]

create_bounds –name bound_name-coordinate {……}-dimension {width height}-effort low|medium|high|ultra-type soft|hardcell_list

create_placement

- effort low|medium|high

- timing_driven

- congestion

- congestion_effort low|medium|high

- num_cpus #

No optimization done

Coarse Placement

To perform a coarse placement:

!

Understanding the Congestion Calculation

Detailed routing tracks

Global routing grid

Signal routing in/out of global

routing grid

Routing crossing the grid edge produces a ‘congestion color’

Textual Congestion Report

X Y

Congestion threshold: 0.8000 0.8000

Violations (usage > threshold)

Number of edges: 13449/68354 0/68354

Maximum violation: 0.4694 0.0000

Average violation: 0.1994 0.0000

Track Usage

Maximum usage: 1.2694 0.7327

Average usage: 0.2352 0.1926

Standard deviation: 0.3903 0.2286

Histo graph for congestion on X

< 0.80: **************************************** (54905)

0.80 - 1.00: ********** (13250)

1.00 - 1.20: * (191)

1.20 - 1.40: * (8)

Histo graph for congestion on Y

< 0.80: **************************************** (68354)

The smaller the better!

report_congestion > placement_congestion.rpt

Methods to Fix Congestion

� Activate congestion-driven placement

� Lower the threshold at which the congestion optimization occurs

� Adjust cell density in congested areas

Congestion-Driven Placement Options

� Some Congestion: use medium effort congestion-driven

� Max routing congestion > 90%

� Large hot spots

� Bad Congestion: use high effort congestion-driven� Max routing congestion >> 90%

� Very large hot spots

� Congestion-driven might affect timing negatively bu t:� Postrouting numbers will not create surprises!

� Lower congestion will speed up the detailed router

Do not use congestion-driven mode on designs with no or low congestion

Do not use congestion-driven mode on designs with no or low congestion!

If Congestion Still Exists!

Consider modifying the floorplan:

� Top-level ports� Change to a different metal layer

� Spread them out or move to other sides of the block

� Macros� Add placement keepouts around your RAMs to reduce

the local congestion around RAM pins

� Move or rotate

� Block shape and size� Make it tall to add more horizontal routing resource

� Increase the block size to reduce overall congestion

Changing the Floorplan within PC

create_site_rowCreates SITEs for detailed placement

create_boundsSets X/Y_BOUNDS of CLUSTER or CELL

set_port_locationUpdates port’s XY coordinates

set_placement_areaCreates core areafor rough placement

RAM

create_wiring_keepoutcreate_placement_keepoutCreates a routing or placement keepouts

set_cell_locationSets XY location of CELL

Physical Compiler Methodology

Additional Physical Constraints

Additional Physical Constraints

Coarse PlacementCoarse Placement

CongestionOK?

CongestionOK?

Physical SynthesisPhysical Synthesis

Refine Switchesand/or FloorplanRefine Switchesand/or Floorplan

No

Yes

Good Result?Good Result?

DoneDone

No

Yes

Incremental OptimizationIncremental Optimization

Items to Check in PC Logs

Check for final legal placement summary******************************************** Check_legality: Final Statistics Information: Use -verbose option to find more about the legality violations. (PSYN-054)******************************************** Number of Cells Not on Row : 0Number of Cell Overlaps : 0Number of Cells overlapping blockages : 0Number of Orientation Violations : 0Number of Site Violations : 0Number of Power Strap Violations : 0*********************************************

Make sure all these values are Zero!

Partial Power Net Blockages

metal 2

Legalization considersall layer SPACING

rules and can also takeinto account the need

to insert VIAs.

Legalization considersall layer SPACING

rules and can also takeinto account the need

to insert VIAs.

Placement Grid

Metal2 routingconnects to Metal1pin by using M1/M2

VIA.

Metal2 routingconnects to Metal1pin by using M1/M2

VIA.

Placement is legal ifpins have enough

space to connect torouter (even if part ofthe pin is covered).

Placement is legal ifpins have enough

space to connect torouter (even if part ofthe pin is covered).

Routing Tracks

SPACING Rules

metal 2

SPACING rule applied

Placement is illegal thepin can not connect toavailable routing track.

Placement is illegal thepin can not connect toavailable routing track.

Pin placement is OKas it can connect to anavailable routing track.

Pin placement is OKas it can connect to anavailable routing track.

Placement is illegalafter considering effect

of M2 VIA insertion.

Placement is illegalafter considering effect

of M2 VIA insertion.

A B

Placement Grid

Routing Tracks

� Creates a placement keepout associated with a speci fic instance:set_keepout_margin

-type hard | soft

-outer {lx by rx ty }

{object_list}

Example: set_keepout_margin -type hard \-outer {20 5 5 15} RAM1

� List keepout areas by type and/or instance:report_keepout_margin

� Remove keepout areas by type and/or instance:remove_keepout_margin

Using Keepout Margins