INTRODUCTION - F A R A D A Yfaraday.ee.emu.edu.tr/suysal/eeng341lecturenotes.pdf · The diode is...

EENG341 ELECTRONICS I 1

INTRODUCTION SIGNAL SOURCE

A. THEVENIN FORM B. NORTON FORM

SINUSOIDAL SIGNAL

t

V(t)

Va

-Va

V(t)=Vasinwt v

Peak value=Va v

Root-Mean-Square(RMS) value=Va

2v


PEAK-TO-PEAK VALUE = 2Va V

EXPONENTIAL SIGNAL V1(t) = 5ejwt

RMS of V1(t) = 5

ELEMENTS

i. RESISTOR SYMBOL UNIT

(RESISTANCE) Ohm(Ω)

ii. CAPACITOR Farad(F)

(CAPACITANCE)

iii. INDUCTOR

L

Henry(H)

(INDUCTANCE)

DERIVATIVES

i. CONDUCTANCE

1/R

Siemens (S)

mho


MULTIPLE ELEMENTS

i. IMPEDANCE

ii. ADMITTANCE

DEVICES


CIRCUITS

A circuit is defined as one which contains a source and at least one element (or a combination

of elements) or a device (or a multiplicity of devices) which perform a specific function.

Examples:

SUBSYSTEMS


A subsytem is one which contains more than one circuit to perform a specific function.

Examples: Transmitter, Receiver

SYSTEMS

A system is one which contains more than one subsystem to perform a specific function.

Examples: Satellite T.V., Radio

Exercise: A list of items which contains electronic is given below. Identify whether they are

circuits, subsystems or systems.

Item Classification

Amplifier Circuit

Oscillator Circuit

Vending Machine

Door bell

Calculator

Alarm Clock

Camcorder

PC

EENET (EMU)


WHAT YOU CAN DO IS TO CHANGE:

A. AMPLITUDE (MAGNITUDE)

Modulation, Gain (Amplification), Attenuation,

Limiting, Clipping, Filtering

B. PHASE (ANGLE)

Modulation, Delaying, Leading, Lagging, Adding,

Subtracting

C. DIRECTION (PATH)

Feedback, Selecting, Dividing, Combining

OF A SIGNAL.

CAN YOU THINK OF ANYTHING ELSE?


DEPENDENT SOURCES (CONTROLLED SOURCES)

A dependent source is a secondary circuit whose value depends on the source (i or v) and a

parameter which is intrinsic to the circuit.

There are four types of dependent controlled sources:

(i) Voltage-Controlled Current Source (VCCS)

V1

+

-

gmV1

Intrinsic parameter

Note: The standard

diamond shape is used to

represent controlled sources.

(ii) Current-Controlled Current Source (CCCS)

βi1

Intrinsic parameter

i1


1. DIODES

The ideal diode may be considered as the most fundamental nonlinear devices.

Examples:

1 kΩ

+10v

i1

+

-

V1

1 kΩ

-10v

i2

+

-

V2

1 kΩ

+10v

i3

+

-

V3

OFF

I1=? V1=? I2=? V2=? I3=? V3=?

I3=0

ON

I1=10 Ma, V1=0

OFF

I2=0


The i-v characteristic of the ideal diode is highly nonlinear; it consists of two straight-line

segments at 90o to one another. A nonlinear curve that consists of straight-line segments is

said to be piecewise-linear.

Terminal Characteristics of Junction Diodes

V

i

Forward

1

V

i

0 0

Reverse

0.5

Breakdown

3

Compressed

scale

-VZK

2

Expanded

scale

knee=k

Silicon junction diode

The i-V curve consists of

1) The forward-biased region, determined by V>0.

2) The reverse-biased region, determined by V>0.

3) The breakdown region, determined by V>-VZK


Forward Bias

In the forward bias V is positive and i is given by

( 1)V

nVTsi I e= −

Where Is is the saturation current also known as the scale current as Is is direcly

proportional to the cross-sectional area of the diode. For “small-signal” diodes (low power

applications) Is is of the order of 10-15 A and its value doubles for every 5 oC rise in

temperature. VT is called the thermal voltage given by

T

kTV

q=

Where k=Boltzmann’s constant = 1.38x10-23 Joules/Kelvin.

T=the absolute temperature in Kelvin = 273+temperature in oC.

q= the magnitude of electronic charge = 1.602x10-19 Coulomb.

VT=25 mV at room temperature (20 oC)

1 for IC dioden

2 for discrete diode

=

For i>>Is, we have T

V

nVs si I e I= −


:

T

V

nVs

Ts

i I e

Exercise Show That

i V=nV ln( )

I

≅

For a diode voltage V1 we can evaluate the current I1:

1

1T

V

nVsI I e=

Similarly, for V2 :

2

2T

V

nVsI I e=

Combining the last two equations we obtain

2 1( )2

1

22 1

1

ln

T

V VnV

T

22 1 T

1

I e

I

or

I V V nV

I

or

I V -V =2.3nV log

I

−

=

− =


The last equation states that for a decade (factor of 10) change in current the diode voltage

drop changes by 2.3nVT, approximately 60 mV. For n=1 and 120 mV. For n=2.

A conducting diode has 0.7 V voltage drop across it; for Vd less than 0.5 V the current is

negligibly small.

Reverse Bias

The reverse-biased region of operation is entered when the diode voltage Vd is made negative.

From

4013

r

T

V 10-nV 1x25

si I e e e−= − =

Exponential term becomes negligible for Vd negative Therefore,

si I≅ −

A good part of the reverse current is due to leakage effects. The reverse current doubles for

every 5 oC rise in temperature.

Breakdown


The breakdown region is entered when the magnitude of the reverse voltage exceeds a

threshold value called the breakdown voltage.

Diode breakdown is normally not destructive provided that the power dissipated in the diode

is limited by external circuitry to a safe level. This safe value is normally specific on the

device data sheets.

Example:

A silicon diode said to be a 1 mA. Device displays a forward voltage of 0.7 V at a current of 1

mA. Evaluate the junction scaling constants would apply for a 1-A diode of the same

manufacture that conducts 1A at 0.7 V?

Solution:

T T

V V-

nV nVs si I e ==> I =ie=

For the 1-mA. Diode :

7003 1525

9

1 10 10

2 10

s

7003 50

s

n I e A

n I 10 e A

−− −

−− −

= = ≅

= = ≅

For the 1-A. Diode :

15 3 12

9 3 6

1 10 10 10

2 10 10

s

s

n I x A

n I 10 x A

− −

− −

= ≅ =

= ≅ =


Example: A diode has Is=10-17 and n=1. Calculate the diode voltage if the diode current is (a)

100 µA and (b) 10 µA. Calculate the diode current if the diode voltage is (c) 0 V

(d) -0.06 V and (e) -4 V.

Solution:

6

6

17

6

6

17

ln(1 )

25

( ) 100 10

100 101 0.025ln(1 ) 0.748

10

( ) 10 10

10 101 0.025ln(1 ) 0.691

10

, ( 1)

(

T

Ts

T

V

nVs

i V nV

I

V mV

a i x A

x V x V

b i x A

x V x V

Now i I e

c

−

−

−

−

−

−

= +

=

=

= + =

=

= + =

= −

17 0

0.0617 170.025

417 170.025

) 0

10 ( 1) 0

( ) 0.06

10 ( 1) 0.909 10

( ) 4

10 ( 1) 1.00 10

V V

i e A

d V V

i e x A

e V V

i e x A

−

−− −

−− −

== − =

= −

= − = −= −

= − = −


Analysis of Diode Circuits

Assuming VDD>0.5 V, we have

( 1)

(1)

(2)

D

T

V

nV DD s s D s

T

DD s

T

DD D D DDD

D DDD

VI I e I e since I >>I

nV

VI I e

nV

Apply KVL to the circuit,

V V V V I

R R RV V

I R R

= − =

==> = →

−= = − +

==> = − + →

We have 2 equations and 2 unknowns which can be obtained by:

A. Assumption + Circuit analysis

B. Graphical analysis

C. Iterative analysis

D. Computer circuit analysis

A. Assumption + Circuit analysis

Will be studied with same examples


B. Graphical analysis

Use i-V plane.

y mx c= +

1 DDD D

VI V

R R= − +


C. Iterative analysis

Start with an assumption: assume a value for VD. Using this VD solve for ID. Use this

value of ID to find the new diode voltage using

22 1

1

2.3 logT

IV V nV

I− =

Using this new VD solve for ID and repeat the calculations until the last calculated values

differ negligibly (or by a specific amount) from the previous values.

D. Computer Circuit-Analysis


Simplified Diode Models

1. Piecewise-linear model

2. Constant –voltage-drop (CVD) model

3. Ideal diode model

4. Small-signal model


1. Piecewise-linear model

A piecewise-linear model is substituted for the exponential i-V model.

ID

(mA)

VD (V)

Slope=1ς

Typically, rD=20Ω

VD0=0.65 V

We have ,

1) D D DD

D DDD D DD

D

i =0, V V

(V -V )2) i = , V Vr

≤

≥

≡

≡


2. The Constant-Voltage-Drop Model


3. The Ideal Diode Model

VD=0 V.

4. The Small-Signal Model

Vd(t)

VD

VD(t)

iD(t)

VD(T)

+

-

+

-

ID

ID(mA)

0 0.6 0.65 0.70

t

Id(t)

0.75 VD(V)

VD

VD0

Bias Point

Q

Vd(t)

t

Tangent at Q

Slope=1

rd


The diode is biased to operate at a point on the forward i-V characteristic and a small

ac signal is superimposed on the dc quantities. The dc voltage is VD and the ac signal is the

triangular waveform Vd(t). The diode is modeled by a resistance rd equal to the inverse of the

slope of the tangent to the i-V curve at the bias point.

In the absence of Vd(t) the diode voltage is equal to VD and the diode current is ID

given by

D

T

VnV

D sI I e=

When the signal Vd(t) is applied, the total instantaneous diode voltage VD(t) will be

given by

( )

( )

( ) ( )

( )

( )

( )

( )

( )

D

T

D d

T

dD

T T

d

T

D D d

D

V tnV

D s

V V nVD s

VV nV nVD s

V nVD D

V t V V t

and i t will be

i t I e

or

i t I e

==> i t I e e

i t I e

+

= +

=

=

=

=


1

( ) (1 )

d

T

dD D

T

VIf

nV

V i t I

nV

<<

≅ +

This is the small-signal approximation. It is valid for signals whose amplitudes are

smaller than about 10 mV (VT=25 mV).

Hence

( ) DD D d

T

Ii t I V

nV= +

( )

,

.

1

1

D D d

Dd d

T

d

Td

D

d

i t I i

where

I i V

nV

The diode small-signal resistance, r is given by

nV r

I

Q Show that

rid

= +

=

=

=Γ∂


The equation of the tangent at Q is

0

1( )D D D

D

i V Vr

= −

This equation is a model for the diode operation for small variations around the bias. The

equivalent circuit is:

Ideal

VD0

rd

iD

Apply KVL:

0D D D d

D0 D d d

D0 D d d d

D d d

V V i r

=V +(I +i )r

=(V +I r )+i r

=V +i r

= +

The signal voltage across the diode is given by


Vs=Signal voltage

VDD=dc source

ID=dc current

VD=diyote dc voltage

id=? signal current across the diode

Vd=? signal voltage across the diode

Apply KVL to the equivalent circuit:

DD s D D0 D d

D d D0 D d d

D D0 D d d d

D D d d

V +V =i R+V +i r

=(I +i )R+V +(I +i )r

=I R+(V +I r )+i (R+r )

=I R+V +i (R+r )


( ) DD s D D d d

DD D D

V V I R V i R r

Seperating dc & signal quantities on both sides for dc:

V I R V

+ = + + +

= +

The diode signal voltage is given by


Small- signal model application:

Power supply ripple

Soln:

0.7

0.93

2 2553.8

0.93

0.0538( - ) 2 2

10 0.0538

D

D 4

Td

D

dd

d

Assume V V

10-0.7Then I = mA

10Since ID is close to 1 mA, the assumption is valid.

nV xr

I

rHence V p p

R r

≅

=

= = = Ω

= =+ +

10.7 mV

The signal amplitude is 5.35 mV.

=

Example: Find the Q-point fort he diode given in the following circuit using

(a) the ideal diode model and


(b) the constant voltage drop model with Von=0.6 V

(c) Discuss the results. Which answer do you feel is most correct?

2kΩ 2kΩ

3kΩ 2kΩ

+- V

+4V

I

Solution: Using Thevenin equivalent circuits:

2kΩ

2kΩ

VTH

+

-

42// 2 1

2 22

4 22 2

TH

TH

R k

V V

= = = Ω+

= =+

and

3kΩ

2kΩ

+

-

3 2 61.2

3 2 52 8

42 3 5

TH

TH

xR k

V =1.6 V

= = = Ω+

= =+

VTH

4V

4V

Therefore,


Combining the sources:

(a) Ideal diode model: The 0.4 V source appears to be forward biasing the diode so we will

assume it is “ON”. Substituting the ideal diode model for the forward region yields.

3

0.40.182

2.2. 10I mA

x= =

This current is greater than zero, which is consistent with the diode being “ON”.Thus the Q-

point is

(0 V, +0.182 mA)


(b) CVD model:

The 0.4 V source appears to be forward biasing the diode so we will assume it is “ON”.

Substituting the CVD model with Von=0.6 V yields

3

0.4 0.690.9

2.2. 10I A

xµ−= = −

This current is negative which is not consistent with the assumption that the diode is “ON”.

Thus the diode must be “OFF”. The resulting Q-point is

(0.4 ,0 ) V mA

(c) The second estimate is more realistic. 0.4 V is not sufficient to forward bias the diode

into significant conduction. For example, let us assume that Is=10-15 A and assume that the full

0.4 V appears across the diode. Then

0.415 0.025

0 10 ( 1) 8.89i e nA−= − =


Example: Find I and V in the following circuit using

(a) ideal diode model and (b)CVD model with Von= 0.7 V.

20kΩ

+5V

V

-5V

20 kΩ

5V

5 V

I

+

-

v

Solution: (a) Diode is forward biased:

V=-5+0=-5 V

3

5 ( 5)0.5

20 10I mA

x

− −= =

Example: Find the Q-point for the diodes in the following circuit using (a) the ideal diode

model and (b) CVD model with Von=0.75 V.


Solution:

1 2 3

41 2

2

1 2

10 - (-15)0, 1.67 .

15 10

10 10 6.67

0

: (0 ,-6.67 ), : (1.67 , 0 )

D D

D D

D

I I mAx

V I V

V

D A V D mA V

= = = +

= − = −=

( ) 1 2 a D OFF, D ON:

1 2

1 2

41 2 2

1 2

( ) , :

10 -0.75 - (-15)0, 1.62 .

15 103

10 -10 -6.17 , 0.75

: (0 , - 6.17 ) , : (1.62 , 0.75 )

D D

D D D

b D OFF D ON

I I mAx

V I V V V

D A V D mA V

= = = +

= = =

Example: Find the Q-points fort he diodes in the following circuit using (a) the ideal diode

model and (b) CVD model with Von=0.6 V.

Solution: (a) D1 ON, D2 OFF, D3 ON :

ID2=0


1 3

3 33

2 1

1 3

1 2 3

1 2 3

2

1

10 01 .

(3 7) 10

0 ( 5)1 1.00

2.5 10

5- (10 -3000 ) -2

0

: (1 , 0 ), : (0 , 2 ), : (1 ,0 )

( ) , , :

0

10 - 0.6 - (

D

D D

D D

D D

D

D

I mAx

I mA ==>I mAx

V I V

V V

D mA V D mA V D mA V

b D ON D OFF D ON

I

I

== =+

− −+ = =

= == =

−

=

=3

3 33

2 1

1 2 3

-0.6)1 .

(3 7) 10

-0.6 - (-5)1 0.760 .

2.5 10

5- (10 - 0.6 -3000 ) -1.4

: (1 , .6 ), : (0 , -1.4 ), : (0.76 , 0.6 )

D D

D D

mAx

I mA I mAx

V I V

D mA O V D mA V D mA V

=+

+ = ==> =

= =


2. DIODE APPLICATIONS

Voltage Regulation

A voltage regulator is a circuit which provides a constant dc voltage between its output

terminals. The output voltage is required to remain as constant as possible in spite of

(a) Changes in the load current drawn by the regulator output terminal and

(b) Changes in the dc power-supply voltage that feeds the regulator circuit.

Since the forward voltage drop of the diode remains almost constant at ≈0.7 V while the

current through it varies by relatively large amounts, a forward-biased diode can make a

single voltage regulator.

Regulated voltages greater than 0.7 V can be obtained by connecting a number of diodes

in series.


Operation in the Breakdown Region – Zener Diodes

At a specific test current , IZT, the voltage across the Zener diode is VZ, (-IZT,-VZ) is

denoted as Q.

For a change of ∆I in current, the Zener voltage changes by ∆V:

∆V=rz ∆I

rz is the incremental resistance(also known as the dynamic resistance) at point Q.


Typically, rz is in the range of 5≈50Ω.A low value of rz is preferred because it provides a

more stable outPut voltage. Its value is high at the vicinity of the “knee”. The Zener voltage is

given by:

VZ=VZ0+rz IZ

Which is valid for IZ>IZK & VZ>VZ0.

Zener Shunt Regulator

Regulation quality is measured by: the line regulation and the load regulation.


The line regulation is defined as the change in V0 corresponding to a 1-V change in Vs,

Line regulation≡ o

s

V

V

∆∆

mV/V

The load regulation is defined as the change in V0 corresponding to a 1-V change in IL

Load Regulation0

L

V

I

∆≡∆

The output voltage is

0s zo z z

s zo z z

s zo z z

z L

V IR V I r

IR V V I r

V V I rR

I I

− − − =

= − −

− −=+

( // )zo zo s L z

z z

rRV =V + V I r R

R+r R r+ −

+


Using the output voltage and the definitions we obtain

&

-( // )

z

z

z

r Line regulation

R r

Load regulation r R

=+

=

We must ensure that the current through the Zener diode never becomes too low.

Minimim Zener current occurs when Vs is at its minimum and IL is at its maximum load

current. This can be achieved by the proper selection of the value of R. Set Vs=Vsmin Iz=Izmin

and IL=ILmax to get

min min

min max

s zo z z

z L

V V r IR

I I

− −=+

Temperature effects

The dependence of the Zener voltage Vz on temperature is specified in terms of its

temperature coefficient TC (mV/oC).


A forward conducting diode’s voltage drops by 2 mV for every 1oC.

Rectifier Circuits

2

1

120s

NV

N=

WHAT IS RECTIFIER? AC TO DC CONVERTER


The Half-Wave Rectifier


Using the piecewise-linear diode model we have

V0=0 , Vs<VD0

0 0 ,s D s D0D D

R RV V V V V

R r R r= − ≥

+ +

Using these equations we can plot the transfer characteristic; also, for many

applications rD<<R which gives

0 0-s DV V V≅

Rectifier diodes are chosen based on:

1- Current handling capability (Burn out), and

2- The peak inverse voltage(PIV)

When Vs is negative the diode will be cut off and V0 will be zero. Hence

PIV=Vs

When choosing a rectifier diode it is customary to choose one with 50% greater

breakdown voltage than the expected PIV.


Full Wave Rectifier

≅ ≅

Positive half cycles: D1 conducts, D2 cuts off

Negative half cycles: D2 conducts, D1 cuts off

To find the PIV: positive half cycles

The voltage at the cathode of D2 is V0 with peak value of Vs-VD0 and at the anode we

have –Vs with peak=Vs. Thus PIV -2Vs-VD0


PEAK INVERSE VOLTAGE (PIV)

LARGEST REVERSE VOLTAGE

HALF-WAVE

FULL-WAVE


The Bridge Rectifier (FULL-WAVE)

Positive half cycles: D1 conducts , through R, D2 conducts. D3 & D4 off. Two diodes in

series , V0 is lower than Vs by 2 diode drops.

Negative half cycles: D3 R D4

D1&D2 OFF


To determine the peak inverse voltage (PIV) of each diode, consider the circuit during

the positive half cycles. The reverse voltage across D3 can be determined from the loop

formed by D3, R and D2 as

VD3 (reverse) =V0+VD2 (forward)

The max VD3 is the PIV: We have from the output waveform, V0=Vs-2VD0

PIV=Vs-2VD0+VD0=Vs+VD0

PIV is about half the value for the full-wave rectifier with a centre-tapped transformer.

Another advantage of the bridge rectifier circuit over that utilizing a centre-tapped

transformer is that only about half as many turns are required for the secondary winding of the

transformer.

The bridge rectifier is the most popular rectifier circuit configuration.


The Peak Rectifier


Choose C such that CR>> T, where T is the period of the input sinusoid. A large CR

ensures a more constant V0.

0L

Vi

R=

D C L

IL

i i i

dV C i

dt

= +

= +

Observations

1. The diode conducts for a brief interval, ∆t near the peak of the input sinusoid and supplies

the capacitor with charge equal to that lost during the much longer discharge time which

is approximately equal to the period T.

2. Conduction begins at t1 and stops at t2; the exact value of the t2 can be determined by

setting iD=0.


0σ

3. During the diode-off interval the capacitor C discharges through R and thus V0 decays

exponentially with a time constant Cr. At the end of the discharge interval V0=Vp-Vr,

when Vr is the peak-to-peak ripple voltage.

4. When Vr is small, V0 is approximately equal to Vp. The dc component of iL is given by

0p p rL L

V V VVI i

R R R

−= = =

A more accurate expression for the output dc voltage can be obtained by taking the

average of the extreme values of V0,

0

1

2p rV V V= −

With these observations we can now find Vr, iDav and iDmax.

At the end of discharge interval we have

- 0Vp Vr V=

During the diode-off interval

0

tCR

pV V e−=

-TCR

p r p

With t=T

V -V V e≅


Since CR>>T

1T

CR

r p

r

pr

p p r

Te

CR

T V V

CR

For CR>>T V is very small Using

V V =

fCR

To find diode conduction interval t:

V cos( t )=V -V

2where =2 f=

TFor small t,

ω

ω

ω

−≅ −

≅

∆

∆

ΠΠ

∆

2

2

( )

( )

2

p p r

r

p

1 cos( t)=1- t

21

V [1- t ]=V -V2

V ==> t

V

ω ω

ω

ω

∆ ∆

∆

∆ =


To determine the average diode current during conduction, iDav, we equate the charge

that the diode supplies the capacitor,

sup CavQ i t= ∆plied

To the charge that the capacitor loses during the discharge interval,

lost rQ =CV

To obtain

Dav L

Vpi =I (1+ 2 )

VrΠ

We have assumed that p

Lav L

V i = IR =

max

(1 2 2 )

D

ID L

1

pDmax L

r

r p Dmax Dav

i can be determined by evaluating

dV i =C i

dt at t=t =- t (t=0 is at the peak)

Then,

V i I

V

For V <<V , i 2i .This means that the

wavefor

+

∆

= + Π

≅

Dm i is almost a right-angle triangle.


To obtain a full-wave peak rectifier a capacitor is connected across the load of the full-

wave rectifier circuit. In this case the period is replaced by2

T.Hence

2p

r

VV

fCR=

Q. For the full-wave peak rectifier, show that

(1 )2

&

pDav L

r

pDmax L

r

V i I V

V i =I (1+2 )2V

= + Π

Π

In the analysis of the peak rectifier circuit more accurate results can be obtained by

replacing the ideal diode by the real diode,i.e., by taking the diode voltage drop into

account.Hence, replacing Vp by Vp-VD0 & Vp-2VD0 where appropriate.

Peak rectifier in also known as a peak detector (because it detects the peak of an input

signal). They are widely used in the design of demodulators for amplitude-modulated (Am)

signals.


Limiters(Clippers)

I

For now, K 1

The input signal range is

L- L V

K K

≤

+≤ ≤



Clamped Capacitor –dc restoration

Because of the diode’s polarity, the capacitor will charge to a voltage Vc equal to the

magnitude of the most negative peak of the input signal.

The output voltage will be

0 I cV V V= +

That is, shifted upwards by Vc with lower peak clamped to 0V.


Voltage Doubler

Because the output voltage is double the input peak, the circuit is known as a voltage

doubler. The technique can be extended to provide output dc voltages that are higher

multiples of Vp.


Example: What is the maximum load current IL that can be drawn from the Zener regulator in

the following figure if it is to maintain a regulated output? What is the minimum value of RL

that can be used and still have a regulated output voltage? What is power dissipation in the

Zener diode for RL=∞?

R=15kΩ

Solution:

R=15kΩ

1.40s

s z L

L s z

z

L

30-9KVL gives : I = mA

15k

KCL gives : I =I +I

I =I -I

For voltage regulation I >0

I <1.40 mA

=Ω


0

-

-&

1 1( )

1 1(

z

z s L

s z zs L

L

s z szz z

L L

z

For voltage regulation I

I I I

V V V I I

R R

V V VV I V

R R R R R

Vs V

R R R

>

=

= =

−= − = − +

− + ) 0

1530

119

L

L

Ls

z

L

Solving for R gives

R R >

V

V

=6.43 k

For R = , Is=1.40 mA

P=9x1.40=12.6 mW

>

=−−

Ω

∞


3. Bipolar Junction Transistor - BJT

The bipolar transistor structure has n-and p-type semiconductor material. These layers

are called emitter (E), base (B) and collector (C). We have two types of BJJ:

(a) npn transistor &

(b) pnp transistor

The physical structure is given in the following figure.


Forward Characteristics

We apply a voltage to the base-emitter (VBE) junction and set VBC=0.

iC has the form of an ideal diode current:

( 1)BE

T

V

VC si I e= −

Where Is is the transistor saturation current and is proportional to the cross-sectional area of

the active base region of the transistor. Its value is between:


18 910 10

25

( 1)BE

T

s

T

B

V

VC sB

F F

A I A

V mV.

i is given by

i I i e

β β

− −≤ ≤

=

= = −

Where βF is called the forward common-emitter current gain. Its value is in the range given

below:

20 500Fβ≤ ≤

By considering the transistor as a super node we can find iE:

( )( 1)

1( )( 1) ( 1)

BE

T

BE BE

T T

E C B

V

VsE s

F

V V

V VsFE s

F F

i i i

I i I e

or

I i I e e

β

ββ α

= +

= + −

+= − = −

Where Fα is called the forward common-base current gain which has a value of


0.95 1.0

1

F

FF

F

and it is given by

α

βαβ

≤ ≤

=+

For the forward active region we can obtain the following useful relationships:

& 1)

CF C F B

B

E F B

CF C F E

E

i or i = i

i

i =( i

Also we have

i or i = i

i

β β

β

α α

=

+

=

The transistor “amplifies” its base current by the factor βF . Because the current gain

βF>>1, injection of a small current into the base of the transistor produces a much larger

current in both the collector and the emitter terminals. The collector and the emitter currents

are almost identical, because 1.Fα ≈


Reverse Characteristics

We now apply a voltage VBC to the base-collector junction and set VBE=0.

The reverse current is given by


( 1)

( 1)

BC

T

BC

T

V

VR s

E R

V

VsRB

R R

i I e

and

i i

Also

Ii i e

β β

= −

= −

= = −

Where βR is called the reverse common-emitter current gain.

βr is in the range:

0 20Rβ< ≤

iC can be found by combining iB & i E:

1(1 )( 1) ( 1)

BC BC

T T

V V

V VsC s

R R

Ii I e e

β α−= − + − = −

Where Rα is called the reverse common-base current gain:

1

0 0.95

RR

R

R

R

has values in the range

βαβ

αα

=+

< ≤


General Bias Equations

1

1

1 1

BC BCBE

T T T

BCBE BE

T T T

BCBE

T T

V VV

V V VsC s

R

VV V

V V VsE s

F

VV

V Vs sB

F R

Ii I e e e

Ii I e e e

I Ii e e

β

β

β β

= − − −

= − + −

= − + −

Example: In the following figure and npn transistor is biased by two dc voltage sources.

Find the terminal voltages and currents.

50 1F R , β β= =

Solution:


0.75 -4.75 -4.75-16 160.025 0.025 0.025

0.75 -4.75 0.75-16160.025 0.025 0.025

0.75

- 0.75 -5 -4.25

10 10 1

1.07

1010 1 1.09

50

BE BB

BC BB CC

C

E

B

V V V

V V V V

i e e e

mA

i e e e mA

i

−

−

= == = =

= − − −

=

= − + − =

=0.75 -4.75-16

160.025 0.025101 10 1 21.4

50

1.07 1.07, 50 &

0.0214 1.09

0.982

C CF F

B E

e e A

I I Also

I I

µ

β α

− − + − =

= = = = =

=

The pnp transistor

Circuit symbol for the pnp transistor is

IC

IE

iB

E

B

C

Consider the following circuit with VEB applied and VCB=0.


1

1

11 1

EB

T

EB

T

EB

T

V

VC s

V

VC sB

F F

V

VE C B s

F

i I e

i Ii e

i i i I e

β β

β

= −

= = −

= + = + −

Now, consider the following circuit with VCB applied and VEB=0


The collector-base voltage establishes the following currents:

1

1

11 1

CB

T

CB

T

CB

T

V

VE s

V

VsB

R

V

VC s

R

C E B

i I e

I i e

i I e

where i =i -i

β

β

− = −

= −

= − + −

For the general bias voltage:


1

1

1 1

CB CBEB

T T T

CBEB EB

T T T

CBEB

T T

V VV

V V VsC s

R

VV V

V V VsE s

F

VV

V Vs sB

F R

I I I e e e

I i I e e e

I I i e e

β

β

β β

= − − −

= − − −

= − + −

Note that these equations are identical to those for the npn transistor except that VEB and VCB

replace VBE and VBC, respectively.

THE OPERATING REGIONS OF THE BJT

We can have four possible regions of operation as defined below:


The i-V Characteristics of the BJT

These are for the

(a) Output characteristics

IC vs VCE

or IC vs VCB

and (b) transfer characteristics

IC vs VBE

(a) Output characteristics

Circuits for common-emitter output characteristics are given below:

The base of the transistor is driven by a constant currents source, and the output

characteristics represent a graph of iC vs VCE (npn) or iC vs VEC (pnp) with base current iB as a

parameter.


Saturation region

2.5 mA

2 mA

1.5 mA

1 mA

0.5 mA

0 mA

-1 mA

-5 V

Reverse - active

region

Forward-

region

active

100Bi Aµ=

80Bi Aµ=

60Bi Aµ=

40Bi Aµ=

20Bi Aµ=

0Bi Aµ=

CutoffSaturation

0 V 5 V 10 V

25,F R =5β β=

:

:C CE

C EC

i vs V npn

i vs V pnp

For IB=0, the transistor is non-conducting or cut off.

For CE BEV V≥ , forward active region iC is independent of VCE ( C F Bi iβ= ).

For CE BEV V≤ , saturation region of operation.

For 0BE CEV V≤ ≤ , saturation region of operation.

For CE BEV V≤ − , reverse active region ( ( 1)C R Bi iβ= − + ) Ic is independent of

VCE


For the pnp transistor, the output characteristics will appear exactly the same as the

npn except VCE is replaced by VEC.

Circuits for measuring the common-base output characteristics of the npn and pnp

transistors are shown below.

In these circuits, the emitter of the transistor is driven by a constant current source, and

the output characteristics plot ic vs VCB for the npn (or ic vs VBC fo the pnp), with the emitter

current iE as a parameter.


1Ei mA=

F Rβ =25, β =5

0.8Ei mA=

0.6Ei mA=

0.4Ei mA=

0.2Ei mA=

0Ei =

For 0CBV V≥ , operation is in the forward active region with ic independent of VCB, and

ic≅ iE.

For 0CBV V≤ , the base-collector junction becomes forward biased, and the collector

current grows exponentially (diode current)in the negative direction as the base-collector

junction begins to conduct.

For the pnp BJT, we have exactly the same characteristics except VCB becomes VBC.


(b) Transfer characteristics

For the BJT this is defined as

Ic Vs VBE

The transfer characteristic is virtually identical to that of a pn junction diode:

( 1)BE

T

V

VC si I e= −

Only a 60 mV change in VBE is required to change ic by a factor of 10.


Simplified Models

(1) Cutoff region

Both junctions are reverse-biased. We need

0BE BCV & V 0.≤ ≤

Assume that VBE<-0.1 V & VBC<-0.1 V

In cutoff npn terminal currents are:


s

F

I

β

Ei

s

R

I

β

Ci

Bi BiCi

Ei

1

1

1 1

, ,

BC BCBE

T T T

BCBE BE

T T T

BCBE

T T

V VV

V V VsC s

R

VV V

V V VsE s

F

VV

V Vs sB

F R

s sC E

R F

I i I e e e

I i I e e e

I I i e e

or

I I i = i =-

β

β

β β

β β

= − − −

= − + −

= − + −

s sB

F R

I Ii =-

β β−

(2) Forward-Active region

Emitter-base junction is forward-biased and the collector-base junction is reverse-

biased. Because of the BJT in this region can exhibit a high voltage and current gain, it is

useful for analog amplification.

For and npn:

0BE BCV & V 0≥ ≤

Further


0.1BE BCV V & V 0.1 V> < −

in Forward – Active npn terminal currents are:

1

1

1 1

BC BCBE

T T T

BCBE BE

T T T

BCBE

T T

BE

T

BE

T

V VV

V V VsC s

R

VV V

V V VsE s

F

VV

V Vs sB

F R

V

V sC s

R

V

VsE

F

I i I e e e

I i I e e e

I I i e e

I i =I e

I I i = e

β

β

β β

β

α

= − − −

= − + −

= − + −

+

+

BE

T

s

F

V

Vs s s0

F F R

I I I i e

β

β β β= − −

Neglecting the small terms, we have


BE

T

BE

T

BE

T

V

VC s

V

VsE

F

V

VsB

F

i I e

Ii e

Ii e

α

β

=

=

=

The terminal currents all have the form of diode currents and the controlling voltage is

VBE and the currents are independent of VBC.

CF C F E

E

CF C F B

B

E C B

E F B

i ==> i = i

i

i ==> i = i

i

i =i +i

==> i =(1+ )i

α α

β β

β

=

=

C F Bi iβ=C F Bi iβ=

(1 )E F Bi iβ= +

(3) Reverse-Active region


The base-collector junction is forward-biased and the base-emitter junction is reverse-biased.

In reverse-active region the terminal currents are:

1

1

1 1

BC BCBE

T T T

BCBE BE

T T T

BCBE

T T

V VV

V V VsC s

R

VV V

V V VsE s

F

VV

V Vs sB

F R

I i I e e e

I i I e e e

I I i e e

β

β

β β

= − − −

= − + −

= − + −

Neglecting the small terms, we have

ER E R B

B

i i = i

iβ β==> = − ==> −

BC

T

BC

T

BC

T

V

VsC

R

V

VE s

V

VsB

R

I i =- e

i =-I e

I i e

α

β

=

ER E R C

C

i i = i

iα α==> = ==>

E R Bi iβ− =

(1 )C R Bi iβ− = +

BC

T

V

VsI e

(1 )C R Bi iβ− = +

(4) Saturation region


Both junctions are forward-biased, and the transistor operates with a small voltage between

collector and emitter terminals. In the saturation region, the dc value of VCE is called the

saturation voltage: VCESAT (npn) or VECSAT (pnp).

To find VCESAT, we obtain the terminal currents with both junctions forward-biased:

sin , & :1

(1- )ln

1(1- )

BCBE

T T

BCBE

T T

VV

V VsC s

R

VV

V Vs sB

F R

RR BE BC

R

B R CBE T

s RF

BC

I i I e e

I I i e e

U g we obtain V V

i i V V

I

V V

α

β βαβ

αα

αβ

= −

= +

=−

+=

+

=-

ln1 1

(1- )

CB

FT

s RR F

ii

I

β

αα β

+

1(1 )1

- ln ,1

(1 )

C

CR BCESAT T B

CR F

R B

i

iiV V i

i

i

βα β

β

+ + = > − +

The simplified model for the transistor in saturation is:


The junctions are replaced with their ON voltages.

VCESAT=0.75-0.7=50 mV.

In saturation, the terminal currents are determined by the external circuit elements ; no

simplifying relationships exist between iC, iB and iE other than .C B Ei i i+ =

The Early Effect and Early Voltage

In a real transistor Ci is not entirely independent of VCE; this observed experimentally

by James Early. When the output characteristic curves are extrapolated back to the point of

zero collector current, the curves all intersect at a common point, VCE=--VA. This is called the

Early Effect and the voltage VA is called the Early voltage.


100Bi Aµ=

80 Aµ

60 Aµ

40 Aµ

20 Aµ

The Early voltage is in the range

25 150A V V V≤ ≤

Modelling the Early Effect

The dependence of iC on VCE can be included using the forward-active region:

0

0

1

1

BE

T

V

V CEC s

A

CEF F

A

s BEB

F T

Vi I e

V

V

V

I Vi

V

β β

β

= +

= +

=

Where 0Fβ represents the value of Fβ extrapolated to VC=0.


Biasing the BJT

The goal of biasing is to establish a known quiescent operating point, or Q-point.

For the npn BJT the Q-point is (IC, VCE), that is, the dc values of the collector current

and collector-emitter voltages.

For the pnp BJT the Q-point is (IC, VCE).The Q-point establishes the initial operating

region of the transistor.

We shall now illustrate the dc biasing with an example. Early voltage is assumed to be

infinite, that is, we will neglect the Early effect.

The four-resistor bias network is shown below:

16kΩ

36kΩ 22kΩ

16kΩ18kΩ

75Fβ =


R1 & R2 form a resistive voltage divider across the power supply and common (12V & 0V)

and attempt to establish a fixed voltage at the base of transistor Q1.

RE & RC are used to define the emitter current and collector-emitter voltage of the transistor.

Our goal is to find the Q-point: (IC, VCE).

Step 1: Split the power supply into two equal voltages as shown below:

18kΩ

36kΩ 22kΩ

16kΩ

Step 2: Replace the base-bias network by it’s Thevenin equivalent circuit as shown below.


1 2I I≅

12kΩ

22kΩ

16kΩ

1 1 2

1 2 1 2

&

&

4 & 12

EQ EQ

EQ CC EQ

EQ EQ

V R are given by

R R R V V R

R R R R

V V R k

= =+ +

= = Ω

Step 3: Assume a region of operation. We will assume that the transistor is operating in the

forward-active region.

KVL in loop1:

6

4 12,000 16,000

- 0.7 & (1 )

4 12,000 0.7 16,000 (1 )

75

4 - 0.72.73

1.21 10

EQ EQ B BE E E

B BE E

BE E F B

B F B

F

B

V R I V R I

I V I

For forward active region V V I I

I I

I Ax

ββ

β

µ

= + +

= + += = +

= + + +=

= =


205

(1 ) 208C F B

E F B

CE

ECE CC C C E E CC C C

F

C EE CE CC C C

F F

I I A

I I A y=mx+c

To find V , we use loop2:

R V =V -R I -R I =V -(R + )I

I R We use I = V =V (R + )I

β µβ µ

α

α α

= == + =

CE C

V =12-38,200 I =12-7,83=4,17V

All the calculated currents are positive, and

0.7 4.17 3.47BC BE CEV V V V= − = − = −

Thus, the base-collector junction is reverse-biased. This means that our assumption of

forward-active region of operation was correct.

- int (205 , 4.17 )The Q po is A Vµ

Q. Estimate the Q-point using the load line.

CE CC CC CEC C

E E EC C C

F F F

CCC CE

EC

F

V V V VI I =

R R RR R + R

V I mV

RR

α α α

α

−− = ==> −+ +

= − ++


Design Objectives for the four-resistor bias network

To explore the design objectives, we first solve for the emitter current using the

The’venin equivalent circuit:

( - )

EQ EQ B BE E E

EQ BE EQ BE

E

EQ BEEQ B EQ BE

E

V R I V R I

V V R II

R

V V for R I V V

R

= + +

− −=

−≅ <<

REQ is normally designed to be small enough to neglect the voltage drop caused by the

base current flowing through REQ. Therefore, IE is set by the combination of VEQ, VBE and RE.

Normally VEQ is designed to be large enough that small variations in the assumed values of

VBE will not affect the values of IE.

Looking at the bias network, we can see that the assumption IBREQ<<(VEQ-VBE) is equivalent

to assuming

2BI I<<

so that

1 2I I<<

The base current of Q1 does not disturb the voltage divider action of R1 & R2.

22kΩ36kΩ

18kΩ16kΩ


Using the approximate expression for IE, we have

4 0.7

20616,000EI Aµ−= =

Which is essentially the same as before.

A very large number of possible combinations of R1 & R2 will yield the desired value

of VEQ. We need to impose an additional constraint to finalize the design choice. A good

choice is to limit the power dissipated in bias resistors R1 & R2 by choosing C2

I I

5≤ .

Example: Design the following circuit to give a Q-point of (750 , )A 5Vµ using a 15V

supply with a transistor having a minimum current gain of 100.


Solution:

The Thevenin equivalent circuit is

1 1 2EQ CC EQ

1 2 1 2

where

R R R V =V & R =

R +R R +R

We assume that the voltage drop in REQ can be neglected. To find VEQ, we must

know the voltage across the emitter resistor RE. It is common to divide the remaining power

supply voltage VCC-VCE=10V equally between RE and RC.

VE=5V

and

VEQ=VBE+VE=5.7 V(neglecting IBREQ)

1 1

1 2 1 2

EQ

CC

V R R5,7 ------------(1)

V R R 15 R R= ==> =

+ +

To find R1 & R2 , we need a second equation. Because the minimum current is 100,

750CI Aµ=

7.5BI Aµ≤ C F BI Iβ=

CB

F

II

β=


We have shown that

B BESAT E

C CESAT E

BESAT CESAT

E B C

B C

B C

B C

4=12,000I +V +16,000I

12=56,000I +V +16,000I

Assume: V =0.75V +V =0.05V

Also, I =I +I

3,25=28,000I +16,000I

11,95=16,000I +72,000I

We have, I =24 A, I =160 A µ µ E

CFor F

B

& I =184 A

I F ( )

I

Q1 is in saturation

µ

β β β< <

2BI I<<

2 75I Aµ≥

Choose 2 100I Aµ=

Because 2 ,B 1 2I I I I>> ≅

2 2 1 1 2 1 2( )

15150

100

(2)

CC

CC1 2

2

1 2

V I R I R I R R

V V R +R = k

I A

R +R =150k

µ

= + ≅ +

==> = = Ω

Ω − − − − − − − − −

We now have two equations with two unknowns which give


1 57

&

2 93

R k

R k

= Ω

= Ω

Finally, the values of RC & RE are given by

5 56.67

750

5& 6.60

758

CC

EE

VR k

I A

5V V R = k

I A

µ

µ

= = = Ω

= = Ω

Example: Find the terminal currents and the region of operation for the following circuit.

12kΩ

56kΩ

16kΩ75Fβ =

Assume forward-active region:

KVL to loop1:


Since VCE is negative, the assumption of forward-active region is not valid.

Assume that Q1 is saturated:

KVL for loop1 & 2 gives

B BESAT E

C CESAT E

BESAT CESAT

E B C

B C

B C

B C

4=12,000I +V +16,000I

12=56,000I +V +16,000I

Assume: V =0.75V +V =0.05V

Also, I =I +I

3,25=28,000I +16,000I

11,95=16,000I +72,000I

We have, I =24 A, I =160 A µ µ E

CF For F

B

& I =184 A

I ( )

I

Q1 is in saturation

µ

β β β< <


BJT Modeling and Small-Signal Analysis

The hybrid-pi small-signal model for the intrinsic bipolar transistor is given below:

rπ

rπ

Where gm is the transconductance

0 0

40Cm C

T

T

C m

o

o

I g I

V

r is the input resistance

V r

I g

r is the output resistance

r

π

πβ β

= =

= =

A CE

C

Ao A

C

V V

I

V r where V =Early Voltage

I

+=

=


0β represents the small-signal common-emitter current gain.

0 mg rπβ =

The small-signal model has a voltage-controlled current source gmVbe. We can transform this

into a current-controlled current source by

be bV i rπ=

m be m b

0 b

g V g r i

= iπ

β=

This result is modeled below:

rπ0 biβ

0 0 00 0

ce cec b b b

V Vi i i for i

r rβ β β= + ≅ <<

Amplification factor

Defined by

40 ,

C A CE A CE CEAf m o

T C T T T

Af A CE A

T

I V V V V VVg r

V I V V V

VV for V V

V

µ

µ

+ += = = = +

≅ ≅ <<


T-Model

The BJT small-signal T-model is shown below:

0 biβ

Te

E

Vr

I=

m beg V


eiα

Fort he small-signal modeling to be valid we need

0.005beV V≤

Small-signal models fort he pnp transistor are identical to that of the npn.


THE BJT COMMON-EMITTER (C-E) AMPLIFIER SMALL-SIGNAL

ANALYSIS

The C-E amplifier is given below:

1kΩ

∞∞

∞10kΩ

30kΩ 4.3kΩ

1.3kΩ

100kΩ

To use the transistor as an amplifier, ac signals need to be introduced into the circuit,

but application of these ac signals must not disturb the dc Q-point that has been established by

the bias network. To do this we use ac coupling through capacitors. Their values at ac are

negligible but they provide dc blocking by behaving like open circuits at dc. C1 & C2 are,

therefore, called coupling capacitors or dc-blocking capacitors. As indicated their

values are chosen to be very large.

In many circuits, we want to force signal currents to go around elements of the bias

network. This is done by using bypass capacitors, C3 in this figure is a bypass capacitor.


Capacitor C3 provides a low impedance path for ac current from the emitter to ground,

bypassing emitter resistor RE. Thus RE, which is required for good Q-point stability, can be

effectively removed from the circuit when ac signals are considered.

dc equivalent circuit

This is used to find the Q-point of the circuit. For this analysis, we assume that

capacitors are open circuits and inductors are short circuits.

Once we have found the Q-point, we determine the response of the circuit to the ac

signals using an ac equivalent circuit. For this purpose we must use the small-signal models

that we have developed.

dc and ac equivalent circuit analysis steps

dc analysis

1. Find the dc equivalent circuit by replacing all capacitors with open circuits

and inductors by short circuits.

2. Find the Q-point using the dc equivalent circuit.

ac analysis

3. Find the ac equivalent circuit by replacing all capacitors by short circuits and

all inductors by open circuits. dc voltage sources.


Bias voltages are replaced by ground connections, and dc current sources are replaced by

open circuits in the ac equivalent circuits.

4. Replace the transistor by its small-signal model.

5. Analyses the ac characteristics of the amplifier using the small-signal ac equivalent circuit

from step 4.

6. Combine the results from step 2 and 5 to yield the total voltages and currents in the

network. This is called superposition.

Now we are in a position to analysis the C-E amplifier.

A. dc analysis of the C-E amplifier. This is done by open-circuiting all the capacitors:

30kΩ 4.3kΩ

1.3kΩ10kΩ

100

0.7F

BE

A

V V

V

β ==

= ∞

dc circuit for C-E Amplifier

The Q-point is (Ic=1.66 mA, VCE=2.68 V)


B. ac small-signal analysis of the C-E amplifier We first obtain the ac equivalent circuit by

short circuiting C1,C2 & C3 and VCC:

7.5kΩ

1kΩ

100kΩ4.3kΩ

We apply Thevenin to the left the dotted line to obtain the simplified circuit:

100kΩ4.3kΩ

880Ω

1 2& //B sBth s th B

B s B s

R RRV V R with R R R

R R R R= = =

+ +

We then replace the transistor by its small-signal model .Since the emitter terminal is

grounded we use the hybrid-pi model:


rπ

A final simplification gives:

rπ


0 3

0

0

0

0

// //

-

-

L c

Vthth

m be L

be thth

m L BV

s th B s

L B

th B s

R r R R

The voltage gain is given by

V A

V

V g V R

r V V

r R

V g r R R A

V r R R R

R R

r R R R

π

π

π

π

π

β

=

=

=

=+

= = −+ +

=+ +

1-

1

m L

th s

B

g R

R Rr

r R

ππ

=+ +

Example: Calculate the voltage gain of this C-E amplifier with 0 100β = , VA=75V & the Q-

point is(1.45, 3.86 V).

Solution:


0

1 2- , //L BV B

th B s

R RA R R R

r R R Rπ

β= =+ +

First, we calculate the the small-signal model parameters:

0

0

1 2

3 0

100 (0,025)1,72

1,45

75 3,8654,4

1,45

// 7,50 // 882

// // 3,83

100 3,83 7,50- -1301,72 0,882 7,50 1

,

( ) 20 log130

T

C

A CE

C

B th s B

L C

V

V

V r k

I

V Vr k

I

R R R k R R R

R R R r k

x A

in decibel

A db

πβ= = = Ω

+ += = = Ω

= = Ω = = Ω= = Ω

= =+ +

=42,3 dB =

C-E Input Resistance

The input resistance RIN to the C-E amplifier is defined in the following figure


1C → ∞

1kΩ

10kΩ1,3kΩ 3C → ∞

30kΩ 4,3kΩ

2C → ∞

RIN represents the total resistance presented to the signal source.

ac equivalent circuit is

30kΩ 10kΩ4,3kΩ 100kΩ

Replacing the BJT by its small-signal model gives

rπ


1 2

( // )

// // //

x x B

xIN B

x

V i R r

V R R r R R r

i

π

π π

=

= = =

C-E OUTPUT RESISTANCE

The output resistance is defined below

1C → ∞

1kΩ

10kΩ1,3kΩ 3C → ∞

30kΩ 4,3kΩ

2C → ∞

The ac equivalent circuit is obtained below (Vs is set to zero).

Replacing the BJT by its small-signal model:

rπ


0

0

0

0 , 0

0

//

:

x xx m be

c

be be bebe

s B

m be

xOUT c

x

C

OUT C

V Vi g V

R r

The base node gives

V V V V

R R r

g V

V R r R

i

For r R

R R

π

= + +

+ + = =

=

= =

>>≅


Field-Effect Transistors-FETs

We shall study the Field-effect-transistors (FETs) with their respect to their:

Structure

Linear operation

Biasing and

Small-signal modelling

Namely, we shall cover,

Metal-oxide-semiconductor FET (MOSFET)

p-channel MOS (PMOS)transistor

n-channel MOS (NMOS)transistor

And

Junction FET (JFET)

The MOS Capacitor

The behaviour of the MOS capacitor forms the basis of operation fort he MOSFET.


The metal electrode is called the

gate.

The insulating layer is formed by

silicon dioxide with thickness Tox.

The semiconductors, which can

n-type or p-type acts as the second

electrode. This is called substrate or

body.

When a large negative bias is

applied a shallow charge

sheet(holes) is formed below the

gate. This is called accumulation.

When the voltage is increased the

hole density near the surface is

reduced below the majority-carrier

level set by the substrate doping

level. The region beneath the metal

electrode is deleted of free carriers

and this is called depletion.

At some voltage level, the electron

density at the surface will exceed the

hole density; the surface has

inverted polarity from the p-type to

an n-type inversion layer. This

voltage is called the threshold-

voltage VTN.


Structure of the NMOS Transistor

The NMOS transistor is illustrated below


The n-channel MOSFET is usually called and NMOS transistor, or NMOSFET

The channel is the MOS capacitor; two heavily doped n-typed regions (n+) are called the

source (S) and drain (D).The substrate forms a fourth terminal known as the substrate

terminal or the body terminal (B). The terminal voltages are given by

GS G S

DS D S

SB S B

V V V

V V V

V V V

= −

= −

= −

These voltages are all 0≥ during normal operation of the NMOSFET.

The pn junctions formed by the source-substrate and drain substrate are kept reverse-biased

times in order to provide isolation between the junctions and the substrate as well as between

adjacent MOS transistors. Thus,

B S

B D

V V

and

V V

≤

≤

The gate length L and gate width W are measured in the direction of current and

perpendicular to the direction of current, respectively. These are important design parameters

for the NMOSFET.


Qualitative i-V behavior of the NMOSFET

We use the following illustration in which the source, drain, and body of the NMOSFET are

all grained.

For a dc gate-source voltage

VGS=VGS well below VTN, back –

to-back pn junctions exist between

the source and drain, and only a

small leakage current can flow

between these two terminals.

For VGS<VTN, a depletion region

forms in the channel and merges

with the depletion regions of the

source and drain. The depletion

region is devoid of free carriers, so

a current cannot appear between

the source and drain

When VGS>VTN, electrons flow in

from the source and drain to form

an inversion layer that connects the

n+ source region to the n+ drain

The current in the NMOSFET

always enters the drain terminal,

travels down the channel, and exits

the source terminal.


Since the gate voltage “enhances” the conductivity of the channel, this type of MOSFET is

named an enhancement-mode device.

Linear Characteristics of the NMOSFET

We have established that iG=0 & iB=0.

is=iD=iDS

We can find iDS by using the following figure

To find iDS we consider the flow of charge in the channel. The electron charge per unit length

(a line charge) at any point in the channel is given by

' " ( ) / ,ox ox TN ox TNQ WC V V C cm V V= − − ≥


Where C”ox= Єox/Tox , oxide capacitance per unit area (F/cm2)

Єox= oxide permittivity (F/cm) [Єox=3.9 Єo]

Єo= 8.854 x 10-14 F/cm

Tox=oxide thickness (cm)

The voltage Vox represents the voltage across the oxide and will be a function of position in

the channel

Vox=VGS-V(x)

Where V(x)=voltage at any point x in the channel referred to the source.

Vox must exceed VTN for an inversion layer to exist, so Q’=0 for Vox<VTN.

At the source end of the channel,

Vox=VGS

At the drain end of the channel,

Vox=VGS-VDS

The electron drift current at any point in the channel is given by the product of the charge per

unit length times the velocity Vx:

i(x)=Q’(x)Vx(x)


i(x)=[-WC”ox(Vox-VTN)][-µn Ex]

where µn is the electron mobility and

Ex is the transverse electric field in the channel

The transverse electric filed is given by

( )

x

dV xE

dx= −

The current at any point in the channel is given by

"

"

( )( ) ( ( ) )

( ) ( ( ) ) ( )

n ox GS TN

n ox GS TN

dV x i x C W V V x V

dx

or i x dx C W V V x V dV x

µ

µ

= − − −

= − − −

The voltages applied to the device terminals are V(0)=0 and V(L)VDS, we can now integrate

between O & L:

"

0 0

( ) ( ( ) ) ( )DSVL

n ox GS TNi x dx C W V V x V dV xµ= − − −∫ ∫

At any point x in the channel i(x)=-iDS

"

"

( )2

( )2

DSDS ox GS TN DS

DSDS GS TN DS

V i L C W V V V

VWor i = C ox V V V

L

µ

µ

= − −

− −


The value of µnC”ox is fixed for a given technology.

' ( )2DS

DS n GS TN DS

' "n n ox

DSDS n GS TN DS

'n n

VW i K V V V

L

where K = C

or

V i =K (V -V - )V

2

Wwhere K =K

L

µ

= − −

The parameters Kn and Kn’ are called the transconductance parameters and both have the units

of A/V2.

This iDS is for the ear region of operation and is valid for

( )

( )

GS TN

DS

DS

GS TN DS

DS

"DS o

V V x V for 0 x L

V x is maximum when x=L

V(L)=V

i is valid for

V -V V

i is sometimes written as

i = WC

− ≥ ≤ ≤

≥

DS DSx GS TN n

V V(V -V - )

2 Lµ


Linear Region i-V Characteristic

' ( )2DS

DS n GS TN DS

' "GS TN DS n n ox

VW i K V V V

L

for V -V V 0 & K = Cµ

= − −

≥ ≥

Sketch for

VTN=1 V & Kn=250 µA/V 2

A portion of the output characteristic (VSB=0)

The characteristics appear to be a family of straight lines (except for VGS=2V).

For small VDS,i.e., VDS<<VGS-VTN, we have

" ( )DS n ox GS TN DS

Wi C V V V

Lµ≅ −

iDS becomes proportional to VDS and MOSFET behaves like a resistor.

1

0'

int

1|

( )DS

DSon V

DS Q pon GS TN

iR

WV K V VL

−

→−

∂= = ∂ −


Saturation of the i-V Characteristics

We have obtained iDS for an MOSFET with VGS>>VTN and VDS=0. Now we shall study this

MOSFET with non-zero VDS as shown below:

The MOSFET is operating in the

linear region with VDS<VGS-VTN

As discussed before.

The value of VDS has increased to

VDS=VGS-VTN,

For which the channel just

disappears at the drain.

Now, we apply

VDS>VGS-VTN

The channel region has disappeared

or “pinched off” before reaching the

drain end of the channel.


We may think that iDS=0 in the MOSFET. However, this is not the case as well shall show by

the use of the following figure.

The voltage the “pinch-off point” in the channel is always equal to

( ) ( ) -GS po TN po GS TNV V x V or V x V V− = =

There is still a voltage equal to VGS-VTN across the inverted portion of the channel, and the

electrons move in the direction of x. When the electrons reach the pinch-off point, they are

injected into the depleted region between the end of the channel and the drain. The electric

field in the depleted region then sweeps the electrons on to the drain. Once the channel has

reached pinch-off, the voltage drop across the inverted channel region is constant, and the

MOSFET enters the saturation region of operation. This region is also known as the pinch-off

region.


To find iDS in this region we use

'

' 2

( )2

( )

DSDS n GS TN DS

DS GS TN

DS n GS TN DS GS TN

VW i K V V V

L

with V =V -V

W i =K V V ,V (V -V ) 0

L

= − −

− ≥ ≥

The current depends on the square of VGS-VTN but is independent of VDS.

At saturation VDS-VDSAT and is defined by

DSAT GS TNV V V= −

VDSAT is known as the saturation voltage or pinch-off voltage.

iDS can be modified as

" ( ) ( )

2GS TN GS TN

DS ox n

V V V Vi WC

Lµ− − =

GS TNV -VE field of

L−


The complete output charactersistics for an NMOSFET with

VTN=1 V & Kn=25µA/V 2

is given below:

The locus of pinch-off points is determined by

VDS=VDSAT

To the left the pinch-off locus the MOSFET is operating in the linear region.

To the right of the pinch-off locus the MOSFET is operating in the saturation region.

For VGS≤VTN=1,the transistor is cut off.


Channel-Length Modulation

When VDS increases, iDS also slightly increases when the device is in saturation. This

phenomenon is called the channel-length modulation which is explained below.

VDS>VDSAT

The channel pinches off before it makes contact with the drain.

The actual length of the resistor channel is


L=Lm-∆L

VDS increases ∆L increases and L decreases

L depends on VDS

We modify iDS to include this drain-voltage dependence as

'

2( ) (1 )nDS GS TN DS

K Wi V V V

L Lλ= − +

Where λ is called the channel-length modulation parameter. λ is dependent on the channel

length and typically is given by

1 10,001 0,1V Vλ− −≤ ≤

NMOSFET Summary for the complete i-V model

"n n ox G B

DS GS TN

DSDS n GS TN DS

WFor all regions: K = C i =0 , i =0

LCutoff region: i =0 for V V

Linear region:

V i =K (V -V - )V

2

µ

≤

2( ) (1 ) 0

GS TN DS

nDS GS TN DS DS GS TN

For V -V V 0

Saturation region:

K i = V V V for V (V -V )

2λ

≥ ≥

− + ≥ ≥


Transfer Characteristics & the Depletion-mode MOSFET

For the transfer characteristic we plot iDS vs VGS for a fixed VDS.

For the enhancement type NMOSFET the threshold voltage VTN is positive. However, it is

also possible to fabricate NMOSFETs with values of VTN≤0. These transistors are called

depletion-mode devices and has an structure as illustrated below:

An n-type channel is built-in using ion-implementation the source and drain are connected

through this resistive channel region. A negative VGS must be applied in order to deplete the

n-type channel region and quench the current path between the source and drain (hence the

name depletion-mode device).

Note that for VGS=0 IDS is

nonzero and a negative VGS is

needed to turn off this device.


PMOS Transistors

This type of MOS transistor uses p-type channel (PMOS) The qualitative behaviour of MOS

is essentially the same as that of NMOS except that the normal voltage and current polarities

reserved. The normal directions of current in the PMOS transistor are depicted in the

following figure.

A negative voltage gate relative to the source (VGS<0) or VSG>0 is required to attract holes

and create a p-type inversion layer in the channel region. In order to initiate conduction in the

enhancement-mode PMOS transistor, the gate-source voltage must be more negative than the

threshold voltage of the p-channel device, denoted by VTP. To keep the source-substrate and

drain-substrate junctions reverse-biased, VSB and VDB must also be less than zero. This

requirement is satisfied by VSD≥0 (VDS≤0).


Output Characteristics

The output characteristic for an enhancement-mode PMOS transistor is given below.

For VGS≥VTP=-1 (VSG ≤-VTP=+1) PMOS is off

PMOSFET Summary

"p p ox G B

SD SG TP GS TP

WFor all regions : K = C i =0 & i =0

LCutoff region: i =0, for V -V (V V )

Linear region:

µ

≤ ≥

2( ) (1 ) ( ) 0

SDSD p SG TP SD SG TP SD

pSD SG TP SD SD SG TP

V i =K (V +V - )V for V +V V =0

2Saturation region:

K i = V V V for V V V

2λ

≥

+ + ≥ + ≥


For the enhancement-mode PMOSFET, VTP<0

For the depletion-mode PMOSFET, VTP ≥0.

In the PMOS device, the charge carries in the channel are holes, and so current is proportional

to hole mobility µp.Hole mobility is typically only 40% of the electron mobility, so far a given

set of voltage conditions, the PMOS device will conduct on 40% of the current of the NMOS

device.

MOSFET Circuit Symbols

NMOS enhancement-mode NMOS depletion-mode Three-terminal NMOS

PMOS enhancement-mode PMOS depletion-mode Three-terminal PMOS


Biasing the MOSFET

We have found that the MOSFET operator is:

Cutoff,

Linear and

Saturation mode.

For circuit applications, we want to establish a well-defined quiescent operating points, or Q-

point, for the MOSFET in a particular mode of operations.

The Q-point for the MOSFET is represented by the dc values (IDS,VDS) that locate the

operating point on the MOSFET output characteristics.

For hand analysis and design of Q-points, we usually set λ=0.

Consider the following biasing circuit for the NMOSFET.

70kΩ

30kΩ

100kΩ

225 /nK A Vµ=

1TNV V=


A dc voltage source VGG is used to establish a fixed gate-source bias fort he MOSFET, and

source VDD supplies drain current to the NMOSFET through resistor RL.

We simplify the gate bias network by applying The’venin equivalent circuit:

100kΩ

1

1 2

211 2EQ GG EQ

1 2

EQ G EQ GS

DD DS L DS

G

GS EQ

R R RV V & R = k

R R R +R

=3V

KVL gives

V =I R +V

V =I R +V

I =0

V =V =3V

= = Ω+

To find the Q-point, we must assume a mode of operation. Assume that the MOSFET is

saturated.


62 225 10

( ) (3 1) 502 2

nDS GS TN

K xI V V Aµ

−

= − = − =

And

DS DD DS L

-6 5

GS TN

V V I R

=10-50x10 x10 =5V

Check:

V -V =2

= −

VDS exceeds (VGS-VTN) so that the MOSFET is saturated.

Q-point is (50µA,5V) with VGS=3 V.

Example: Electronic current source-current sink

Let VGS=3 V


If V DD≥VGS-VTN=3-1=2 V, then the output current will be constant at 50µA.

Q. A current source with IDC=25µA is indeed, and an NMOSFET is available with

Kn=25 µA/V 2 and VTN=1V. What is the required value of VGS? What is the minimum value of

VDS needed for current source behavior?

[Ans: 2.41V, 1.41 V]

The fixed gate-source bias theoretically works fine but in practice VTN & Kn values are not

exactly known. Also, ambient conditions may affect component values. Therefore, in order to

have a stable Q-point we use four-resistor bias circuit as shown below:

225 /nK A Vµ=

2 150R k= Ω 75DR k= Ω

1 100R k= Ω39sR k= Ω

1TNV V=

The simplified equivalent circuit is obtained by applying The’venin to the gate:


75DR k= Ω

60

4EQ

EQ

R k

V V

= Ω

=

KVL gives the loop equations


2

( )

( )

0

( )

EQ G EQ GS G DS s

DD DS D D S G DS s

G

EQ GS DS s

DD DS D s D S

nDS G S TN

EQ

V I R V I I R

V I R V I I R

But I

V =V + I R

V = I (R +R )V

Assum e saturation:

K I = V V

2Put in V :

= + + +

= + + +

=

−

2

2

( )

1

( 1)2

n sEQ GS GS TN

-6 2TN n

-6 4

GS GS

2GS G S

GS

K R V =V + V V

2

V & K =25x10 A /V

25x10 x3.9x10 4=V + V

Sim plifying w e have

V +0.05V -7.21=0

V = 2.66V

−

=

−

±

For VGS=-2,66 V MOSFET is cutoff (VGS<VTN)


VGS=2,66 V

62

6 3 3

25 10(2,66 1) 34,4

2

10 34,4 10 (75 10 39 10 )

6,08

DS

DS

DS

DS GS TN

DS GS TN

GS

xI A

x x x V

V V

We have

V =6,08 V, V -V =1,66 V

V (V -V )

Q-point: (34.4, 6.08 V) with V =2.66 V

µ−

−

= − =

= + +→ =

≥

Example: Design a four-resistor bias network with VDD=10 V, VTN=1 V, Kn=25 µA/V 2 for a

Q-point of (100 µA,6V)

Solution:


6

( )

10 640

100 10

DD DS DS D s

DD DSD s

DS

s

EQ GS DS s

EQ GSs

DS

V V I R R

V -V R +R = k

I x

But R can be obtained using

V =V +I R

V -V ==>R =

I

We need to fin

−

− = +−= = Ω

GS

2nDS GS TN

DSGS TN

n

s -6

d V first.

KUsing I = (V -V )

2

2I 2x100 ==> V =V + =1+

K 25

=3,83 V

4-3,83 R = =1,7k

100x10Ω

With this value of Rs , Vs is only 0.17 V which is small. Therefore, we increase VEQ 4 to 6 V.

6

6 3,8321,7

100 10&

s

D

R kx

R =40-21,7=18,3k

−

−= = Ω

Ω

For VEQ=6V & REQ=60kΩ


We have R1=150 kΩ & R2=100 kΩ

Example: For the depletion mode MOSFET shown below, find the value of Rs required to

achieve IDS=100µA.

Solution: We must determine the value of VGS needed to establish the design value of IDS.

Assume saturation mode:

6

6

6

2 2 100 103 2

200 10

0,

-

2- 20

100 10

DSGS TN

n

G

GS DS s

GSs

DS

I x x V V V

K x

Since I the loop equation gives

V I R

V R k

I x

−

−

−

= + = − + = −

=

=−==> = = − = Ω

Check:


10 2 8

2 ( 3) 1DS DO s

GS TN

V V V V

V V

= − = − =− = − − − = +

Because VDS>(VGS-VTN) , saturation-mode assumption was correct, and Rs=20kΩ will set the

Q-point to

(100µA,8 V) with VGS=-2 V.

Example: Electronic voltage source.

This is illustrated using an n-channel depletion-mode MOSFET. The goal for the MOSFET is

to supply a constant output voltage even through the load current iL may change. We need to

calculate the output voltage VL and then the output resistance for the circuit.


Solution: We first simplify the circuit using a Thevenin transformation of the gate-bias

network.

KVL to the input loop gives (iG=0):

3

5 73,000

01,6 10

G GS L

L GS

DS L

DSGS TN

n

-2

i V V

V =5-V

i =i =20mA

Assume saturation mode:

2I V =V +

K

2(2x10 ) =-5+ V

x

−

= + +==>

=

L V =5V


Check:

5

12 5 7

- mod

GS TN

DS

DS GS TN

V V V

V V

V V V saturation e

− = += − => − ==>

Thus, for a load current of 20 mA, this circuit produces and output voltage of 5 V.

Now let us investigate the behavior of the circuit for small changes in iL. The output

resistance of this circuit can be defined as

int|Lo Q po

L

VR

i −∂=∂

in t

25 5

( )

)1 2 1|

2 2

125

DSL GS TN

n

L DS

GS TNo Q po

n DS DS

iV V V

K

i i

(V -VR

K i I

1 5 =

2 0,02

The final circuit is given below:

−

= − = − −

=

= =

= Ω


The value of Ro is valid only for small changes in circuit near the Q-point. Ro is called

the small-signal output resistance of this circuit.

Note that VEQ=7,5 V, not 5 V, in order to account fort he voltage drop across Ro so

that VL=5 V when iL=20mA.

Example: Find the Q-point fort he PMOS device which is biased using two resistors and a

voltage source.


The loop equations VSD & VSG give:

5

6

-65 2

12 10

10

0, .

mod :

100 1012-10 ( -2)

2

3.32 , 0.

SD SD

SG SD G

G SD SG

SG SG

SG

V I

V V I

I V V

Assume saturation e

x V V

V V

= −

= −= =

=

==> = 58

-2 , 0.58

3.32

87.1 & 3.29

TP SG

SG

SD SD

V

Since V V V V is not sufficient to turn on

the PMOSFET

V V

I A V Vµ

= =

=

= =

We see that VSD≈VSG. Also, VSG+VTP=1.29 V and VSD>VSG+VTP, so PMOSFET is saturated.

Q-point: (87.1µA, 3.29 V)

For VGS=VDS (or VSG=VSD), an enhancement-type device will always be in saturation.


Example: Find the Q-point for the PMOSFET in the following circuit.

Solution:

[ ]2

4 1600

4 ( 1) 1.132

&

SG

SD SD

-6

SD

SD

SG

V =4 V

Output loop equation gives

V I

Assume saturation-mode:

250x10 I = mA

V =2.19 V

Check:

V

− =

+ − =

[ ]

TP

SG TP SD

+V =4+(-1)=3V

V +V >V

3 V>2.19

assumption of saturation-mode is incorrect.


Assume linear-mode:

6

2

1

2

1

4 1600 ( )2

4 1600 250 10 4 12

-11 20 0

8.7

2.3

8.7

SDSD p SG TP SD

SDSD SD

SD SD

SD

SD

SD

V V K V V V

V V x x V

V V

V V

V V

V V is not pos

−

− = + −

==> − = − −

==> + =

==

=

-6

2.3

2.3250 10 4 -1- 2.3

2

1.06

:

4 -1 3 &

SD

SD

SG TP SG TP SD

sible

V V

and I x

mA

Check

V V V V V V

=

=

=

+ = = + >

Thus, the PMOSFET is operating in the linear-mode at the Q-point (1.06 mA, 2.3 V ).


The Junction FET(JFET)

JFET can be found without the need for an insulating oxide by using pn junction as

shown below. It consists of a block of semiconductor material (n-type, or p-type) and two pn

junctions that from the gate.

In the n-channel JFET current enters the channel at the drain and exits from the source.

An applied voltage to the gate changes the width of the channel and thus, the resistance

becomes dependent on this voltage. This voltage-controlled resistance is given by

CH

LR

t W

ρ=

Where p=resistivity channel region; L=channel length

W=channel width and t=depth of the channel diodes

Application of a reverse bias to the gate-channel diodes will cause the depletion layers to

widen, reducing W and decreasing current. Thus, the JFET is inherently a depletion-mode

devide, a voltage must be applied to the gate to turn off the device.


The JFET Bias Applied

VGS is now negative and the

depletion layers have increased

in width, increasing the channel

resistance. W’<W. Because G-S

junction is reverse –biased ,iG=IS

and we can assume iG≈0.

When we apply more negative VGS

the conducting channel disappears.

The channel becomes pinched-off

and pn junctions merge at the centre

of the channel. VGS=Vp

CHR → ∞

VGS must not exceed the zener

breakdown voltage.


JFET with Drain-Source Bias (VDS)

VGS is fixed for all cases.

For small values of VDS, the

resistive channel connects

drain and source, and JFET is

linear mode.

For larger values of VDS, the

depletion layer widens at the

drain and until the channel

pinches-off near the drain. At

pinch-off, we have

VGS-VDSP=Vp

VDSP=VGS-Vp

Once the JFET channel pinches

off, the drain current saturates.

Electrons are injected into the

depletion region and swept on

to the drain by the field. For an

even larger value of VDS the

pinch-off point moves to the

source and JFET suffers from

channel-length modulation.


n-Channel JFET i-V Characteristics

The JFET is structurally different from MOSFET but the i-V characteristics are virtually

identical. For the JFET VTN is replaced by Vp.

For the saturation mode we have

2

2 2

2

( )2

( ) (1 )2

(1 )

2

nDS GS p

n GSp

p

GSDS DSS

p

2n DSSDSS n 2

p

K i V V

K V V

V

or

V i =I

V

where

K 2I I = Vp or K =

Vp

Typically , we have

-25 V 0 V

= −

= − −

−

≤ ≤

100-5DSS and 10 I A≤ ≤

With channel-length modulation Ids in pinch-off (saturation) becomes

2GSDS DSS DS

p

DS GS p

V i =I (1- ) (1+ V )

V

for V V -V 0

λ

≥ ≥


For the linear mode of the JFET we have

2

2( )

2DSS DS

DS GS p DS

GS p DS GS p

I V i V V V

Vp

for V V & V V -V

= − −

≥ ≤

Transfer Characteristic

The transfer characteristic for a JFET operating in pinch-off is shown below:

IDSS is the current in the JFET for VGS=0 and represents the maximum current in the device

under normal operating conditions because the gate diode should be kept reverse-biased, with

VGS.


Output Characteristics

The overall output characteristics for an n-channel JFET with λ=0 are given below:

The drain current decreases from a maximum of IDSS toward zero as VGS ranges from zero to

Vp.


Circuit Symbols

The arrow identifies the polarity of the gate-channel diode. Source and drain are

determined by the voltages in the circuit in which the JFET is used. However, the arrow that

indicates the gate-channel junction is often to indicate the preferred source terminal of the

device.

JFET Summary

n-channel JFET

iG=0 for VGS≤0 (Vp<0)

Cutoff mode: iDS=0 for VGS≤Vp

Linear mode:

2

2( )

2

- 0

DSS DSDS GS p DS

GS p DS

I Vi V V V

Vp

for V V V

= − −

≥ ≥


Saturation mode:

2

mod

(1 ) (1 )

- 0

0 0 ( 0)

mod :

GSDS DSS DS

p

DS GS p

G SG p

saturation e

V i I V

V

for V V V

p channel JFET

i for V V

Cutoff e

λ= − +

≥ ≥

−≈ ≤ >

2

0

mod :

2( )

2 2

0

mod :

(1 ) (1 )

SD SG p

SD

SGSD DSS SD

p

i for V V

Linear e

IDSS VSD i VSG Vp VSD

Vp

for VSG Vp VSD

saturation e

V i I V

V

λ

= >

= + −

+ ≥ ≥

= + +

0SD SG p for V V V≥ + ≥


Small-Signal MODELS for FETs

The hybrid-pi small-signal model for the MOSFET is given below:

ro

id

+

-

Vgs

gmVgs

S

D

Vds

G

Where gm is the transconductance

int

2int

| ( )(1 )

2

2tan

1| ( )

2

DSQ po n GS TN DS

GS

DSID

GS TNGS TN

DS nQ po GS TN

o DS

igm K V V V

V

I

V VV V

ro is the output resis ce

i K V V

r V

I

λ

λ

λ

∂= = − +∂

= = −−

∂= = −∂

=11

1

D D

DSDS

DS

oDS

f m o

I

V V

V r

I

Also

g r

λλ

λ

µ

=+ +

+=

=


T-Model

The MOSFET small-signal T-model is shown below:

Definition of Small-Signal Operation for the MOSFET

The limits of linear operation of the MOSFET can be explored using the simplified iDS with

λ=0:

2

2

2 2

( ) -2

sin

&

-2

( ) 2 ( )2

nDS GS TN DS GS TN

GS GS gs DS DS ds

nDS GS gs TN

nDS ds GS TN gs GS TN gs

K i V V for V V V

U g

V V V i I i

we have

K i V V V

or

K I i V V V V V V

But

= − ≥

= + = +

= +

+ = − + − +

2( )2

nDS GS TN

K I V V= −


22 ( )nds gs GS TN gs

K i = V V V V

2 − +

For this equation to be considered linear ids must be directly proportional to Vgs, which is

achieved for

2 2 ( )gs gs GS TNV V V V<< −

Simplifying, we find that for small-signal operation of the MOSFET requires

2( )

0.2( )

gs GS TN

gs GS TN

V V V

or

V V V

<< −

= −

A factor of 10 satisfies the inequality.

Because the MOSFET can easily be biased with (VGS-VTN) equal to several volts,

we see that it can handle much larger values of Vgs then the values of Vbe corresponding to

the BJT. This is another fundamental difference between the MOSFET and BJT and can be

very important in circuit design, particularly in RF amplifier design for example.

Small-signal models for the PMOS & JFET are identical to that of the NMOS.


The Common-Source Amplifier

Now we can analyse the small-signal characteristics of the common-source (C-S) amplifier

shown below, which uses an enhancement-mode n-channel MOSFET in a four-resistor bias

network.

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