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8/12/2019 Introduction to CMOS VLSI Design_lect17
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Introduction toCMOS VLSI
Design
Lecture 17:Design for Testability
David Harris
Harvey Mudd College
Spring 2004
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17: Design for Testability Slide 2CMOS VLSI Design
Outlineq Testing
Logic Verification Silicon Debug
Manufacturing Testq Fault Modelsq Observability and Controllabilityq Design for Test
Scan BIST
q Boundary Scan
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17: Design for Testability Slide 3CMOS VLSI Design
Testingq Testing is one of the most expensive parts of chips
Logic verification accounts for > 50% of designeffort for many chips
Debug time after fabrication has enormousopportunity cost
Shipping defective parts can sink a company
qExample: Intel FDIV bug Logic error not caught until > 1M units shipped Recall cost $450M (!!!)
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17: Design for Testability Slide 4CMOS VLSI Design
Logic Verificationq Does the chip simulate correctly?
Usually done at HDL level Verification engineers write test bench for HDL
Cant test all cases Look for corner cases Try to break logic design
q Ex: 32-bit adder
Test all combinations of corner cases as inputs: 0, 1, 2, 2 31-1, -1, -2 31, a few random numbers
q Good tests require ingenuity
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17: Design for Testability Slide 5CMOS VLSI Design
Silicon Debugq Test the first chips back from fabrication
If you are lucky, they work the first time If not
q Logic bugs vs. electrical failures
Most chip failures are logic bugs from inadequatesimulation
Some are electrical failures Crosstalk Dynamic nodes: leakage, charge sharing Ratio failures
A few are tool or methodology failures (e.g. DRC)q Fix the bugs and fabricate a corrected chip
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17: Design for Testability Slide 6CMOS VLSI Design
Shmoo Plotsq How to diagnose failures?
Hard to access chips Picoprobes
Electron beam Laser voltage probing Built-in self-test
q Shmoo plots
Vary voltage, frequency Look for cause of
electrical failures
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17: Design for Testability Slide 7CMOS VLSI Design
Shmoo Plotsq How to diagnose failures?
Hard to access chips Picoprobes
Electron beam Laser voltage probing Built-in self-test
q Shmoo plots
Vary voltage, frequency Look for cause of
electrical failures
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17: Design for Testability Slide 8CMOS VLSI Design
Manufacturing Testq A speck of dust on a wafer is sufficient to kill chipq Yield of any chip is < 100%
Must test chips after manufacturing beforedelivery to customers to only ship good parts
q Manufacturing testers arevery expensive Minimize time on tester
Careful selection oftest vectors
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17: Design for Testability Slide 9CMOS VLSI Design
Testing Your Chipsq If you dont have a multimillion dollar tester:
Build a breadboard with LEDs and switches Hook up a logic analyzer and pattern generator
Or use a low-cost functional chip tester
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17: Design for Testability Slide 10CMOS VLSI Design
TestosterICsq Ex: TestosterICs functional chip tester
Designed by clinic teams and David Diaz at HMC Reads your IRSIM test vectors, applies them to
your chip, and reports assertion failures
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17: Design for Testability Slide 11CMOS VLSI Design
Stuck-At Faultsq How does a chip fail?
Usually failures are shorts between twoconductors or opens in a conductor
This can cause very complicated behavior q A simpler model: Stuck-At
Assume all failures cause nodes to be stuck-at0 or 1, i.e. shorted to GND or V DD
Not quite true, but works well in practice
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17: Design for Testability Slide 12CMOS VLSI Design
Examples
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17: Design for Testability Slide 13CMOS VLSI Design
Observability & Controllability
q Observability : ease of observing a node by watchingexternal output pins of the chip
q Controllability : ease of forcing a node to 0 or 1 bydriving input pins of the chip
q Combinational logic is usually easy to observe andcontrol
q Finite state machines can be very difficult, requiringmany cycles to enter desired state Especially if state transition diagram is not known
to the test engineer
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17: Design for Testability Slide 14CMOS VLSI Design
Test Pattern Generationq Manufacturing test ideally would check every node
in the circuit to prove it is not stuck.q Apply the smallest sequence of test vectors
necessary to prove each node is not stuck.
q Good observability and controllability reducesnumber of test vectors required for manufacturingtest. Reduces the cost of testing Motivates design-for-test
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17: Design for Testability Slide 15CMOS VLSI Design
Test ExampleSA1 SA0
q A3q A2q A1q A0q n1q n2q n3q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 16CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2q A1q A0q n1q n2q n3q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 17CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2 {1010} {1110}q A1q A0q n1q n2q n3q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 18CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2 {1010} {1110}q A1 {0100} {0110}q A0q n1q n2q n3q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 19CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2 {1010} {1110}q A1 {0100} {0110}q A0 {0110} {0111}q n1q n2q n3q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 20CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2 {1010} {1110}q A1 {0100} {0110}q A0 {0110} {0111}q n1 {1110} {0110}q n2q n3q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 21CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2 {1010} {1110}q A1 {0100} {0110}q A0 {0110} {0111}q n1 {1110} {0110}q n2 {0110} {0100}q n3q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 22CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2 {1010} {1110}q A1 {0100} {0110}q A0 {0110} {0111}q n1 {1110} {0110}q n2 {0110} {0100}q n3 {0101} {0110}q Y
q Minimum set:
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 23CMOS VLSI Design
Test ExampleSA1 SA0
q A3 {0110} {1110}q A2 {1010} {1110}q A1 {0100} {0110}q A0 {0110} {0111}q n1 {1110} {0110}q n2 {0110} {0100}q n3 {0101} {0110}q Y {0110} {1110}
q Minimum set: {0100, 0101, 0110, 0111, 1010, 1110}
A3 A2
A1 A0
Y
n1
n2 n3
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17: Design for Testability Slide 24CMOS VLSI Design
Design for Testq Design the chip to increase observability and
controllability
q If each register could be observed and controlled,test problem reduces to testing combinational logicbetween registers.
q Better yet, logic blocks could enter test mode wherethey generate test patterns and report the resultsautomatically.
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17: Design for Testability Slide 25CMOS VLSI Design
Scanq Convert each flip-flop to a scan register
Only costs one extra multiplexer q Normal mode: flip-flops behave as usualq Scan mode: flip-flops behave as shift register
q Contents of flopscan be scanned
out and newvalues scannedin
F l o p
QD
CLK
SI
SCAN
scan out
scan-in
inputs outputs
F l o p
F l o p
F l o p
F l o p
F l o p
F l o p
F l o p
F l o p
F l o p
F l o p
F l o p
F l o p
LogicCloud
LogicCloud
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17: Design for Testability Slide 26CMOS VLSI Design
Scannable Flip-flops
0
1 F l o p
CLK
D
SI
SCAN
Q
D
X
Q
Q
(a)
(b)
SCAN
SI
D
X
Q
Q
SI
s
s
(c)
d
d
d
s
SCAN
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17: Design for Testability Slide 27CMOS VLSI Design
Built-in Self-testq Built-in self-test lets blocks test themselves
Generate pseudo-random inputs to comb. logic Combine outputs into a syndrome With high probability, block is fault-free if it
produces the expected syndrome
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17: Design for Testability Slide 28CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
7
6
54
3
2
1
1110
QStep
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17: Design for Testability Slide 29CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
7
6
54
3
2
1101
1110
QStep
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17: Design for Testability Slide 30CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
7
6
54
3
1012
1101
1110
QStep
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17: Design for Testability Slide 31CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
7
6
54
0103
1012
1101
1110
QStep
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17: Design for Testability Slide 32CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
7
6
51004
0103
1012
1101
1110
QStep
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17: Design for Testability Slide 33CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
7
6
00151004
0103
1012
1101
1110
QStep
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17: Design for Testability Slide 34CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
7
0116
00151004
0103
1012
1101
1110
QStep
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17: Design for Testability Slide 35CMOS VLSI Design
PRSGq Linear Feedback Shift Register
Shift register with input taken from XOR of state Pseudo-Random Sequence Generator
F l o p
F l o p
F l o pQ[0] Q[1] Q[2]
CLK
D D D
111 (repeats)7
0116
00151004
0103
1012
1101
1110
QStep
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17: Design for Testability Slide 36CMOS VLSI Design
BILBOq Built-in Logic Block Observer
Combine scan with PRSG & signature analysis
MODE C[1] C[0]Scan 0 0Test 0 1Reset 1 0Normal 1 1
F l o p
F l o p
F l o p
1
0
D[0] D[1] D[2]
Q[0]Q[1]
Q[2] / SOSI
C[1]C[0]
PRSGLogicCloud
Signature Analyzer
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17: Design for Testability Slide 37CMOS VLSI Design
Boundary Scanq Testing boards is also difficult
Need to verify solder joints are good Drive a pin to 0, then to 1 Check that all connected pins get the values
q Through-hold boards used bed of nailsq SMT and BGA boards cannot easily contact pinsq Build capability of observing and controlling pins into
each chip to make board test easier
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17: Design for Testability Slide 39CMOS VLSI Design
Boundary Scan Interfaceq Boundary scan is accessed through five pins
TCK: test clock TMS: test mode select TDI: test data in TDO: test data out TRST*: test reset (optional)
q Chips with internal scan chains can access thechains through boundary scan for unified teststrategy.
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Summaryq Think about testing from the beginning
Simulate as you go Plan for test after fabrication
q If you dont test it, it wont work! (Guaranteed)
