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Design for Testability

By, Nikunj Vadodaria.

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Agenda

DFT

Types of DFT

Fault Models

DFT Scan Insertion Flow

Conclusion

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DFT DFT(aka "Design for Testability") is a nothing but changing a given circu

overall difficulty of testing.

Changing refers to the addition of new logic or modification of existing circuit.

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Objective

Controllability Observability

Ability to establish specific

signal value at each node

in circuit by setting values

at circuit inputs

Ability to determine

signal values at any node

in the circuit by controlling

the signal input and observing

the output

Modes of Operations

Test Mode N

Configured only

for testing purpose

Circ

samorig

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Types of DFT

Scan Insertion

BIST (Built

In Self Test) Memory BIST Insertion

Logical BIST Insertion

Boundary Scan Insertion

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Scan insertion

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Normal F/F

Muxed F/F

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2 types of At-Speed Testing

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Path Delay Testing Transition Delay

Scan operation for delay test is similar to stuck-at test.

Main difference is delay test requires 2 inputs instead of one input.

First is always scanned in vector

Second input can be generated in 2 different ways.

Broad Side

Launch off shift

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Transition delay Fault methodolo

Transition delay testing is used to test as many paths as possible at spee

inserts transition faults for all cell inputs in the chip, and determines wh

for launch points and capture points. From the user's perspective, the

generate these scan vectors is very similar to generating scan vectors for s

Transition delay vectors do not replace stuck at fault vectors, but they

number of required stuck at fault scan vectors. This is done by generating

vectors first and then generating stuck-at vectors for faults that were misdelay vectors.

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Types of Transition Tests

Launch Off Shift Broad Side

Last Shift of the scan cycle load

also serves as the transition launch event

Critical Time Time from last clock cycle to capture clock

Entire scan data shifting ca

speed in test mode

2 at-speed clocks are pulseand capture in functional m

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Path delay Fault methodology

Path delay testing is used to test known critical paths at-speed. For path delay test

generates a pattern which, when scanned into a chain, sensitizes the path of interes

value to be sent through the path. Many of the gates in the path will have several inp

the one that is part of the path and the scan vector must also control those inputs.

Sensitizing the path means that those additional inputs will be driven to values that

from the launching scan flop to propagate to the capture scan flop. After the pattern is

must generate two or more capture clocks whose period matches the operating freq

chain is scanned. The test passes if the capture flop captured the correct values.

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Built in Self Test

Memory BIST

Logical BIST

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I/P Pattern Circuit under Yield O/P Respo

Golden Response Comparator

d S

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Boundary Scan

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Fault Models

Common Fault Models

Stuck at faults

Single / Multiple Stuckat faults

Transistor Faults

Open / Short

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Stuck At Faults

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Transistor Faults

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Used to reduce no. of Single Stuc

to be considered

Fault Equivalence and

Only 1 line is faulty at a time.

Fault is not of intermediate nature

Fault can occur at the input or outp

Mechanism to find 2 faults whose affect on the circuit a

Results into Fault Collapsing

F lt E i l d F lt C ll i

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Fault Equivalence and Fault Collapsin

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F l E i l E l

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Fault D

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Fault Equivalence Example

T t tt G ti

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Test pattern Generation

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S f F lt Si l ti

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Summary of Fault Simulation

Fault Simulation is used to verify the quality of the given test vector.

To know what fault is getting detected and visa versa.

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Test Generation

Given Circuit netlist

Fault Set

Reduced Fault set -- Collapsed

Helps us to get the set of test vectors required to detect faults in the set

Gives the list of undetected faults

DFT Top Down Scan Insertion Flow

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DFT Top Down Scan Insertion Flow

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Summary

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Summary

DFT techniques are essential to an efficient and successful testi

manufactured device.

By implementing DFT features early in the design cycle, full te

coverage on the design may be achieved, thereby reducing the

time normally spent at the tester after the device is fabricated.

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Thank You

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