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Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to...

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Introduction to Digital VLSI Design מבוא לתכנוןVLSI ספרתיFloor Planing Lecturer: Gil Rahav Semester B’ , EE Dept. BGU. Freescale Semiconductors Israel
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Page 1: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

Introduction to Digital VLSI Design

ספרתיVLSIמבוא לתכנון

Floor Planing

Lecturer: Gil RahavSemester B’ , EE Dept. BGU.Freescale Semiconductors Israel

Page 2: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

24.01.2007Introduction to Digital VLSIGil Rahav

Wire Bond

Page 3: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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Wire Bond (Cont.)

Page 4: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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C4 Bumps

Page 5: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

24.01.2007Introduction to Digital VLSIGil Rahav

•Better power supply•Expensive

C4 Bumps (Cont.)

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Floor Plan + Considerations

Page 7: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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Source

Drain

Gate

Source

Drain

Gate

Layout - Transistor

Page 8: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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Layout - inverter

Polysilicon gae

Metal

Contact

Vss

Vcc

In OutPolysilicon gate

Gate

Source

Source

Drain

Drain

In

Vcc

Vss

Out

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Proprietary Formats

ViewlogicMotive Modeling FormatMMF

SynopsysNon-Linear Delay Model cell-level timing modelNLDM

CadenceTable Lookup Format – cell-level timing modelTLF

CadenceVerilog Change DumpVCD

CadenceLayout Exchange FormatLEF

Mentor GraphicsInterpolated Table Lookup cell-level timing modelITL

CadenceStandard Parasitic Extended FormatSPEF

CadencePolygon Level Layout formatGDSII

SynopsysDesign Compiler Scripting LanguageDC Shell

CadenceDesign Exchange FormatDEF

TSSIWaveform Graphical LanguageWGL

OwnerDescriptionFormat

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Technical definitions

•GDSII file (also called GDBIN) –Binary file which contains info of layout cell.•LEF file –Library Exchange Format – ASCII file which can describe technology, special technology rules, cell’s size, obstructions and pins geometries.•Technology file -LEF file which contains a specific process definitionssuch as : number of metals and vias, electrical behaviorin terms of resistance and capacitance, special rules and more.

Page 11: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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•DEF file –Data Exchange Format – Ascii file which candescribe cell’s size, obstructions, pins and nets geometries, instance’s placement coordinates and orientation,floor plan description in details, special rules and more.•Obstruction –A geometry description for an occupied area whichis being described for a specific metal.Obstructiondefines keep out area for automatic route tool.•Abstract file –DEF / LEF file which contains physical info of cell’s size, pins and obstructions.

Technical definitions

Page 12: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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•DRC –•Design Rules Check – An automatic verification which verify that all released process rules are being respectedin the physical design.•LVS –Logic Versus Schematic – An automatic verification whichcompare equal of two files, spice netlist and physical spice.•ECO –•Engineering Change Order – New netlist description forchip top level or a module which contains minor changes related to previous netlist release.

Technical definitions

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Transistor

Key feature:transistor length L

p+ p+

n substrate

channel

Source Drain

p transistor

G

S

D

SB

Polysilicon GateSiO2

Insulator LW

G

substrate connectedto VDD

Polysilicon GateSiO2

Insulator

n+ n+

p substrate

channel

Source Drain

n transistor

G

S

D

SB

LW

G

S

D

substrate connectedto GND

2002: L=130nm2003: L=90nm2004: L=65nm

Page 14: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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Technology Library Structure� Date and Revision� Library Attributes� Environmental Descriptions

� Default Attributes� Nominal Operating Conditions � Custom Operating Conditions� Scaling Factors� Wire Load Models� Timing Ranges

� Cell Descriptions� Cell Attributes� Sequential Functions� Bus Descriptions

• Default Attributes• Bus Pin Attributes• Pin

• Pin Attributes• Combinational Function• Timing

• Timing Attributes• Timing Constraints

Page 15: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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D Flip-Flop Description

cell (dff) {area : 1 ;pin (CLK) {direction : input ;capacitance : 0 ;

}pin (D) {

nextstate_type : data;direction : input ;capacitance : 0 ;

}pin (CLR) {

direction : input ;capacitance : 0 ;

}

pin (PRE) {direction : input ;

capacitance : 0 ;

}ff (IQ, IQN) {

next_state : ”D” ;

clocked_on : ”CLK” ;

clear : ”CLR’” ;preset : ”PRE’” ;

clear_preset_var1 : L ;

clear_preset_var2 : L ;}

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Library File Extensions

� .lib Technology library source files� .plib Physical library source files� .pplib Pseudo physical library source files� .slib Symbol library source files� .db Compiled technology libraries in Synopsys internal database

format� .pdb Compiled physical libraries in Synopsys internal database

format� .sdb Compiled symbol libraries in Synopsys internal database

format� .vhd Generated VHDL simulation libraries� .E Encrypted VHDL files

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Full Chip Layout

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Active Regions

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Poly

Page 20: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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Metal 1

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Metal 2

Page 22: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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M3

Page 23: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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M4

Page 24: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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Full Chip Layout + Final Floorplan

ComparatorComparatorComparatorComparator

SRAMSRAMSRAMSRAM

DecoderDecoderDecoderDecoder

Control Control Control Control BlockBlockBlockBlock

REGISTERS

SSSSRRRR

RRRRNNNNGGGG

REGISTERS

RegistersRegistersRegistersRegisters

Page 25: Introduction to Digital VLSI Design - BGUdigivlsi/slides/floor_planning_2_1.pdf · Introduction to Digital VLSI 24 .01.2007 ... performance and area through floorplanning/placement,

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Definitions

Virtual Component (VC):

A block that meets the Virtual Socket Interface Specification and is used as a component in the Virtual Socket design environment. Virtual Components can be of three forms — Soft, Firm, or Hard --which are defined below.

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Hardness

�One parameter for characterizing VCs is the “hardness” of the block, or the degree to which the VC has been targeted toward a particular fabrication process.

�Three types of hardness: Soft VC, Firm VC, and Hard VC.

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Soft VC

�Soft VCs are delivered in the form of synthesi-zable HDL, and have the advantage of being more flexible and the disadvantage of not being as predictable in terms of performance (i.e., timing, area, power).

�Soft VCs typically have increased Intellectual Property protection risks because RTL source code is required by the integrator.

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Firm VC

�Firm VCs have been optimized in structure and in topology for performance and area through floorplanning/placement, possibly using a generic technology library.

�Firm VCs offer a compromise between Soft and Hard. More flexible and portable than Hard, yet more predictive of performance and area than Soft.

�Protection risk is equivalent to that of Soft if RTL is included and is less if it is not included.

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Hard VC

�Hard VCs have been optimized for power, size, or performance andmapped to a specific technology.

�Hard VCs are process/vendor specific and generally expressed in GDSII.

�Hard VCs require, at a minimum, a high level behavioral model, a test list, full physical and timing models along with the GDSII.

�The ability to legally protect Hard VCs is much better because of copyright protections and there is no requirement for RTL.


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