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Introduction to HSR/PRP/ IEEE 1588(PTP) - UCAIugucaiug.org/Meetings/CIGRE_2014/USB Promo...

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Introduction to HSR/PRP/ IEEE 1588(PTP) V:140626‐UCA STICK System-on-Chip engineering SoCe
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Page 1: Introduction to HSR/PRP/ IEEE 1588(PTP) - UCAIugucaiug.org/Meetings/CIGRE_2014/USB Promo Content/SoC-e... · Introduction to HSR/PRP/ IEEE 1588(PTP) ... DANH DANH DANH DANH DANH SOURCE.

Introduction to HSR/PRP/IEEE 1588(PTP)

V:140626‐UCA STICK

System-on-Chip engineering

SoCe

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Index:

SoCe

Introduction:• PRP (IEC 62439‐3 Clause 4)• HSR (IEC 62439‐3 Clause 5)• IEEE 1588 – IEC61588 (PTP)

HPS IP:• SoCe Industrial: Solutions• HSR/PRP Switch IP Scalability and Regular Ethernet Ports 

Introduction

SoCe Portable Tools

Cases –of­Use

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Introduction: Parallel Redundacy Protocol (PRP)

LAN ALANB

SAN

SAN

SAN

SAN

DAN DAN

VDANVDAN

RedBox

• PRP nodes (Dual Attached Nodes­DANs), are connected to two independent Ethernet networks (LAN A and LAN B)

• DAN nodes send the same frames over both networks

• Fault­free state: Destination nodes consume the first received frame and discard the duplicates

• Fault state: the frames will still be transmitted and received through the other

• Non‐PRP nodes can be attached to a single Network

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Introduction: PRP

• Redundancy Control Trailer (RCT):• 16bit sequence number• 4bit LAN identifier• 12bit Frame Size (additional check)• 16 bit PRP suffix 0x88FB (new in Ed. 2)

• Duplicate Discard Algorithm• Open to different implementations• Occasional acceptance of a duplicate is tolerated

dest_addr type

12

LSDU repairscr_addr sizesequence Lan FCS

140 6

RCT

padding PRP sufx

PRP Frame Format

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Introduction: PRP

• Monitor the status of each node and LANs Each DAN sends periodically a Supervision Frame

• Supervision Frame Format:• Multicast by each DANP over both ports every LifeCheckInterval• VLAN tag optional• MAC addresses• Protocol version• Mode of operation supported• Supervision frames sequence number

Network Supervision

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Introduction: High­availability Seamless Redundancy (HSR)

• HSR nodes (Dual Attached Nodes with HSR protocol ­ DANHs), are provided with two Ethernet ports

• Provide redundancy by sending duplicate packets in both directions

• Multicast and Unicast operation

• Typical configuration: rings and ring of rings

• SANs must be connected through a RedBox

• Deterministic (Worst Case Scenario)

switch

Red Box

SAN

Interlink

DESTINATIONS

A_frame (HSR) B_frame (HSR)

C_frame D_frame

AB

SANSAN

DANHDANH

DANHDANHDANHDANHDANH

DESTINATIONSSOURCE

switch

Red Box

SAN

Interlink

DESTINATION

A_frame (HSR) B_frame (HSR)

C_frame

D_frame

SANSAN

DANHDANH

DANHDANHDANHDANHDANH

SOURCE

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Introduction: HSR

• Supervision Frame Format:• Multicast by each DANH over both ports VLAN tag optional

• Ethernet subtype for supervision frames type

• MAC addresses• Protocol version• Mode of operation supported• Supervision frames sequence number

• HSR tag:• 16 bit Ethertype = 0x892F• 4bit path identifier• 12bit frame size• 16bit sequence number

HSR ‐ EtherType

destination

source

LPDU = 1500 octets

checksum

sequencesizepath

HSR Frame

HSR Tag

Original EtherType

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Introduction: HSR

QuadBox A

QuadBox B

A_frame (HSR)

B_frame (HSR)

C_frame

D_frame

DANHDANH

DANHDANHDANHDANHDANH

SOURCE

DANH

Ring 1

DANH DANH

Ring 2

DESTINATION

interlink

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Introduction: HSR & PRP

Red Box

DANHDANHDANHDANHDANH

Red Box

endnode

SOURCE

end node

DESTINATION

LAN BLAN A

interlink A interlink B

PRP nodes

DANH

BA ABA B

A A A A ABBBBBB

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Introduction: IEEE 1588 V2(Precise Time Protocol –PTP­)

• Synchronize Networked Clocks in nano­second range• Precision with easy installation• Systems Synchronization and Data Transfer in the same standard version

• Packet Looped Loop (approach) for syntonization using a PID algorithm

• Main Drawback:  It assumes that the packets will arrive at the destination reliably and with no delays

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Introduction: IEEE 1588 V2(Precise Time Protocol –PTP­)

Mastertime

Slavetime

t1

t2

t3

t4

t‐ms

t‐sm

syncfollow_up

delay_resp

delay_req

t2

t1  t2

t1 t2 t3

t1 t2 t3 t4

Timestampsknown by slave

Delay+Offset = t2 – t1

Delay‐Offset = t4 – t3

2)t(t)t(tDelay 3412 −+−

=

2)t(t)t(tOffset 3412 −−−

=

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Introduction: IEEE 1588 V2(Precise Time Protocol –PTP­)

Master SlaveTransparentClock 1

TransparentClock 2

Synchronization(t1,c)

C:=C0

Synchronization(t1,c)

Synchronization(t1,c)

t t

s1

s2

Time stamping

Synchronization residence time

Correction Field

C:=C+ s1

C:=C+ s2

End‐to‐End

Master TC

TC

Slave

TC

TC Slave

Slave

Slave

end-to-end delay measurement

Synchronization

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Introduction: IEEE 1588 V2(Precise Time Protocol –PTP­)

Master SlaveTransparentClock 1

TransparentClock 2

Synchronization(t1,c)

C:=C0

Synchronization(t1,c)

Synchronization(t1,c)

t t

s1

s2

Time stamping

s Synchronization residence time

Correction Field

C:=C+ s1+ L1

L1

L2

L3

C:=C+ s1+ L2

L uplink delay

C:=C+ L3

Delay calculations

Peer‐to‐Peer

Master

Slave

Slave

Slave

Slave

peer-to-peer delay measurement

Synchronization

TC

TC TC

TC

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Introduction: IEEE 1588 V2(Precise Time Protocol –PTP­)

• The precision of the results depends on the timestamps

PHY

MAC

NIC Driver

IP PTP Stack

UDP

PTP StackLargeunknown latency

Smallunknown latency

Smallknown latency

Only SW, Application LevelAcc.: 100usHuman Control

Driver LevelAcc.: 10us‐1usProcess/Motion Control

HW LevelAcc.: <50nsPrecision Control

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Introduction: IEEE 1588 V2(Precise Time Protocol –PTP­)

• IEEE 1588 Transparent Clock: Switches• IEEE 1588 Ordinary Clock: End‐ equipment• IEEE 1588 Master Clock: Clock Reference Equipments (GPS)• IEEE 1588 Boundary Clock: Gateways/Different Clock Domains• IEEE 1588 E2E:Mode of operation between Master and Slave• IEEE 1588 P2P:Mode of operation between peers• IEEE 1588 1­step: No need for follow‐up messages• IEEE 1588 2­step: Need for follow‐up messages

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Introduction: IEEE 1588 V2(Precise Time Protocol –PTP­)

PTP

UDP

IP

MAC

PHY

Boundary clock

Slave clockMaster clock

PTP

UDP

IP

MAC

PHY

PTP

UDP

IP

MAC

PHY

PTP

UDP

IP

MAC

PHY

Slave Master

Synchronization

Switching function

Message flow

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Energy, ISM, WirelessIP an software. Seamless integration with UES for 1588‐aware solution on Zynq

ZynqFull IEEE 1588 solution for Zynq

ISM, Industrial Ethernet, Aerospace

Multiport Ethernet Switch with IEEE1588 Transparent Clock.Combinable with HSR/PRP Switch

S6, Zynq‐7S

Unmanaged Ethernet Switch (UES)

Energy, ISM, WirelessProfinet IP, Ethernet IPS6, Zynq‐7S

Industrial Ethernet IPs

Name Dev. Description Sectors

HSR/PRP Switch S6, Zynq‐7S

Redundant Ethernet with IEEE1588 Energy, Transportation, Automation, Aerospace

Managed Ethernet Switch (MES) S6, Zynq‐7S

Multiport Ethernet Switch with 1588 Transparent Clock, managed (VLAN, manual access to MAC table)Combinable with HSR/PRP Switch

ISM, Industrial Ethernet, , Aerospace

Irigb and IEEE 1588­2008 v2 IPs S6, Zynq‐7S

Sub‐microsecond synchronization using Ethernet. Three IPs for different IEEE 1588 modes

Energy, ISM, Wireless

IP Cores

SoCe Industrial: Solutions

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Name Description Key features

NEToem Ready to use HSR/PRP/1588 solution for Fast Ethernet copper

• 4 integrated Ethernet Phyters•Industrial grade

SMARToem family Ready to use HSR/PRP/1588 solution for Fast Ethernet copper/fiber

• Up to 6 integrated Ethernet Combo Phyters•Industrial grade•Compatible (size, pins) with other modules•Design open to customer

NETBox Development‐kit and ready to use HSR/PRP RedBox

•JTAG, PMODs, •Graphic Display•Industrial grade

Modules and Development Platforms

SoCe Industrial: Solutions

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Modules and Development Platforms

SoCe Industrial: Solutions

SMARToem family

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HSR/PRP Switch IP Simplest Solution (fully scalable in Port Numbers)

PORTI

PORTA

PORTB

CTRL

HSR/PRP Switch IP

Spartan­6 FPGA

CPUEthernetController

Ethernet Phyter

Ethernet Phyter

RJ45/SFP

RJ45/SFP

Embedded SystemCPU Board

CPUEthernetController

Ethernet Phyter

RJ45/SFP

Embedded SystemCPU Board

NonRedundantEthernetNetwork

ZeroSwitchoverReliableEthernetNetwork

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ARM ® Cortex TM­A9

UART1

UART0

GMAC1

GMAC0

Processing System 7 Series Programmable LogicMemoryInterfaces

External Memory

CustomLogic

Ethernet Phyter

Ethernet Phyter

Console

Zynq® Platform ® SoC 

1 GE Interface 1

PORTI

AXI4

HSR/PRP Switch IP

PORTA

PORTB

AXI4

PHY‐MAC IF

PHY‐MAC IF

PHY‐MAC IF

HSR&PRPLink

USB0

Mouse & Keyboard

ExternalPeripheralsI/O

AXI4

HSR/PRP Switch IP : Simplest Solution (fully scalable in Port Numbers)

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SoCe Portable Tools

• Configuration and Management APIs

• Supervision Frames Management Tools

• RSTP Stacks

• Application Software Examples

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IED

IED

IED

IED

IED

Substation Bay 1

HSR‐1 (62439‐3‐Clause 5) Ring 

Network

PRP‐1 (62439‐3‐Clause 4) Redundant Ethernet Network

v

LAN A

LAN B

GPS

HSR/PRP Switch IP

IED

IED

IED

IED

Substation Bay 2

IED

IED

IED

IED

IED

Substation Bay N

HSR/PRP Switch IP

HSR‐1 (62439‐3‐Clause 5) Ring 

Network

HSR‐1 (62439‐3‐Clause 5) Ring 

Network

IED

HSR/PRP Switch IP

SCADA

v v v v

NCC NCC

Redbox

Case of use 1.: ELECTRIC SUBSTATION AUTOMATION: Process‐Bus implemented using HSR and Station and Inter‐bay Buses using PRP

SoCe Industrial : (case of use 1)

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CASE OF USE 2: TRANSPORTATION: Train Bus and Vehicle Bus implemented using HSR

HSR/PRPSwitch IP

HSR ring

HSR ring

SoCe Industrial : (case of use 2)

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System-on-Chip engineering, S.L.Zitek Bilbao ‐ ETSI Alda. Urquijo s/n

48013‐Bilbao (Bizkaia)Spain

Phone: +34 944420700 E‐mail: industrial@soc‐e.com

WEB: www.soc‐e.com

SoCe


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