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Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Introduction to Microelectronics
Dr. Hubert KaeslinMicroelectronics Design Center
ETH Zurich
VLSI I: Architectures of VLSI Circuits
last update: April 8, 2009
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Worldwide semiconductor market by vendors (2007)Revenue Share Share
Rank Vendor [GUSD] [%] [%]1 Intel 33.80 12.32 Samsung Electronics 20.46 7.53 Toshiba 11.82 4.34 Texas Instruments 11.77 4.35 Infineon + Qimonda 10.20 3.76 ST-Microelectronics 9.97 3.67 Hynix 9.10 3.38 Renesas 8.00 2.99 AMD 5.88 2.1
10 NXP 5.87 2.1... others 147.05 53.8
Total 237.91 100 0.49
for comparison World GDP (2006) 48 462 100source: Gartner March 2008 and www.worldbank.org May 2008
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Economic leverage of semiconductors I
Microelectronics has a much larger impact on world economy, however,because it is acting as a technology driver for
I Computer and software industry
I Telecommunications and media industry
I Commerce, logistics and transportation
I Natural science and medicine
I Power generation and distribution
I Finance and administration
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Economic leverage of semiconductors II
EDA software &virtual components
Semiconductor componentsElectronic components
Electronic goods(computers, mobile phones, home entertainment equipment, etc.)
Applications:• Goods with embedded electronics (machines, cars, cameras, watches, etc.)• Information technology services (corporate IT, Internet, music download, etc.)
World-wide gross domestic product 2006: 48.2 TUSD/y
2006: 248 GUSD/y
Figure: Impact of microelectronics on “downstream” industries and services.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Microelectronics drives the information age
I Microelectronics has an enormous economic leverage as any progressthere spurs innovations in “downstream” industries and services.
I While computing, telecommunication, and entertainment productsexisted before the advent of microelectronics, today’s informationsociety would not have been possible without.
⇒ Microelectronics is the enabler of information technology.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Microelectronics drives the information age
I Microelectronics has an enormous economic leverage as any progressthere spurs innovations in “downstream” industries and services.
I While computing, telecommunication, and entertainment productsexisted before the advent of microelectronics, today’s informationsociety would not have been possible without.
⇒ Microelectronics is the enabler of information technology.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Impact of semiconductors on consumer goods I
Figure: Four products that take advantage of microelectronics.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Impact of semiconductors on consumer goods II
Figure: Similar products that include no large-scale integrated circuits.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Impact of semiconductors on consumer goods III
Figure: A product that has brought system integration to even higher levels.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
The Guiness book of records point of view“How large is that circuit?”
I Geometric chip size
I Transistor count
I Gate-equivalents1 GE 7→ 1 two-input nand 7→ 4 MOSFETs in static CMOS logic
circuit complexity GEs of logic + bits of memorysmall-scale integration (SSI) 1 ... 10medium-scale integration (MSI) 10 ... 100large-scale integration (LSI) 100 ... 10 000very-large-scale integration (VLSI) 10 000 ... 1 000 000ultra-large-scale integration (ULSI) 1 000 000 ...
Hint: state storage capacities separately from logic complexity, e.g.75 000 GE of logic + 32 Kibit SRAM + 512 bit flash ≈ 108 000 GE
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
The Guiness book of records point of view“How large is that circuit?”
I Geometric chip size
I Transistor count
I Gate-equivalents1 GE 7→ 1 two-input nand 7→ 4 MOSFETs in static CMOS logic
circuit complexity GEs of logic + bits of memorysmall-scale integration (SSI) 1 ... 10medium-scale integration (MSI) 10 ... 100large-scale integration (LSI) 100 ... 10 000very-large-scale integration (VLSI) 10 000 ... 1 000 000ultra-large-scale integration (ULSI) 1 000 000 ...
Hint: state storage capacities separately from logic complexity, e.g.75 000 GE of logic + 32 Kibit SRAM + 512 bit flash ≈ 108 000 GE
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
What you ought to know about logic families
A logic family is a collection of digital subfunctions that• assemble to arbitrary logic, arithmetic and storage functions• are compatible among themselves electrically• share a common fabrication technology
Acronym Meaning
MOS Metal Oxide Semiconductor.FET Field Effect Transistor (n- or p-channel)BJT Bipolar Junction Transistor (npn or pnp)
CMOS Complementary MOS (circuit or technology)static CMOS data stored in bistable subcircuits and retaineddynamic CMOS data stored as electrical charges to be refreshedTTL Transistor Transistor Logic (BJTs & passive devices)ECL Emitter-Coupled Logic (non-saturating logic)BiCMOS CMOS & bipolar devices on a single chip
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
2-inputnandgate invarioustechno-logies
e)
OUP
VCC
GND
IN1
IN2
g)
bias section
other gatesshared with
(NAND)OUP1 OUP2
(AND)
IN1
IN2
VCC2
VEE
VCC1
p-channel
MOSFET
n-channel
voltage-controlledcurrent source
npn
pnp
current-controlledcurrent source
BJTdevice
icon
approximatebehavior
resistor diodedevice
icon
variations depletiondevice
c)
VDD
VSS
OUP
IN1
IN2
b)
OUP
VDD
VSS
IN1
IN2
evolutiontechnological
Figure: Static CMOS (c), NMOS (b), early TTL (e), and ECL circuit (g).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
The marketing point of view
“How do functionality and target markets relate to each other?”
General-purpose IC. Examples are either very simple or very generic.Simple circuit: gates, flip-flops, counters, etc.Generic functionality: RAMs, ROMs, microcomputers,FPL, etc.
Application-specific integrated circuit (ASIC).
I Application-specific standard product (ASSP):designed for a specific task and sold to variouscustomers.Examples: graphics accelerators, cellular radio chipsets, smart card chips, etc.
I User-specific integrated circuit (USIC):designed and produced for a single company.Examples: audio processor for hearing aids, etc.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
The marketing point of view
“How do functionality and target markets relate to each other?”
General-purpose IC. Examples are either very simple or very generic.Simple circuit: gates, flip-flops, counters, etc.Generic functionality: RAMs, ROMs, microcomputers,FPL, etc.
Application-specific integrated circuit (ASIC).
I Application-specific standard product (ASSP):designed for a specific task and sold to variouscustomers.Examples: graphics accelerators, cellular radio chipsets, smart card chips, etc.
I User-specific integrated circuit (USIC):designed and produced for a single company.Examples: audio processor for hearing aids, etc.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
A first IC classification scheme
counterlogicgate
SSI MSI LSI VLSI ULSI
multiplierparallel
complexityhardware
. . . . "system on a chip (SoC) " . . . .
functionality
glue logic
mobile radiobase-bandprocessor
compressorvideo data
digitalfilter
error-correctingencoder/decoder
transceiverspatial diversity
. . . . memory [and still more memory] . . . .. . . . program-controlled processor . . . .interface
computer
. . . . field-programmable logic devices . . . .(before getting programmed)
generalpurpose
application-specific
Figure: ICs classified as a function of functionality and hardware complexity.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
A first glimpse at VLSI manufacturing
a)
unprocessed wafer
b)
most masks shared with
other designs
few masksmade to orderfor one design
all masks made to orderfor one design
preprocessedwafer
Figure: Full-custom (a) and semi-custom (b) masks sets compared.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Semi-custom fabrication I
preprocessed master
a)
Figure: Prefabricated gate array site.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Semi-custom fabrication II
b)
custom metallization
+
Figure: Custom contact and metal masks.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Semi-custom fabrication III
c)
customized circuit
=
not used
not used
Figure: Site customized into a 2-input NAND gate.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Evolution of semi-custom floorplans
a)
predefined routing channel
b)
input/outputpad
routing channelonly where needed
unutilized areas
GA SOG
utilized devices
availability
metal layersof multiple
row of prefabricatedtransistor pairs
row of prefabricatedgate-array sites
Figure: Channeled gate-array (a) versus channelless semi-custom circuits (b).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Field-programmable logic
I No dedicated layout structures, no dedicated photomasks.Customization is via purely electrical means.
I “Programmable” is a misnomer as there is no instruction sequenceto execute. “Configurable” is more accurate as pre-manufacturedsubcircuits are made to form the target circuit.
I All configuration technologies today have their roots insemiconductor memory technology.
I Benefits compared to mask-programmed ASICs:I Easy and extremely fast to modify (highly agile).I Solutions for testability, I/O subcircuits, clock and power
distribution, embedded memories, etc. all come at no extra effortshut in the FPL component.
⇒ FPL can be thought as “soft hardware”.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
The fabrication point of view (summary)
“To what extent is a circuit manufactured to user specs?”
Full-custom IC: all fabrication layers, full set of photomasks.
Semi-custom IC (gate array, sea-of-gates, structured ASIC):a few metal layers only, subset of photomasks.
Field-programmable logic (SPLD, CPLD, FPGA):customization occurs electrically, no masks involved.
Standard part: catalog part with no customization whatsoeveraka commercial off-the-shelf (COTS) component.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
The design engineer’s point of view
“Which levels of detail are being addressed during a part’s design?”
Hand layout: Desired geometric shapes manually drawn to scale.
Cell-based design by means of schematic entry:Manual schematic entry automatic place & route.
Automatic circuit synthesis:Manual HDL or SW code writing automatic netlistgeneration.
I Logic synthesisI Register transfer level (RTL) synthesisI Architecture or high-level synthesis
Design with virtual components:Purchase of HDL code automatic netlist generation.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Views of a library cell (or of any other subcircuit)
a)
INAINBINC
OUP
architecture procedural of nor3 isbegin
end procedural;OUP <= not (INA or INB or INC) after tpd;
entity nor3 is
port (INA, INB, INC : in StdLogic;OUP : out StdLogic );
generic (tpd : time := 1.0 ns );
end nor3;
b)
0001
10
0010
10
0100
10
stimuli responses
1000
01
INA OUPINB INC
c)
d)
INA
INB
INC
OUP
e)
INA OUPINB INC
INA OUPINB INC
VSS
VDD
VSS
VDD
INA OUPINB INC
INA OUPINB INC
VSS
VDD
VSS
VDD
f)
Figure: Icon (a), simulation model (b), test vector set (c), transistor-level
schematic (d), detailed layout (e), and cell abstract (f).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Typical cell mix in a full-custom IC
stdcell
stdcell
stdcell
stdcell
stdcell
standard cell row
with over-the-cell routing
F4A
F4B
F1C
F1D
F1A
F1B
F4C
F4D
F2C
F2D
F2B
F2A
F3C
F3D
F3B
F3A
megacell
macrocell
megacell
megacell
megacell
macrocell
CLK RST
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Automatic circuit synthesis I
Logic synthesis accepts logic equations, truth tables, and state graphs.
Generates gate-level netlists for combinational logic andfor finite state machines (FSM).
⇒ Absorbed in today’s EDA flows.
Register transfer level (RTL) modelling:
I Circuit viewed as a network of storage elements— registers and possibly also RAMs — that are heldtogether by combinational building blocks.
I Behavioral specifications allowed to include arithmeticfunctions, string operations, arrays, enumeratedtypes, and other more powerful constructs.
⇒ Introduced in the early 1990s, universally adopted.Parametrized and portable designs favor reuse.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Automatic circuit synthesis II
b)
architecture procedural of patternmatch is
beginsignal PREST : Std_Logic_Vector(0 to 5);
end architecture procedural;
process (CLK,CLR) isbegin
if CLR=’1’ then
allbits : for i in 1 to 5 generate
end process;
elsif CLK’event and CLK=’1’ then
end generate;
PREST(i) <= PREST(i-1);end if;
PREST(0) <= INP;
PREST(i) <= ’0’;
OUP <= true when PREST(1 to 5)="11011"else false;
D Q
Q
CLRCLK
D Q
Q
CLRCLK
D Q
Q
CLRCLK
D Q
Q
CLRCLK
D Q
Q
CLRCLK
c)
a)
ROM
+ | - | 0
*
+1w w
v
2w+3
Figure: RTL diagram (a), RTL synthesis model (b), and gate-level schematic
(c) (simplified, note that (a) and (b) refer to different circuits).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Automatic circuit synthesis III
Architecture synthesis starts from a purely behavioral data processingalgorithm. Source code includes no explicit indications forhow to marshal data processing operations and hardwareresources. Works in five major phases:
1. Identify the computational and storage requirements.
2. From a virtual library, select a suitable building block for each kindof processing and storage operation.
3. Establish a cycle-based schedule for carrying out the algorithm.
4. Decide on a hardware organization able to execute the resultingwork plan.
5. Keeping track of data moves and operations for each clock cycle,translate into the necessary instructions for RTL synthesis.
⇒ Does not always yield optimal results, active field of research.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Virtual components
VCs (aka intellectual property modules or cores) are HDLsynthesis packages made available to others on acommercial basis:
I Vendor develops a major function into a synthesis model for sale.
I Licensee buys VC, incorporates it into his design, then carries outall the rest, i.e. synthesis, place and route (P&R), and overallverification.
I VCs are portable across fabrication technologies (soft modules),standard/macro/megacells are process-specific (hard modules).
I Most VCs implement fairly common subfunctions,parametrization is sought to cover more applications.
I Examples: processor cores, all sorts of filters, audio and/or videoen/decoders, cipher functions, error correction en/decoders, USB,FireWire, and other interfaces.
⇒ VCs have given rise to a new industry since the late 1990s.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Virtual components
VCs (aka intellectual property modules or cores) are HDLsynthesis packages made available to others on acommercial basis:
I Vendor develops a major function into a synthesis model for sale.
I Licensee buys VC, incorporates it into his design, then carries outall the rest, i.e. synthesis, place and route (P&R), and overallverification.
I VCs are portable across fabrication technologies (soft modules),standard/macro/megacells are process-specific (hard modules).
I Most VCs implement fairly common subfunctions,parametrization is sought to cover more applications.
I Examples: processor cores, all sorts of filters, audio and/or videoen/decoders, cipher functions, error correction en/decoders, USB,FireWire, and other interfaces.
⇒ VCs have given rise to a new industry since the late 1990s.Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
A second IC classification scheme
Fabricat. Electrical Semi-custom Full-customdepth configuration fabrication fabrication
Design Cell-based as obtained from Hand layoutlevel ◦ synthesis with VCs in HDL form,
◦ synthesis from captive HDL code,◦ schematic entry, or a mix of these
Product Field- Gate-array, Std. cell Full-customname programmable sea-of-gates, IC IC
logic device or structured(FPGA, CPLD) ASIC
IC families as a function of fabrication depth and design abstraction level.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Electronic system-level (ESL) design automation
Pressure towards better design productivity has incited the industry tolook at design automation from a wider perspective.
I Correct-by-construction methodology by supporting progressiverefinement starting with a virtual prototype
I Explore the architectural solution space more systematically andmore rapidly than with RTL synthesis methods.
I Make it possible to start software development before hardwaredesign is completed.
I Improve the coverage and efficiency of functional verification bydealing with system-level transactions and by taking advantage offormal verification.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Players in semiconductor markets I
Our final question relates to business.“How are the industrial activities shared between business partners?”
Traditional business model:
Integrated device manufacturer (IDM): a chip vendor who operates hisown wafer processing facilities.Examples: Intel, Toshiba, Samsung, ST-Microelectronics,IBM semiconductors, austriamicrosystems, etc.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Players in semiconductor markets II
More recent business models support more narrow specialization:
Silicon foundry: a company that operates a wafer processing line andthat offers its manufacturing services to others.Examples: TSMC, UMC, etc.
Fabless chip vendor: develops and markets proprietary semiconductorcomponents but has their manufacturing commissioned toan independent silicon foundry.Examples: Altera and Xilinx (FPL), Broadcom(networking), Cirrus Logic/Crystal (audio and video chips),Nvidia (graphics chips), Ramtron (non-volatile memories).
Fab-lite chip vendor: retains just the limited and specializedmanufacturing capabilities to integrate sensors, actuators,RF components, or photonic devices, in a silicon substratealong with electronic circuitry.Examples: Sensirion, Luxtera.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
Players in semiconductor markets III
Virtual component vendor: a company that develops synthesis packagesand licenses them to others for incorporation into theirown ICs.Examples: ARM, Sci-worx, Synopsys (former InSilicon).
System house: a company that integrates both hardware and softwareinto their products. Hardware is based on microprocessors,memories, ASSPs and FPGAs. USICs are being designediff they provide a competitive advantage.Examples: Apple (media players), Cisco (networkequipment), Landis+Gyr (energy meters), Valeo(automotive).
Many small and medium-sized electronics companies (typical for Europe)operate as system houses.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Guiness book of records point of viewThe marketing point of viewThe fabrication point of viewThe design engineer’s point of viewThe business point of view
What has made these new business models possible?
Three factors came together to make fabless operation possible:
I Generous integration densities at low costs.
I Proliferation of high-performance engineering workstations and EDAsoftware
I Availability of know-how in VLSI design outside IC manufacturingcompanies (this course).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
The Y-chart
physicalperspective
back-enddesign
behavioralperspective
structuralperspectivefront-end
design
physicalperspective
behavioralperspective
structuralperspective
transferfunctions
subtasks
truth tables,state graphs
data movesand operations
transistors, wires
gates, latches, flip-flops
ALUs, registers, memories
standard cells, macro cells
detailed layoutmask polygons,
chip or board
placementand routing
electrical
logic (aka gate-level)
architecture
system
register transfer
levels of abstraction
floorplan,partitioning
goal
start
algorithmand I/O
top blocks
subblocks
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
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Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
More design views
c)
architecture seriesexpansion of cosine isbegin
process (theta) is
beginsum := 1.0;
end process;end architecture seriesexpansion;
end loop;result <= sum;
variable sum, term : real;variable n : natural;
term := 1.0;n := 0;while abs term > abs (sum / 1.0E6) loop
n := n+2;term := (-term)*theta**2 / real(((n-1)*n));sum <= sum+term;
b)
e)
Uoup
inpU
trellistrace
unitback
survivormemory
branchmetric
unitcomput.
add-compare-
unitsselect
pathmetric
Imemory
pathmetric
IImemory
f)
a)
d)
A B
C
state graph(models reactive behavior)
data dependency graph(models transformatorial behavior)
localcontroller
localcontroller
localcontroller
super-visory
controller
Figure: Floorplan (a), software model (b), encapsulated chip (c), graphical
formalisms (d), transfer characteristic (e), and block diagram (f) (simplified).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
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Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Electronic system-level design flows
y s
t e m
- l
e v
e l
d e
s i
g n
collection of algorithmsalong with data formats
ASIC or programmable IC program-controlled processor
over a single consistent data base?
truly portable and amenableto synthesis with good results?
behavioralmodelling and
simulation
model librariesfor various
subfunctions
control flow,cooperat. finitestate machines
protocols,user interfaces
ressource and/orinstruction set
planning
algorithms andsystem archi-tecture design
abstract mathematical modelssubject to successive refinement
data networks,congestions,
traffic, queues
effects fromfinite word sizes,
scaling
filter synthesis,filtering,
correlation
error correctioncoding,
modulation
source coding,
compressiondata
key distribution,ciphering,
authentication clock recoverysynchronization,
is there an agreed-onsystem-level design
language (SLDL)?
is there any broadly acceptedformalism for specification?
• exploration,• fast prototyping, and • validationof algorithms and system architectures
implies addressing a subsetof the issues shown here
code generatorfor signal- or
microprocessor
machine code
to processor
from marketingand customers
HDL generatorfor hardware
synthesis
bit-trueHDL model
systemspecifications
SystemC may provide an answer
- interactive resource allocation- automatic scheduling- automatic binding- translation to RTL model
UML may provide a workable solution
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
System-level design
Decisions taken at this stage determine the final outcome more thananything else:
I Specify the functionality and characteristics of the system to be
I Partition the system’s functionality into subtasks
I Explore alternative hardware and software tradeoffs
I Decide on make or buy for all major building blocks
I Decide on interfaces and protocols for data exchange
I Decide on data formats, operating modes, exception handling, etc.
I Define, model, evaluate and refine the various subtasks
Result: System-level model.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Algorithm design
Streamline computations in view of their implementation in hardware:
I Cut down computational burden and memory requirements
I Find compromises between computational complexity and accuracy
I Contain effects due to finite word-length computation
I Decide on number representation schemes
I Evaluate alternatives and selecting the one best suited
I Quantify the minimum required computational resources
Result: Bit-true software model.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Digital VLSI design flow (front-end)f r
o n
t e
n d
d
e s
i g n
pre-layouttiming
verification
preliminarytiming
estimation
faultgrading
designarchitecture
gate-levelnetlist (1)
[or schematics]arith./logic ops
code of regs and
specifications
test vectorgeneration
insertion oftest structures
auto
m. t
est i
nser
tion
from system-level development
formalequivalence
check
block diagramhigh-level
[or HDL code]
electricalrule check
(ERC)
HD
L sy
nthe
sis
calculationdelay
cell and wire delays
floorplan
overall beha-vioral simulation
inp. to outp. mapping
block-level be-havioral simul.transaction-based
register transferlevel simulation
cycle-true
simulationgate-level
event-driven
behavioralmodelling
(algorithm withsoftware model
data formats)
gate-levelnetlist (2)
RTL designincl. macrocell
preparation
logic design andoptimization
estimation of diesize and major
cost factors
preliminarypower
estimation
high
-leve
l syn
thes
is
floorplanning,
and pinoutpackage selection
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Architecture design ITake important high-level decisions:
I Partition a computational task in view of a hardware realization.
I Organize the interplay of the various subtasks.
I Allocate hardware resources to each subtask (allocation).
I Define datapaths and controllers.
I Decide between off-chip RAMs, on-chip RAMs and registers.
I Decide on communication topologies and protocols (parallel, serial).
I Define how much parallelism to provide in hardware.
I Decide where to opt for pipelining and to what degree.
I Decide on a circuit style and fabrication process.
I Get a first estimate of the circuit’s size and cost.
Results: High-level block diagram and preliminary floorplan.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Architecture design IIWork out lower-levels details of an architecture by deciding:
I How to implement arithmetic and logic units?
I Whether to use hardwired logic or microcode for a controller?
I When to use a ROM rather than random logic?
I What operations to perform during which clock cycle (scheduling)?
I What operations to carry out on which processing unit (binding)?
I What clocking discipline to adopt?
I What time interval to use as the basic clock period?
I Where to prefer a bidirectional bus over two unidirectional ones?
I By what test strategy to ensure testability?
I How to initialize the circuit?
Results: Set of more detailed diagrams and verified RTL code.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
DigitalVLSIdesign flow(back-end)
b a
c k
e n
d
d e
s i g
n
preliminarycell placement
larg
ely
auto
mat
ed p
hysi
cal d
esig
n to
ols
detailedrouting
chip abstract layout
formalequivalence
check
floorplan
substitution ofdetailed layout
for cell abstracts
chip detailed layout
extraction ofdevices andinterconnect
layout versusschematic
(LVS)
substitution ofdetailed circuits
for cell icons
auto
mat
ic la
yout
mer
ge
to IC manufacturing hk 2.07.07
gate-levelnetlist (2)
placement andgate netlist (3)
transistor-level netlistback-annotated
extraction ofcell abstracts
and interconnect
layout versusschematic
(LVS)
layout/designrule check
(DRC)
post-layouttiming
verificationlogic simulation
post-layout
event-drivencalculation
delay
analysissignal integrity
gate-level netlistback-annotated
cell and wiredelays
analysispower grid
manufacturabilityanalysis
DRC and/or
padframe constr.,power distribution,initial placement
drawing ofbonding diagram
to IC packagingbondingdiagram
reoptimizationand rebuffering
of logic
clock treeinsertion
placement andgate netlist (4)
rebuffering,hold time fixing,and rerouting
gate-levelnetlist (5)
final
preliminaryabstract layout
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Physical design
Steps
I Floorplanning (begins during front-end design)
I Padframe generation and power distribution
I Intial placement of cells
I Reoptimization and rebuffering
I Clock tree insertion
I Detailed routing
I Rebuffering and hold time fixing
I Chip assembly (global routing)
I Substitution of detailed layout for cell abstracts
Result: Polygon layout data for mask preparation (GDS II).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Physical design verification
Prior to fabrication, all layout data need to be checked to protect againstfatal mishaps. The set of instruments available includes:
I Check conformity of layout with geometric rules (DRC)
I Search for patterns likely to be detrimental to yield
I Layout extraction [re-]obtains the actual circuit netlist
I Layout-versus-schematic (LVS)
I Post-layout timing verification
I Post-layout simulation
Result: Either proof of geometric integrity or error list.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
The leitmotiv of VLSI design
I Any design flaw found after tapeout or, even worse, after prototypefabrication wastes important amounts of time and money.
I Redesigns are so devastating that the entire semiconductor industryis committed to “first-time-right” design as a guiding principle.
I VLSI engineers typically spend much more time verifying a circuitthan actually designing it.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
The leitmotiv of VLSI design
I Any design flaw found after tapeout or, even worse, after prototypefabrication wastes important amounts of time and money.
I Redesigns are so devastating that the entire semiconductor industryis committed to “first-time-right” design as a guiding principle.
I VLSI engineers typically spend much more time verifying a circuitthan actually designing it.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Cell libraries Ilib
rary
dev
elop
men
t
hk 18.4.02
layout versusschematic
(LVS)
purc
hase
of c
ell l
ibra
ry
transistor-levelschematics
designtransistor level
circuitextraction
leaf cell layouts
circuitsimulation
continuous time
layout designat detail level
cellcharacterization
transistor-level netlistswith layout parasitics
leaf cell timing models
flow of design data
corrective action by designerbased on feedback information
design automation shortcuts
behavioral aspects
structural aspects
physical aspects
construction verification
list of leaf cells to be
behavioralmodelling
leaf cellfunctional models
target cell library
directly contribute to design decisions
and/or process data
manufacturabilityanalysis
DRC and/or
Figure: Library design flow.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Cell libraries II
The views required for each cell in a library include:
I Datasheet with functional, electrical and timing specs.
I Graphical icon or symbol.
I Accurate behavioral models for simulation and timing analysis.
I Set of simulation and test vectors.
I Transistor-level netlist or schematic.
I Detailed layout.
I Simplified layout showing only cell outline and connector locations(known as cell abstract, floorplanning abstract, or phantom cell).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
The Y-chart, a map of digital electronic systemsMajor stages in VLSI designCell libraries
Cell libraries III
I Designing, characterizing, documenting, and maintaining a celllibrary is a considerable effort.
I To protect their investments, library vendors are not willingto disclose how their cells are constructed internally.
I Vendors thus supply only cell abstracts.
I Detailed layouts are to be substituted for all abstractsby the vendor before mask preparation can begin.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Field-programmable logic (FPL) configuration technologies
a)
static memory cell
electronicswitch
c)
layout view
(to be blown or notnarrow constriction
during programming)
d)
cross section
base material
thin dielectric layer(to be ruptured or notduring programming)
metal
metal
b)
control gate(used for programming only)
floating gate(acting as charge trap)
cross section
metal metal
source drain
Figure: Configuration storage is adapted from semiconductor memories.
◦ SRAM: Switch steered by static memory cell (a),
◦ Flash: MOSFET controlled by trapped charge (b),
◦ PROM: fuse (c) and antifuse (d).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Field-programmable logic (FPL) configuration technologies(continued)
Non Live at Reconfi- Unlimit. Area ExtraConfiguration vola- power gurable endu- occupation fabr.technology tile up rance per link steps
SRAM no no in ckt yes large 0
UV-erasable yes yes out of no small 3EPROM circuit in array
Electr. erasable yes yes in ckt > 5EEPROM no 2·EPROMFlash memory no ≈EPROM
Antifuse PROM yes yes no n.a. small 3
Ideal yes yes in ckt yes zero 0
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Unlimited reprogrammability has its drawback
I Storing the FPL configuration is an SRAM-type memory implies thatthe configuration gets lost whenever the circuit is powered down.
I The problem is solved in one of three possible ways:
(a) by reading from a dedicated off-chip ROM (bit-serial or bit-parallel),(b) by downloading a bit stream from a host computer, or(c) by long-term battery backup.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Complex programmable logic devices (CPLD)
equivalent toone SPLD
programmableinterconnect
CPLDc)
ANDplane
ORplane
PLA
inputs outputs
a)
logicprogrammable
ANDplane
ORplane
SPLD
flip-flops & feedback
inputs outputs
b)
programmablefeedback
logicprogrammable
evolutiontechnological
evolutiontechnological
flip-
flops
& fe
edba
ck
AN
Dpl
ane
OR
plan
e
configurableI/O cell
Figure: General architecture of CPLDs (c) along with precursors (a,b).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Field-programmable logic devices (FPGA)Overall organization patterned after mask-programmed gate-arrays.
logiccell
config.
switchbox
conf.
configurableI/O cell
wire
s
FPGA
wires
Figure: General architecture of FPGAs.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Fine-grained FPGAs
A few logic gates and/or one bistable per configurable logic cell.
Actel logic tile
INP1
as clock
INP2may serve
OUP1to local routing
OUP2to long routing
may serveINP3
as reset
a)
subcircuitscontrolled by
configuration bits
Figure: Example: logic tile from Actel ProASIC.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Coarse-grained FPGAs
Combinationalfunctions offour or morevariables,
two or morebits stored perconfigurablelogic cell.
b)
Xilinx slice
LUTconfig.
D Q
ENA
SRREV
CLK
or
XQ
X
XMUX
XB
F5
YQ
Y
YMUX
YB
FX
D Q
CLK
G1
G2
G3
G4
F1
F2
F3
F4
SR
CE
BY
BX
FXINAFXINB
CIN
LUTconfig.
ENA
SRREV
CLK
or
Figure: Example: logic slice from Xilinx Virtex-4 (4-input LUTs, 2 bistables).
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
There is a general trend towards coarser granularities
Figure: LUT granularity trade-offs at the 65 nm technology node.
I The optimum trade-off for LUTs has shifted from 4 to 6 inputsover the last couple of process generations.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Example I:Logic slicefrom XilinxVirtex-5
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Example II: Adaptive logic module from Altera Stratix II
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Commercial products
overall organization of hardware resourcesconfiguration CPLD FPGAtechnology coarse grained fine grained
static Xilinx Spartan, Virtex. Atmel AT6000,memory Lattice SC, EC, ECP. AT40K.(SRAM) Altera FLEX, APEX,
Stratix, Cyclone.eASIC Nextreme SL
UV-erasable Cypress MAX340(EPROM) (discontinued)electrically Xilinx XC9500, Lattice XP Actel ProASICerasable CoolRunner-II. MACH XO. ProASICPLUS,(flash) Altera MAX3000, 7000. Fusion
Lattice MACH 1,...,5. Igloo.Cypress Delta39K,
Ultra37000.antifuse QuickLogic Eclipse II, Actel MX,(PROM) PolarPro. Axcelerator AX.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Watch out!
Capacity figures of FPL and of semi-custom ICs may be confusing.
Manufactured gates: Total number of GEs physically present on a die.
Usable gates: Maximum number of GEs that are usable under typical orbest case conditions. The exact percentage depends onthe application, advertisements tend to exaggerate.
Actual gates: GEs that are indeed put to service by a given design,corresponds to the GEs for a cell-based full-custom IC.
GEmanufactured > GEusable > GEactual
⇒ Carry out benchmarks with representative designs as this helps to
I make better cost calculations,
I obtain realistic timing figures,
I avoid misguided choices.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Watch out!
Capacity figures of FPL and of semi-custom ICs may be confusing.
Manufactured gates: Total number of GEs physically present on a die.
Usable gates: Maximum number of GEs that are usable under typical orbest case conditions. The exact percentage depends onthe application, advertisements tend to exaggerate.
Actual gates: GEs that are indeed put to service by a given design,corresponds to the GEs for a cell-based full-custom IC.
GEmanufactured > GEusable > GEactual
⇒ Carry out benchmarks with representative designs as this helps to
I make better cost calculations,
I obtain realistic timing figures,
I avoid misguided choices.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Some FPGAs also include wide datapath units (MAC)
Figure: Example: DSP48E slice from Xilinx Virtex-5.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
Further extensions
Many commercial parts include field-programmable logic plus
I hardwired SRAMs, FIFOs, clock recovery circuits, etc.
I hardwired microprocessor and DSP cores (e.g. PowerPC, ARM),
I hardwired standard interface circuits(PCI, USB, FireWire, Ethernet, WLAN, JTAG, LVDS, etc.)
I hardwired analog-to-digital and digital-to-analog converters,
I configurable analog building blocks (such as filters, for instance),
I field-programmable analog arrays (FPAA)built from OpAmps, capacitors, resistors and switchcap elements,
I combinations of the above.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
FPL design flow
I Front-end flow (architecture design, HDL coding, functionalverification) is much the same for FPGAs and CPLDs as for ASICs.
I Back-end flow differs to some extent.
1. Netlist obtained from HDL synthesis is mapped ontoconfigurable blocks available in the target device.
2. Interconnect gets implemented using the wires, switches anddrivers available.
3. Result is converted into a configuration bit stream for downloadinto the FPL device.
4. FPL vendors make available proprietary tools for the aboveprocedure.
⇒ Hierarchy of required skills:Field-programmable logic ⊂ Semi-custom ICs ⊂ Full-custom ICs.Let us begin with topics that matter independently of fabrication depth.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Configuration technologiesOrganization of hardware resourcesCommercial productsDesign flow
FPL design flow
I Front-end flow (architecture design, HDL coding, functionalverification) is much the same for FPGAs and CPLDs as for ASICs.
I Back-end flow differs to some extent.
1. Netlist obtained from HDL synthesis is mapped ontoconfigurable blocks available in the target device.
2. Interconnect gets implemented using the wires, switches anddrivers available.
3. Result is converted into a configuration bit stream for downloadinto the FPL device.
4. FPL vendors make available proprietary tools for the aboveprocedure.
⇒ Hierarchy of required skills:Field-programmable logic ⊂ Semi-custom ICs ⊂ Full-custom ICs.Let us begin with topics that matter independently of fabrication depth.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Major semiconductor technologies and logic families
The alphabet soup explained.
Acronym Meaning
MOS Metal Oxide Semiconductor.FET Field Effect Transistor (n- or p-channel)BJT Bipolar Junction Transistor (npn or pnp)
NMOS n-channel MOS (transistor, circuit or technology)PMOS p-channel MOS (transistor, circuit or technology)CMOS Complementary MOS (circuit or technology)static CMOS data stored in bistable subcircuits and retaineddynamic CMOS data stored as electrical charges to be refreshedTTL Transistor Transistor Logic (BJTs & passive devices)ECL Emitter-Coupled Logic (non-saturating logic)BiCMOS CMOS & bipolar devices on a single chip
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
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Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
2-input nand gate in TTL technologyTTL invented 1961 as an improvement over DTL and RTL.
d)
IN1OUP
IN2
e)
OUP
VCC
GND
IN1
IN2
f)GND
VCC
OUPIN1
IN2
evolutiontechnological
Figure: Icon (d), original multi-emitter circuit (e), and more recent F generation
circuit (f). The auxiliary devices serve clamping and speed-up purposes.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
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Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
2-input nand gate in ECL technologyECL invented 1956 as fast non-saturating current switching logic.
resistor varicapdiodedevice
icon
p-channel
MOSFET
n-channel
voltage-controlledcurrent source
npn
pnp
current-controlledcurrent source
BJTdevice
icon
approx.behavior
Schottkydevicevariations depletion
device
g)
bias section
other gatesshared with
(NAND)OUP1 OUP2
(AND)
IN1
IN2
VCC2
VEE
VCC1
Figure: Circuit (g) with schematic symbols used.
Switching is by current steering without transistors entering saturation.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
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Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
2-input nand gate in MOS technologies
CMOS invented 1963 as an improvement over NMOS and PMOSwith (close-to) zero quiescent power.
a)
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c)
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Figure: PMOS (a), NMOS (b), and static CMOS (c) circuits.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics
Economic impactConcepts and terminology
Design flow in digital VLSIField-programmable logic
Appendix I: A brief glossary of logic families
Why does CMOS technology dominate VLSI today?
As first observed in 1972 by Robert Dennard
I Geometric down-scaling benefitsI layout density,I operating speed,I energy efficiency, andI manufacturing costs per function.
I Simplicity and comparatively low power dissipation have allowedfor integration densities not possible on the basis of BJTs.
⇒ After a start as a low-power but slow circuit alternative, CMOShas gradually displaced competing technologies and logic families.
Dr. Hubert Kaeslin Microelectronics Design Center ETH Zurich Introduction to Microelectronics