Introduction to PlayStation®2 Architecture

James RussellSoftware Engineer

SCEETechnology Group

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In this presentation

ä Company overviewä PlayStation 2 architecture overviewä PS2 Game Developmentä Differences between PS2 and PC.

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1) Sony Computer Entertainment Overview

Japan

SCE Europe(includes Aus,NZ, Mid East,

Southern Africa)America

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Sales

ä 40 million sold world-wide since launchä Since March 2000 in Japanä Since Nov 2000 in Europe/US

ä New markets: Middle East, India, Korea, China

ä Long term aim: 100 million within 5 years of launch

ä Production facilities can produce 2M/month.

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Design considerations

ä Over 5 years, we’ll make 100,000,000 PS2s

ä Design is very importantä Must be inexpensive (or should become that way)ä Technology must be ahead of the curve

ä Need high performance, low price.

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How to achieve this?

ä Processor yieldä High CPU clock speed means lower yields

ä Solution?ä Low CPU clock speed, but high parallelism

ä Nothing readily availableä SCE designs custom chips.

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2) Technical Aspects of PlayStation 2

ä 128-bit CPU core “Emotion Engine”ä + 2 independent Vector Unitsä + Image Processing Unit (for MPEG)

ä GS - “Graphics Synthesizer” GPUä SPU2 - Sound Processing Unitä I/O Processor (CD/DVD, USB, i.Link).

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“Emotion Engine” - Specifications

ä CPU Core 128 bit CPU ä System Clock 300MHzä Bus Bandwidth 3.2GB/sec ä Main Memory 32MB (Direct

Rambus)ä Floating Point Calculation 6.2 GFLOPSä 3D Geometry Performance 66 Million

polygons/sec.

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System Architecture

RAM

RAM

ROM CD/DVD

VIDEO OUT

AUDIO OUT

EXTERNAL DEVICES

EmotionEngine

(EE)

EmotionEngine

(EE)

I/OProcessor

(IOP)

GraphicSynthesiser

(GS)

SoundProcessor

(SPU2)

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Emotion Engine architecture

IOPDRAM

FPUCOP1 CPU

Core

VU0

COP2

VU1

EFUGIF

SIFDRAMCIPU

128bit Main Bus

GS

DMACTimer

INTC

Overview

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Emotion Engine architecture

IOPDRAM

FPUCOP1 CPU

Core

VU0

COP2

VU1

EFUGIF

SIFDRAMCIPU

128bit Main Bus

GSCPUCore

DMACTimer

INTC

CPU Core

ä 128 bit CPUä 300 MHz clock frequencyä MIPS instruction setä 64 bit instructions, 2-way

superscalarä 128 bit multimedia instructions

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Emotion Engine architecture

IOPDRAM

FPUCOP1 CPU

Core

VU0

COP2

VU1

EFUGIF

SIFDRAMCIPU

128bit Main Bus

GSCPUCore

DMACTimer

INTC

CPU Core

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Emotion Engine architecture

IOPDRAM

FPUCOP1 CPU

Core

VU0

COP2

VU1

EFUGIF

SIFDRAMCIPU

128bit Main Bus

GSCPUCore

DMACTimer

INTC

CPU Core

ä 16Kb I-Cacheä 8Kb D-Cacheä 16Kb scratchpad

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Emotion Engine architecture

IOPDRAM

FPUCOP1 VU0

COP2

VU1

EFUGIF

SIFDRAMCIPU

128bit Main Bus

GS

Floating Point Unit (FPU)

CPUCore

Timer

INTC

DMAC

FPUCOP1

Single FPU for the CPU core

CPUCore

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Emotion Engine architecture

IOPDRAM

FPUCOP1 VU0

COP2

VU1

EFUGIF

SIFDRAMCIPU

128bit Main Bus

GS

DMAC

DMA Controller (DMAC)

CPUCore

INTC

Timer

INTC

DMAC

ä Moves data from memory to devicesä Essential to maximising EE performance

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Emotion Engine architecture

IOPDRAM

VU0

COP2

VU1

EFUGIF

SIFDRAMCIPU

128bit Main Bus

GS

Timer

INTC

VU0

COP2

VU1

EFU

CPUCore

Vector Processing Units (VU0 & VU1)

FPUCOP1

DMACDMAC

ä Used for mathematical operationsä FMACs for addition and multiplicationä FDIV for division and square root operationsä Built-in memory for microprograms

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Emotion Engine architecture

IOPDRAM

FPUCOP1 VU0

COP2

GIF

SIFDRAMCIPU

128bit Main Bus

GS

DMACTimer

INTC

VU0

COP2

VU1

EFU

CPUCore

VU1

EFU

ä 4 FMACs, 1 FDIVä Connected to the CPU, executing macroinstructionsä 4 KB VUMem (data), 4 KB MicroMem (instructions)ä Usually used for animation and physics.

Vector Unit 0 (VU0)

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Emotion Engine architecture

IOPDRAM

FPUCOP1 VU0

COP2

GIF

SIFDRAMCIPU

128bit Main Bus

GS

DMACTimer

INTC

VU0

COP2

VU1

EFU

CPUCore

VU1

EFU

Vector Unit 0 (VU0)

ä The VU0 is a 128 bit SIMD/VLIW design.ä A SIMD processor operates on vectors of data.

As an example, when a SIMD instruction adds 64 bit numbers, the 64 data streams are sent to 64ALUs to perform 64 sums in a single clock cycle

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Emotion Engine architecture

IOPDRAM

FPUCOP1

GIF

SIFDRAMCIPU

128bit Main Bus

GS

DMACTimer

INTC

VU0

COP2

CPUCore

VU0

COP2

VU1

EFU

VU1

EFU

ä No direct path to CPU core, but direct path to GIFä 16 Kb VUMem (data), 16 Kb MicroMem (instructions)ä Used for geometry transformations

Vector Unit 1 (VU1)

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Emotion Engine architecture

IOPDRAM

FPUCOP1

GIF

SIFDRAMCIPU

128bit Main Bus

GS

DMACTimer

INTC

VU0

COP2

CPUCore

VU0

COP2

VU1

EFU

VU1

EFU

Vector Unit 1 (VU1)

ä VU1 is architecturally identical to VU0, but has some additional features that are related to the fact that VU1 acts as a geometry processor for the GS. One of these features is the EFU, which is composed of 1 FMAC and 1 FDIV unit, and it is used to perform more basic calculations for geometry processing No direct path to CPU core, but direct path to GIF

ä VU1 has 16K instruction memory and data memory while VU0 has only 8K/8k of memory. This larger amount is because VU1 is a geometry processor and therefore is required to handle much more data than VU0

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Emotion Engine architecture

FPUCOP1

IPU

128bit Main Bus

GS

DMACTimer

INTC

CPUCore

VU0

COP2

VU1

EFUGIF

IPU

DRAM

DRAMC

Image Processing Unit (IPU)

ä Image data decompression processorä Decodes MPEG2 streams

IOP

SIF

IOP

SIF

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System Architecture

EmotionEngine

(EE)

RAM

RAM

GraphicSynthesiser

(GS)

VIDEO OUT

SoundProcessor

(SPU2)

AUDIO OUT

EXTERNAL DEVICES

EmotionEngine

(EE)

GraphicSynthesiser

(GS)

ROM CD/DVD

I/OProcessor

(IOP)

ä Clock Frequency 150 Mhzä Embedded DRAM 4MBä Total memory bandwidth 1.2Gb/secä Pixel fill rate 2.4GPixel/sec.

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GS specifications

ä Clock Frequency 150 Mhzä Embedded DRAM 4MBä Total memory bandwidth 1.2Gb/secä Pixel fill rate 2.4GPixel/sec.

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System Architecture

EmotionEngine

(EE)

I/OProcessor

(IOP)

RAM

RAM

ROM Disc Drive

VIDEO OUT

SoundProcessor

(SPU2)

AUDIO OUT

CD/DVD

I/OProcessor

(IOP)

GraphicSynthesiser

(GS)

GraphicSynthesiser

(GS)

EXTERNAL DEVICES

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IOP (Input/Output Processor)

ä Contains an R3000 (PlayStation CPU+)ä Used for backwards compatibilityä 2 MB of RAMä Handles all external devicesä Controllersä USBä SPU 2ä CD/DVD unitä IEEE1394ä Hard disc, ethernet/modem.

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System Architecture

EmotionEngine

(EE)

I/OProcessor

(IOP)

RAM

RAM

ROM

VIDEO OUT

SoundProcessor

(SPU2)

AUDIO OUT

I/OProcessor

(IOP)

CD/DVD

GraphicSynthesiser

(GS)

SoundProcessor

(SPU2)EXTERNAL DEVICES

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SPU 2

ä 48 Channelsä 2MB sound memoryä Output to DAC or Optical digital output (Dolby

5.1)ä Realtime DTS 5.1 is possible.

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Coming Soon..

ä Broadband Adaptorä HDD interface & 100/10 Ethernet portä Ethernet allows access to broadband (via

ADSL/CATV/Satellite/etc)ä HDD used by game for local storage, or

downloadable content.

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3) Game Development

ä Programming a game on the PS2.

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PS2 Development EnvironmentThe TOOL

ä TOOL = PlayStation 2 with more RAM, and network

ä A separate Linux/Windows box runs the compilers and debuggersä Connects over the network to

the TOOL.

ä Use Linux-based tools (provided), or 3rd-party Windows development tools

LAN

PC

TV

Controllers

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Console programming

ä Halfway between embedded system and PC.ä Small & basic OSä Large amount of control

ä Low level codingä No driversä Standard hardware means you can optimise for

the systemä Performance analysis has benefit.

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Differences between PS2 and PC

ä Uses parallelismä Information should ‘stream’ through the systemä But not all algorithms are parallelisable

ä Random memory access hits hardä Data must be reorganised so that related parts sit

together

ä Optimisation is easier on PS2ä Standard hardware means optimisation works on

all machines.

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Rasterisation

Transformto 2D

Traverse scene

Calculateanimation

+-*/

+-*/

Basic Rendering Pipeline

CPU + coprocessor VU0

List processing DMA

VU1

GS

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DMA bus: 2.4Gb/secMemory

VU0CPU

Geometry andtexture

IOP SPU IPU

VU1 GS

Transformation

FPU

1st Attempt At A PC Port(max 0.5 million polys)

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DMA bus: 2.4Gb/secMemory

VU0CPU

Geometry andtexture

IOP SPU IPU

VU1 GS

Transformationin parallel with CPU

FPU

2nd Attempt At A PC Port(max 1.5 million polys)

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DMA bus: 2.4Gb/secMemory

VU0CPU

IOP SPU IPU

VU1 GSFPU

Transformation

Geometry Texture

Complete Game (lighting, animation)(typical 5-10 million polys)

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How To Improve PS2 Performance

ä By not treating the PS2 as a PCä Think parallel – think ‘assembly

line’ä Code for small Instruction and

Data Cache

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Summary

ä PS2 is a state-of-the-art machine

ä Achieves high performance and low cost through high parallelism

ä But it requires a different way of programming

ä Question Time!