Introduction to Verilog and Combinational Logicntroduction to Verilog and Combinational Logic

8/18/2019 Introduction to Verilog and Combinational Logicntroduction to Verilog and Combinational Logic

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Introduction to VerilogCombination Logic

Integration System & Intellectual Property Lab

CSIE NCTU

TA : Yu-Chun KuoProfessor : Terng-Yin Hsu


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Outline

isIP Integration System & Intellectual Property Lab

• Introduction• Gate-level Design• Combinational Logic


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Outline


• Introduction- Design Flow- Module- Lexical Convention- Data Types

- Operator Types- Port

• Gate-level Design• Combinational Logic


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Design Flow

Design Specification

RTL Model

Gate-level Model

Physical Layout

Synthesis

Layout

VerilogHDL



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• Basic building block : module

Module

module ( ) ;

endmodule

module FullAdder ( sum, c_out, a, b, c_in ) ;…endmodule

• Example

a

c_inb

c_out

sum



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Lexical Convention• Four logic values

- 0 : logic zero or false condition- 1 : logic one or true- x : unknown logic value- z : high-impedance

•

Number specification’- : length in bits- : b(binary), o(octal), d(decimal) or h(hexadecimal)- : any legal number in the selected base

• Example- 4’b0101 , 16’h1A80 , 32’d10- 8’h1x , 4’bzzzz- 12’b0101_1001_0110



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• Data types- wire : represent physical connections between devices ( default = z )- reg : represent abstract data storage element ( default = x )- integer : 32-bit unsigned

Data Types

• Example- wire a, b ; // 1-bit wire

- reg c, d ; // 1-bit reg- wire [7:0] bus ; // 8-bit wire, bus[7] is the MSB- reg [0:31] address ; // 32-bit reg, address[0] is the MSB

• Declaration syntax [ : ]



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• OreratorsAritthmetic- A = B + C;- A = B – C;- A = B * C;

- A = B / C;- A = B % C;

Shift- A = B >> 2;

- A = B >> 2;- A = B


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• OreratorsBitwise- A = ~ B;- A = B & C;- A = B | C;

- A = B ^ C;- A = B ~^ C;

Logical- A = ! B;

- A = B && C;- A = B || C;

Operator Types



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• OreratorsRational and Equality- , ==, !=, ===, !==

Reduction- A = & B;- A = | B;- A = ̂ B;- A = ~& B;- A = ~| B;

- A = ~^ B;

Operator Types



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• OreratorsConcatenation- A = { B , C }; // B = 2’b00, C = 4’b1001 → A = 6’b001001- A = { B , C[1:0] }; // B = 2’b00, C = 4’b1010 → A = 4’b0010

Replication- A = { 2{B} }; // B = 1’b1 → A = 2’b11;- A = { {4{B}} , 2{C} }; // B = 1’b1, C = 2’b01 → A = 8’b11110101

Conditional- C = sel ? A : B;

Operator Types



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Port• Port connection rules

reg or wire wirereg or wirewire

input output

inout

wire

wire

module



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Port• Connect ports by order

FullAdder fa0( Sum, C_out, A, B, C_in );

• Connect ports by nameFullAdder fa1( .sum(Sum), .c_out(C_out), .a(A), .b(B), .c_in(C_in) );



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Outline


• Introduction• Gate-level Design

- Gate Types- Full Adder- Ripple Adder- Gate delay

• Combinational Logic


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Gate Typesand 0 1 x z

0 0 0 0 01 0 1 x xx 0 x x xz 0 x x x

or 0 1 x z

0 0 1 x x1 1 1 1 1x x 1 x xz x 1 x x

nand 0 1 x z

0 1 1 1 11 1 0 x xx 1 x x xz 1 x x x

nor 0 1 x z0 1 0 x x1 0 0 0 0x x 0 x xz x 0 x x

xnor 0 1 x z0 1 0 x x1 0 1 x xx x x x xz x x x x

xor 0 1 x z0 0 1 x x1 1 0 x xx x x x xz x x x X

buf in out

0 01 1x xz x

not in out

0 11 0x xz x



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module FullAdder( sum, c_out, a, b, c_in );

//port declarationoutput sum, c_out;input a, b, c_in;//data_type declarationwire t1, t2, t3;//structure of full_adderxor x0(t1, a, b);xor x1(sum, t1, c_in);and a0(t2, c_in, t1);

and a1(t3, b, a);or o0(c_out, t2, t3);endmodule

Full Adder


c_out

sum

t1

t2

t3

a

b

c_in


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`include "FullAdder.v"module RippleAdder( sum, c_out, a, b, c_in );//port declarationoutput [3:0] sum;output c_out;input [3:0] a, b;

input c_in;//data_type declarationwire c1, c2, c3;//structure of ripple_adderFullAdder fa0(sum[0], c1, a[0], b[0], c_in);

FullAdder fa1(sum[1], c2, a[1], b[1], c1);FullAdder fa2(sum[2], c3, a[2], b[2], c2);FullAdder fa3(sum[3], c_out, a[3], b[3], c3);endmodule

Ripple Adder

fa0fa3 fa2 fa1 c_in

sum[0]sum[3] sum[2] sum[1]

c_out

a[0]a[1]a[2]a[3] b[0]b[1]b[2]b[3]



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• Gate delay

Gate Delay


Types of delay :- rise delay : 0, x or z → 1- fall delay : 1, x or z → 0- turn-off delay : 0, 1 or x → zUsage : #( rise_delay, fall_delay, turn-off_delay )

Three values :- minimum- typical- maximunUsage : #( min : typ : max )


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Gate Delay


Verilog uses typical delay values of each primitive to

simulate your design

Your can force verilog to use minimum or maximumdelay values to simulate your design by using thefollowing command line options- +mindelays, +typdelays, +maxdelays

Example- verilog test.v +maxdelays


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Gate Delay


• Example// one delay// if +mindelays, delay = 1// if +typdelays, delay = 2// if +maxdelays, delay = 3and #(1:2:3) a0(out, in1, in2);

// two delays// if +mindelays, rise = 1, fall = 4, turn-off = min(1,4)// if +typdelays, rise = 2, fall = 5, turn-off = min(2,5)// if +maxdelays, rise = 3, fall = 6, turn-off = min(3,6)and #(1:2:3, 4:5:6) a1(out, in1, in2);

// three delays// if +mindelays, rise = 1, fall = 4, turn-off = 7// if +typdelays, rise = 2, fall = 5, turn-off = 8// if +maxdelays, rise = 3, fall = 6, turn-off = 9and #(1:2:3, 4:5:6, 7:8:9) a2(out, in1, in2);


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Outline


• Introduction• Gate-level Design• Combinational Logic

- Assignments- Structured Procedures- Conditional Statements- 2-to-1 Multiplexer


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• Continuous assignmentwire out;assign #10 out = i1 & i2;

Assignments


• Procedural assignmentreg clk;always #5 clk = ~clk;


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• initial statement- start at time 0- execute exactly once during a simulation, and do not

execute again

- not use for synthesis

Structured Procedures


initial begin

…

end


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• always statement- start at time 0- execute continuously in a loop

Structured Procedures


always @( ) begin

…

end


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• if-else statement

Conditional Statements


if ( ) begin< statement1 >

endelse if ( ) begin

< statement2 >end…else begin

< default_statement >end


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• case statement

Conditional Statements


case ( )< alternative1 >: begin

< statement1 >end

< alternative2 >: begin< statement2 >

end…

default: begin< default_statement >end

endcase


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2-to-1 Multiplexer


MUX out

i1

i0

sel

module MUX( out, i0, i1, sel );

output out;input i0, i1, sel;

assign out = sel?i1:i0;

endmodule


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2-to-1 Multiplexer


MUX out

i1

i0

sel



reg out;

always @(i0 or i1 or sel) beginif(sel)

out = i1;else

out = i0;end

endmodule


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2-to-1 Multiplexer

i IP Integration S stem & Intellect al Propert Lab

MUX out

i1

i0

sel



reg out;

always @(i0 or i1 or sel) begincase (sel)

1'b0: out = i0;1'b1: out = i1;

endcaseend

endmodule

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Introduction to Verilog and Combinational Logicntroduction to Verilog and Combinational Logic

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