Introduction to VHDL

Jiri Gaisler

CTH / GaislerResearch

VHDL history

�

VHDL standsfor VHSIC (Very High SpeedIntergratedCircuit) HardwareDecriptionLanguage

�

Developedby Intermetrics,IBM andTexasInst.

�

Initial developmentcost:$33M (1983level)

�

IEEEstandard1076 �1987/93

�

One of thetwo mostcommonHDLs

VHDL objectives

�

Initial objectives(1983):

�

Modelling of digital systems

�

Un �ambigousandexecutable specification

�

Co �simulationof modelsfrom differentcompanies

�

Secondaryobjectives(1993+):

�

Automaticsynthesis

�

Gate �level sign �off simulation

�

RTL sign �off

Language overview

�

VHDL is basedonAdasemantics

�

A programconsistsof a numberof processes

�

All processesexecutesin avirtual environmentwhereaglobaltime andaneventqueueis maintained

�

Time is maintainedin discretesteps(e.g.1 ns)anddeltas(e.g.423ns,delta4).

�

All inter �processcommunicationoccursthroughthespecialdatastructuresignal

�

Thesignal messagedelayis at leastonedelta

Graphical VHDL example

P1

P2

1ns

S1

P3

P4

1ns

S2

1

�S3

Scheduling and execution

�

Eachprocesshasa list of signalscalledsensitivity list(thelist maybeempty)

�

A processis scheduledfor executionwhenanyof thesignalsin its sensitivity list changevalue,or whenatimedsuspensionexpires

All scheduledprocessesareexcutedfor oneiteration,oruntil theyblockon aspecificwait statement

Simulation cycle

1. Simulationtime is advanceduntil asignaldriverbecomesactiveor a suspendedprocessresumes

2. Signalvaluesareupdatedfrom activedrivers

3. All processessensitiveto signalswith events,andresumedprocesses,arescheduledfor execution

4. All scheduledprocessesexecuteuntil suspension

5. Theeventqueueis updatedwith newsignaldriverevents

A VHDL entity

ThesmallestexecutableVHDL moduleis anentity

Similar to anAda task,it consistsof a interfacedeclarationandabody.

It cancontainanynumberof processesandsignals.

It cancontainotherentities(hierarchicaldesign)

Entity declaration

Entity ramisgeneric (a : integer);port (addr: in integer;data: inout integer;err : out integer;csn: boolean � � implicit in

);type ....constant ...

end;�

Portsaresignals

�

Genericsarelocal constants

�

Typeandconstantdeclarations allowedin entitybut less frequentlyused.

VHDL Entity structureEntity entity_name is entitydeclarationgeneric_declarations;port_declarations;);

architecture arch_name of entity_name istype_declarations; arch.declarationpartconstant_declarations;signal_declarations;subprogram_declarations;component_declarations;

beginconcurrent_statements; arch.statementpartprocess_statements;component_instatiations;generate_statements;

end;

Type declarations

�

Scalartypes

�

Integer,floating �point

�

Enumerated,physical

�

Composite

�

Records,arrays

�

Access

�

File�

Integer:+/ � 231

�

Real: �1E38to +1E38

�

Standardoperatorsdefined

+, �, *, /, <, >, =

�

Enum:

type booleanis (false,true);

type bit is ('0', '1');

type shortis range 0 to 7;

Type declarations

�

Physicaltypes

typetime is range0 to 1E18unitsfs;ps= 1000fs;ns= 1000ps;us= 1000ns;ms= 1000us;s= 1000ms;

endunits;

wait for 10us;a<= b after(10ms+ 1 ns);

�

Compositetypes

typebarris array(1 to 5) of bit;typev is array(integerrange<>) of real;subtypefarr is x ( 0 to 127);

signaly : v(10 downto0);attributes:v'length,v'range,v'left, v'right

typemrecis recorda : integer;

endrecord;

variablex : mrec;x.a:= 3;

Constant declarations

�

Constantscanoccurin entitiesandsub �programs

constant name: type:= value;

constant pi : real:= 3.1416;

�

Aggregatesareallowed:

constant v : int_vector(1 to 8) := (1, 2, 3, 4, others=> 0);

�

Constantexpressionareallowed:

constant v : integer:= a**3 + xfunc(34);

Signal declarations

�

Signaldeclarationis allowedin thedeclarationpartof anarchitecture

�

An defaultvalueis allowed(butnot synthesisable)

signal name: type[:= value];

signal s1: integer;signal s2: bit_vector(1to 2) := “00”;

VHDL signals

�

Holdsavalueof (almost)anydatatype

�

Assignmententersa drivereventin theeventqueue:

a<= b after10 ns; � � eventafter10nsdelay

a<= b; � � eventafter1 deltadelay

�

In additionto its currentvalue,severalattributesareimplicitly maintained:s'event,s'last_event,s'last_value,s'stable...

�

A signalwith multiple driversmusthavea resolutionfunctiondeclared

Component declarations

�

Componentdeclarationis allowedin architecturedeclarationpartandin packages

�

Is usedto maketheinterfaceof anotherentity visible

�

Mustbeidenticalto theoriginalentity,butgenericscanberemovedif notused

component adderport (a : in integer;b : in integer;c : out integer

);end component;

Sub �program definition

�

Sub �programdefinition is allowedin architecturedeclarationpart,in sub �programdeclarationpart,andin packages

�

Similar semanticsto AdaandPascal

function parity (v : bit_vector)return bit isvariable b : bit;

beginfor i in v'range loopb := b xor v(i);

end loop;return b;

end;

Processes

�

Processesaredefinedthroughconcurrent statements, orprocess statements

�

Choiceof syntaxdoesnot changefunction

�

Eachconcurrentstatementis aseparateprocess,with allinput signalsimplicitely addedto thesensitivitylist

�

Theprocessstatementallowsexplicitedeclarationofsensitivitylist, andtheuseof wait statements

�

All codewithin aprocessstatementexecutessequentially

Process structure

�

Similar structureto asub �program(procedure)

Label: process [(sensitivity_list])]type_declarations; � � processdeclarationpartconstant_declarations;subprogram_declarations;variable_declarations;

beginsequential_statements; � � processstatementpart

end;

�

Wait statementallowedif nosensitivitylist

wait for 10ns;wait on a,b, c until a> b for 300ns;

Concurrent vs. Process statements

�

Concurrentstatements

a<= b + c after10ns;

a<= b wheninc = 0elseb+1wheninc =1elseb+2;

�

Processstatement

p1 : process(b, c)begina<= b+cafter10ns;

endprocess;

p2 : process(b, inc)beginif inc = 0 thena<= b;

elsif inc =1 thena<= b+1;

elsea<=b+2;

endif;endprocess;

Sensitivity list vs. Wait statement

�

Sensitivitylist

p1 : process(a,b, c)beginres<= a+ b *c;

endprocess;

p2 : process(clk)beginif clk = '1' thenres<= a+ b*c;

endif;endprocess;

�

Wait statement

p1 : processbeginres<= a+ b *c;wait ona,b, c;

endprocess;

p2 : processbeginres<= a+ b*c;wait onclk until clk = '1';

endprocess;

Concurrent vs. Process statements

Concurrentstatementsarelimited in complexity,andsuitableto expressfunctionalityin dataflowmanner

Processstatementsallow complexstatementssuchasloopsandmulti !caseselections.

Proceduresandfunctionsmustusesequentialcode

Component instantiation

Providesameanto connectentitiesin ahierarchy

Theportstransportsthesignalswithoutdelay

"

Bothnamedandpositionsignalassociationallowed

"

Outputscanbeleft open(a=>open)

"

Allowed in architecture

architecturertl of xxx issignala,b, c, d, e, f : integer;

componentadderport (a : in integer;b : in integer;c : out integer

);endcomponent;

beginu0 : adderportmap(a => a,b => b, c =>c);

u1 : adderport map(d, e, f);end;

Generate statements

#

Allows to includeor excludestatementsin thearchitecture

#

Loopsallowed

#

Resolvedatelaborationtime

architecturertl2 of adderissignalc : bit_vector(8downto0);beginc(0)<= '0';g0 : for i in 0 to 7 generateu0 : full_adderportmap

(a(i), b(i), c(i), sum(i),c(i+1));endgenerate;

end;

Entity addergeneric(fast: boolean);portmap(a,b : in bit_vector(7dowto0);sum: out bit_vector(7downto0);

);

architecturertl of adderisbegina0: if fastgenerateu0 : csa_adder(a,b, sum);

endgenerate;a1: if not fastgenerateu0 : ripple_adder(a,b, sum);

endgenerate;end;

Packages

$

Similar to Ada,aVHDLpackagecontainsacollectionof types,constants,componentdeclarationsandsub %programs

$

Entitiesor processescannotbeplacedin packages!

$

Usageof packagesfollowsAdasyntax:

library ieee;useieee.std_logic_1164.all;useiee.std_logic_arith.”+”;

Packagecomplex_mathistypecomplexis recordr : real;i : real;

endrecord;functioncadd(c1,c2 : complex)

returncomplex;end;packagebodycomplex_mathisfunctioncadd(c1,c2 : complex)

returncomplexisvaraibleres: complex;

beginres.r:= c1.r+ c2.r;res.i:= c1.i + c2.i;returnres;

end;end;

Pre &defined types and packages

'

STANDARD

packagestandardistypebooleanis (false,true);typebit is ('0', '1');typecharacteris (NUL, SOH,..... 'A', 'B', 'C' ....DEL);typeintegeris range (2**31 to 2**31; ( ( implementationdefinedtyperealis (1E38to +1E38; ( ( implementationdefinedtypetime is .....

functionnow returntime;subtypenaturalis integerrange0 to integer'high;subtypepositiveis integerrange1 to integer'high;typestringis array(positiverange<>) of character;typebit_vectoris array(naturalrange<>) of bit;endstandard;

IEEE packages

)

std_logic_1164

typestd_ulogicis ('U', * * Uninitialized'X', * * Forcing Unknown'0', * * Forcing 0'1', * * Forcing 1'Z', * * High Impedance'W', * * Weak Unknown'L', + + Weak 0'H', + + Weak 1' +' + + Don'tcare

);typestd_ulogic_vectoris array(naturalrange<>) of std_ulogic;

Resolvedtypesarecalledstd_logic/ std_logic_vectors

IEEE packages

,

std_logic_1164,definedfunctions

,

and,nand,or, nor,xor, xnor,not (on scalarsandvectors)

,

to_bit, to_bitvector,to_stdlogic,to_stdlogicvector

,

is_x

,

std_logic_arith

typeUNSIGNEDis array(NATURAL range<>) of STD_LOGIC;typeSIGNEDis array(NATURAL range<>) of STD_LOGIC;

operators:+, -, *, / <, >, =, <=, >=, /=, abs,conv_integer,conv_unsigned,conv_signed,conv_std_logic_vector

Examples

.

Clockgenerator

signalclk : std_logic:= '0';

clk <= notclk after5 ns;

.

Transparentlatch

latch: process(clk, d)beginif clk = '1' thenq <= d;

endif;endprocess;

.

flip /flop

dff1 : process(clk)beginif clk'eventand(clk = '1') thenq <= d;

endif;endprocess;

dff2 : process(clk)beginif rising_edge(clk)thenq <= d;

endif;endprocess;

Library ieee; 0 0 SIMPLE ASYNC RAMuseieee.std_logic_1164.all;useieee.std_logic_arith.all;

entityasync_ramisgeneric( abits: integer:= 10; dbits: integer:= 8 );port (address: in std_logic_vector((abits01) downto0);data : inoutstd_logic_vector((dbits01) downto0);csn,wen,oen : in std_logic);

end;

architecturebehavioralof async_ramistypememis array(0to (2**abits 11)) of std_logic_vector((dbits11) downto0);

beginr : process(address,data,csn,wen,oen)variablememarr: mem;variabledout: std_logic_vector((dbits11) downto0);

beginif csn= '0' thendout:= memarr(conv_integer(unsigned(address)));if wen'eventand(wen= '1') thenmemarr(conv_integer(unsigned(address))):= data;

endif;if oen= '0' thendata<= dout;elsedata<= (others=> 'Z'); endif;

endif;endprocess;

end;

Library ieee; 2 2 32 2bit RAM BANKuseieee.std_logic_1164.all;useieee.std_logic_arith.all;

entitymem_bankisport (address: in std_logic_vector(23downto2);data : inoutstd_logic_vector(31downto0);csn,wen,oen : in std_logic);

end;

architecturebehavioralof async_ramis

componentasync_ramgeneric( abits: integer:= 10;dbits: integer:= 8 );port (address: in std_logic_vector((abits31) downto0);data : inout std_logic_vector((dbits31) downto0);csn,wen,oen : in std_logic);

endcomponent;

beginmb: for i in 0 to 3 generateu0 : async_ramgenericmap(22,8);

portmap(address,data(i*8+7downtoi*8), csn,wen,oen);endgenerate

end;

Common problems

4

Clockskew

clkn <= notclk;clk2 <= clk;

4

Signalsareassignedwith delay

a<= b;c <= a;

c is NOT equalto b !!

4

Oscillation

clk <= notclk;

4

Inifinite loop (missingwait)

processbeginstatements;..

endprocess;

Elaboration and start 5up

4

Beforeexecutionstarts,theprogramis elaborated

4

Generatesareresolved

6

All signalsandvariablesinitialised

6

All processesscheduledfor execution

6

Time is setto 0

Execution (simulation)

6

Theprogramis run for agiventime

6

Outputcanbewritten to consoleor files

6

Graphicaltracingof signalscommonduringdebug

7

Variablesdifficult to trace(asin Ada/Pascal)

7

No exit() call – difficult to 'stop'aprogramfrom within

Execution (simulation)

Not covered topics

8

Configurations

8

Blocksandguards

8

Textiopackageandfile I/O

8

Synthesissubset

VHDL resources on the web

8

Sites

www.eda.org, www.vhdl.org, rassp.scra.org

8

Coursesanddocs

http://mikro.e9technik.uni9ulm.de/vhdl/vhdl_infos.html

VHDL coursemodules(3) at rassp.scra.org

8

References

VHDL LanguageReferenceManual,IEEEstandard1076

VHDL Cook 9book,PeterAshenden,Uni. Adelaide