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Introduction to VHDL ECOM 4311 Digital System Design
Introduction to VHDL
ECOM 4311
Digital System Design
2
Required reading
• P. Chu, RTL Hardware Design using VHDL
Chapter 2, Overview of Hardware Description
Languages
Chapter 3, Basic Language Constructs of VHDL
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4
5
6
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VHDL
• VHDL is a language for describing digital
hardware used by industry worldwide
• VHDL is an acronym for VHSIC (Very High
Speed Integrated Circuit) Hardware
Description Language
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VHDL Fundamentals
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Naming and Labeling (1)
• VHDL is case insensitive
Example:
Names or labels
databus
Databus
DataBus
DATABUS
are all equivalent
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Naming and Labeling (2)
General rules of thumb (according to VHDL-87)
1. All names should start with an alphabet character (a-z
or A-Z)
2. Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_)
3. Do not use any punctuation or reserved characters within a name (!, ?, ., &, +, -, etc.)
4. Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid)
5. All names and labels in a given entity and architecture must be unique
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Valid or invalid?
7segment_display
A87372477424
Adder/Subtractor
/reset
And_or_gate
AND__OR__NOT
Kogge-Stone-Adder
Ripple&Carry_Adder
My adder
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Free Format
• VHDL is a “free format” language
No formatting conventions, such as spacing or
indentation imposed by VHDL compilers. Space
and carriage return treated the same way.
Example: if (a=b) then
or if (a=b) then
or if (a =
b) then
are all equivalent
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Comments
• Comments in VHDL are indicated with
a “double dash”, i.e., “--” Comment indicator can be placed anywhere in the
line
Any text that follows in the same line is treated as
a comment
Carriage return terminates a comment
No method for commenting a block extending over a couple of lines
Examples:
-- main subcircuit
Data_in <= Data_bus; -- reading data from the input FIFO
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Comments
• Explain Function of Module to Other
Designers
• Explanatory, Not Just Restatement of Code
• Locate Close to Code Described
• Put near executable code, not just in a header
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Design Entity
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Example: NAND Gate
a b z
0 0 1
0 1 1
1 0 1
1 1 0
a
b z
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Example VHDL Code
• 3 sections to a piece of VHDL code
• File extension for a VHDL file is .vhd
• Name of the file should be the same as the entity name (nand_gate.vhd)
LIBRARY DECLARATION
ENTITY DECLARATION
ARCHITECTURE BODY
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
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Design Entity - most basic
building block of a design.
One entity can have many different architectures.
entity declaration
architecture 1
architecture 2
architecture 3
design entity
Design Entity
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ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC
);
END nand_gate;
Reserved words
Entity name Port names Port type
Semicolon
No Semicolon
after last port
Port modes (data flow directions)
Entity Declaration
• Entity Declaration describes the interface of
the component, i.e. input and output ports.
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ENTITY entity_name IS
PORT (
port_name : port_mode signal_type;
port_name : port_mode signal_type;
………….
port_name : port_mode signal_type);
END entity_name;
Entity declaration – simplified syntax
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a
Entity Port signal
Driver resides
outside the entity
Port Mode IN
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Entity
Port signal
Driver resides
inside the entity
Output cannot be read within
the entity
z
c <= z
c
Port Mode OUT
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Port signal
Entity
Driver resides
inside the entity
Signal x can be
read inside the entity
x
c
z
z <= x
c <= x
Port Mode OUT (with extra signal)
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Entity
Port signal
Driver resides
inside the entity
Port signal Z can be
read inside the entity
c
z
c <= z
Port Mode BUFFER
Not recommended
Problems reported with synthesis of designs using these ports.
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Signal can be
read inside the entity
Entity Port signal
Driver may reside
both inside and outside
of the entity
a
Port Mode INOUT
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Port Modes - Summary
The Port Mode of the interface describes the direction in which data travels with
respect to the component
• In: Data comes into this port and can only be read within the entity. It can
appear only on the right side of a signal or variable assignment.
• Out: The value of an output port can only be updated within the entity. It
cannot be read. It can only appear on the left side of a signal
assignment.
• Inout: The value of a bi-directional port can be read and updated within
the entity model. It can appear on both sides of a signal assignment.
• Buffer: Used for a signal that is an output from an entity. The value of the
signal can be used inside the entity, which means that in an assignment
statement the signal can appear on the left and right sides of the <=
operator. Not recommended to be used in the synthesizable code.
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Architecture (Architecture body)
• Describes an implementation of a design
entity
• Architecture example:
ARCHITECTURE model OF nand_gate IS
BEGIN
z <= a NAND b;
END model;
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Architecture – simplified syntax
ARCHITECTURE architecture_name OF entity_name IS
[ declarations ]
BEGIN
code
END architecture_name;
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Entity Declaration & Architecture
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY nand_gate IS
PORT(
a : IN STD_LOGIC;
b : IN STD_LOGIC;
z : OUT STD_LOGIC);
END nand_gate;
ARCHITECTURE dataflow OF nand_gate IS
BEGIN
z <= a NAND b;
END dataflow;
nand_gate.vhd
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Tips & Hints
Place each entity in a different file.
The name of each file should be exactly the same
as the name of an entity it contains.
These rules are not enforced by all tools
but are worth following in order to increase
readability and portability of your designs
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Tips & Hints
Place the declaration of each port,
signal, constant, and variable
in a separate line
These rules are not enforced by all tools
but are worth following in order to increase
readability and portability of your designs
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Example: Even parity detection circuit
• Input: a(2), a(1), a(0)
• output: even
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Even parity detection circuit
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Conceptual interpretation
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Even parity detection circuit
• Implicit δ-delay (delta delay)
Architecture xor_arch of even_detector is
Signal odd: std_logic;
begin
even <= not odd; -- implicit delta delay
odd <= a(2) xor a(1) xor a(0);
end xor_arch;
More efficient architecture which uses xor operator (entity declaration
is the same):
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Libraries
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VHDL Library
• A VHDL library is a place to store design
units
• The default library is ‟work‟
• Library “ieee” is used for many ieee
packages
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• Line 1: invoke a library named ieee
• Line 2: makes std_logic_1164 package
visible to the subsequent design units
• The package is normally needed for the
std_logic/std_logic_vector data type
VHDL Library Example
Lexical Elements
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Lexical elements
• Lexical element:
• Basic syntactical units in a VHDL program
• Types of Lexical elements:
• Comments
• Identifiers
• Reserved words
• Numbers
• Characters
• Strings
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Comments
• Starts with - -
• Just for clarity
• e.g.,
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Identifier
• Identifier is the name of an object
• Basic rules:
• Can only contain alphabetic letters, decimal
digits and underscore
• The first character must be a letter
• The last character cannot be an underscore
• Two successive underscores are not allowed
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Identifier
• Valid examples:
A10, next_state, NextState, mem_addr_enable
• Invalid examples:
sig#3, _X10, 7segment, X10_, hi_ _there
• VHDL is case insensitive:
• Following identifiers are the same:
nextstate, NextState, NEXTSTATE,
nEXTsTATE
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Reserved words
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Numbers, characters and strings
• Number: • Integer: 0, 1234, 98E7
• Real: 0.0, 1.23456 or 9.87E6
• Base 2: 2#101101#
• Character: • „A‟, „Z‟, „1‟
• Strings • “Hello”, “101101”
• Note • 0 and „0‟ are different
• 2#101101# and “101101” are different
Objects
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Objects
• A named item that hold a value of specific data type
• Four kinds of objects
• Signal
• Variable
• Constant
• File (cannot be synthesized)
• Related construct
• Alias
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Signal
• Declared in the architecture body's declaration
section
• Signal declaration: signal signal_name, signal_name, ... : data_type
• Signal assignment: signal_name <= projected_waveform;
• Ports in entity declaration are considered as signals
• Can be interpreted as wires or “wires with memory” (i.e.,
FFs, latches etc.)
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Variable
• Declared and used inside a process
• Variable declaration: variable variable_name, ... : data_type
• Variable assignment: variable_name := value_expression;
• Contains no “timing info” (immediate assignment)
• Used as in traditional PL: a “symbolic memory location”
where a value can be stored and modified
• No direct hardware counterpart
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Constant
• Value cannot be changed
• Constant declaration: constant const_name, ... : data_type :=
value_expression
• Used to enhance readability • E.g.,
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Alias
• Not an object
• Alternative name for an object
• Used to enhance readability • E.g.,
Data types and operators
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Data types and operators
We‟ll consider data types and operators in
each of
• Standard VHDL
• IEEE1164_std_logic package
• IEEE numeric_std package
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Data type
• Definition of data type
• A set of values that an object can assume.
• A set of operations that can be performed on
objects of this data type.
• VHDL is a strongly-typed language
• an object can only be assigned with a value of
its type
• only the operations defined with the data type
can be performed on the object
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Data types in standard VHDL
• integer:
• Minimal range: -(2^31-1) to 2^31-1
• Two subtypes: natural, positive
• boolean: (false, true)
• bit: ('0', '1')
• bit_vector: a one-dimensional array of bit
The bit type is not versatile enough to handle other
hardware values, high impedance (tri-state) and
wired-or structures (shorting)
We‟ll see std_logic defined later to handle this
problem
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Operators in standard VHDL
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Operators in standard VHDL
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Operators in standard VHDL
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IEEE std_logic_1164 package
• What‟s wrong with bit?
• New data type: std_logic, std_logic_vector
• To use:
library ieee;
use ieee.std_logic_1164.all;
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Standard Logic
• std_logic:
• 9 values: ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-')
'0', '1': forcing logic 0' and forcing logic 1
'Z': high-impedance, as in a tri-state buffer.
'L' , 'H': weak logic 0 and weak logic 1, as in wired-logic
'X', 'W': “unknown” and “weak unknown”
'U': for uninitialized
'-': don't-care.
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• an array of elements with std_logic data type
• Imply a bus
• E.g.,
signal a: std_logic_vector(7 downto 0);
Most significant bit is ‟labeled‟ 7 -- best
representation for numbers
• Another form (less desired)
signal a: std_logic_vector(0 to 7);
• Bits or a range of bits can be referenced as:
a(1)
a(7 downto 3)
Standard Logic Vectors
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Standard Logic Vectors
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= „1‟;
b <= ”0000”; -- Binary base assumed by default
c <= B”0000”; -- Binary base explicitly specified
d <= X”AF67”; -- Hexadecimal base
e <= O”723”; -- Octal base
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Modeling Wires and Buses
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0);
wire
a
bus
b
1
8
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Overloaded operators for IEEE std_logic_1164 package
• Which standard VHDL operators can be applied to std_logic and
std_logic_vector?
• Overloading: same operator of different data types
• Overloaded operators in std_logic_1164 package
• But the arithmetic operators are NOT!
• We‟ll take a look at conversions between signed and unsigned,
which do allow arithmetic operations, later in this slide set.
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Type Conversion
• Type conversion function in std_logic_1164
package:
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• E.g.,
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Operators over an array data type
• Several operators are defined over the 1-D
array data type, including
• Concatenation operator
• Relational operator
• Array aggregate operator
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Relational operators for array
• operands must have the same element type
but their lengths may differ
• Two arrays are compared element by element,
form the left most element
• All following returns true
• "011"="011", "011">"010", "011">"00010",
"0110">"011“
• Be careful -- this always returns false if sig1 is
shorter than sig2
if (sig1 = sig2) then
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Concatenation operator (&)
• Very useful operator -- can be used to shift
elements
• e.g.,
y <= "00" & a(7 downto 2);
y <= a(7) & a(7) & a(7 downto 2);
y <= a(1 downto 0) & a(7 downto 2);
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Array aggregate
• Aggregate is a VHDL construct to assign a value to an array-typed object
• E.g., a <= "10100000";
a <= (7=>'1', 6=>'0', 0=>'0', 1=>'0', 5=>'1', 4=>'0', 3=>'0', 2=>'1');
a <= (7|5=>'1', 6|4|3|2|1|0=>'0');
a <= (7|5=>'1', others=>'0');
• E.g., a <= "00000000"
a <= (others=>'0');
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IEEE numeric_std package
• How to infer arithmetic operators?
• In standard VHDL:
signal a, b, sum: integer;
. . .
sum <= a + b;
• But this is difficult to realize in hardware because
integer does NOT allow the range (number of
bits) to be specified
• We certainly don‟t want a 32-bit adder when an 8-
bit adder would do
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• Two new data types:unsigned and signed
• Both are defined as an array of elements with std_logic data type
• For signed, the array is interpreted in 2‟s-compliment format, with the MSB as the sign bit
IEEE numeric_std package
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IEEE numeric_std package
• Therefore, all of std_logic_vector, signed and unsigned are arrays of std_logic data type but they are treated as independent data types in VHDL
• This makes sense because they are interpreted differently, e.g., the bits "1100“ represent 12 when interpreted as an unsigned number but -4 as a signed number
ECE 448 – FPGA and ASIC Design with VHDL
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Overloaded operators in
IEEE numeric_std package
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Overloaded operators in
IEEE numeric_std package
• E.g.,
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Overloaded operators in
IEEE numeric_std package
• The relational operators, =, /=, <, >, <=, >=, are also
overloaded
• The overloading overrides the left-to-right, element-by-
element comparison procedure
• Instead, the two operands are treated as binary numbers
• For example:
-- return false if operands are either : std_logic_vector or
unsigned
"011" > "1000"
-- but returns true if operands are signed because 3 is
greater than -8!
ECE 448 – FPGA and ASIC Design with VHDL
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New functions in
IEEE numeric_std package
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Type conversion
• Std_logic_vector, unsigned, signed are
defined as an array of element of std_logic
• They considered as three different data types
in VHDL
• Type conversion between data types:
• type conversion function
• Type casting (for “closely related” data types)
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Type conversion between number-related
data types
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
. . .
signal s1, s2, s3, s4, s5, s6: std_logic_vector(3 downto 0);
signal u1, u2, u3, u4, u6, u7: unsigned(3 downto 0);
signal sg: signed(3 downto 0);
Example
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• Ok
u3 <= u2 + u1; --- ok, both operands unsigned
u4 <= u2 + 1; --- ok, operands unsigned and natural
• Wrong
u5 <= sg; -- type mismatch
u6 <= 5; -- type mismatch
• Fix
u5 <= unsigned(sg); -- type casting
u6 <= to_unsigned(5,4); -- conversion function
Example Continue….
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• Wrong
u7 <= sg + u1; -- + undefined over the types
• Fix
u7 <= unsigned(sg) + u1; -- ok, but be careful
• Wrong
s3 <= u3; -- type mismatch
s4 <= 5; -- type mismatch
• Fix
s3 <= std_logic_vector(u3); -- type casting
s4 <= std_logic_vector(to_unsigned(5,4));
Example Continue….
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• Wrong
s5 <= s2 + s1; + undefined over std_logic_vector
s6 <= s2 + 1; + undefined
• Fix
s5 <= std_logic_vector(unsigned(s2) + unsigned(s1));
s6 <= std_logic_vector(unsigned(s2) + 1);
Example Continue….
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?
Any Question
Finally!!
