Introduction to VLSI Introduction to VLSI ITI Ismailia Detailed Design Choose the design entry...

Introduction to VLSI ITI Ismailia

Introduction to VLSI

Dr. Hassan Mostafa

حسن مصطفى. د

[email protected]


Contents

CMOS Processing

Scaling

Memory Design: RAM/ROM

Controller: Finite-State Machines

Data-path: Shifters, Adders, Multipliers

Layout and Design Rules

Digital Implementation Strategies: ASIC/FPGA

SoC Subsystems




Design Rules

Interface between designer and process engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width scalable design rules: lambda parameter

absolute dimensions (micron rules)


CMOS Process Layers Layer Selection Window (LSW)

Layer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green


Intra-Layer Design Rules

Metal2 4

3

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole


Transistor Layout

1

2

5

3

Tra

nsi

sto

r


Via’s and Contacts

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


Select Layer

1

3 3

2

2

2

WellSubstrate

Select3

5


CMOS Inverter Layout

A A’

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A’

A A’


Contents

CMOS Processing

Scaling

Memory Design: RAM/ROM

Controller: Finite-State Machines

Data-path: Shifters, Adders, Multipliers


Digital Implementation Strategies: ASIC/FPGA

SoC Subsystems


FPGA Design Flow

Detailed (RTL)

Design

Design

Ideas

(Specifications)

Device

Programming

Timing

Simulation

Synthesis &

Implementation

Functional

Simulation

tpd=22.1ns fmax=47.1MHz

FPGA CPLD


Design Specification

What are the main design considerations?

Design feasibility?

- Performance

- power consumption

- cost

Design spec?

- Written (Document)

– Good starting point, but can be misinterpreted by design team

- Executable (UML, C/C++, Behavioral VHDL, SystemVerilog)

– Harder to understand, less room for misinterpretation

Implementation platform

- FPGA/CPLD?

- ASIC?

- Which FPGA/CPLD vendor?

- Which device family?

Development time?


RTL Specification

Determine I/O signals

Standard interface, protocol, custom interface

Partition design into functional blocks

Datapath, Control logic, Memory, etc.

Determine block interfaces

Specify each block separately at RTL

MUXs, counters, adders, flip-flops etc.


Detailed Design

Choose the design entry method

Schematic

- Intuitive & easy to debug

- Poor designer productivity (gates/time)

HDL (Hardware Description Language), e.g. Verilog, VHDL, SystemC

- Requires some experience, harder to debug

- Descriptive

- Easy to modify

- Greater productivity

Mixed HDL & schematic

Interpret the specifications

Manage the design hierarchy

Design partitioning

- Chip partitioning

- Logic partitioning

Use vendor-supplied IP libraries to reduce design time

Create & manage user-created libraries (circuits)


Functional Simulation

Preparation for simulation

Generate simulation patterns

- Waveform entry

- HDL testbench

Generate simulation netlist

Functional simulation

To verify the functionality of your design only

Simulation results

Waveform display

Text output

Self-checking testbench

Challenge

Sufficient & efficient test patterns


HDL Synthesis

Synthesis = Translation + Optimization

Translate HDL design files into gate-level netlist

Optimize according to your design constraints

- Area constraints

- Timing constraints

- Power constraints

Main challenges

Learn synthesizable coding style

Use proper design partitioning for synthesis

Specify reasonable design constraints

Use HDL synthesis tools efficiently

assign z=a&b

a

b z


Design Implementation

Implementation flow

Netlist merging, flattening, data base building

Design rule checking

Logic optimization

Block mapping & placement

Net routing

Configuration bitstream generation (FPGA only)

Scan flip-flop insertion (DFT Insertion) (ASIC only)

Implementation results

Design error or warnings

Device utilization (FPGA)

Die size (ASIC)

Timing reports

Challenge

How to reach high performance & high utilization implementation?

FPGA CPLD

a

b z

01011...


Timing Simulation (optional)

Post-layout simulation

Includes component and wire delays, clock skew, setup and hold times

Same input vectors with functional simulation

Not necessary if Static Timing Analysis shows no problems


Device Programming (FPGA only)

Choose the appropriate configuration scheme

SRAM-based FPGA/CPLD devices

- Downloading the bitstream via a download cable

- Programming onto a non-volatile memory device & attaching it on the circuit board

OTP, EPROM, EEPROM or Flash-based FPGA/CPLD devices

- Using hardware programmer

Finish the board design

Program the device

Challenge

Board design

System considerations

FPGA CPLD


Testing (ASIC only)

Find defects in chips that return from the foundry due to the manufacturing process

Identify differences between specification/verification/prototyping and manufactured ASIC


Common pitfalls/important points

Not detailed enough specifications

Do not start design entry until all details are clear

A poor design cannot be saved by good code and synthesis/implementation constraints

Sometimes though, it is better to let the tool do the optimization (for example state machines)

Always remember that you cannot prove a complex design has no bugs

For complex designs, verification (simulation) and redesign is 80% of total design time!


Design For Testability (DFT)


Boundary scan

In boundary scan, all flip-flops enter a test mode where they are controllable and observable

After functional verification, normal flip-flops are replaced by scan flip-flops

Only D flip-flops must be used

Clocks must not be generated internally


Built-In Self-Test (BIST)



More details….


ASIC Design Flow

ASIC tools are generally driven by scripts

Post-synthesis static timing analysis and equivalency checking are musts for sign off to foundry

Verification of deep sub-micron effects (second- and third-order effects) is required for ASICs

Internal, deep sub-micron effects are already verified for Xilinx FPGAs


FPGA Design Flow

FPGA tools are generally GUI-driven, pushbutton flows

FPGA tools also have scripting capabilities

After the design passes behavioral simulation and static timing analysis, verification is completed most efficiently by verifying in circuit

Static timing analysis is used to verify timing of the design

Timing simulation is supported

This is a simplified/typical design flow


ASIC Implementation

Create HDL

Optimized for ASIC technology and area

Synthesis

Primarily driven by scripts

Synopsys design compile

Design for test logic insertion (BIST, Scan, and JTAG)

Place & route

Foundry tools, Cadence, AVANT

BIST: Built-In Self Test

JTAG: Joint Test Action Group


FPGA Implementation

Create HDL

Optimized for Xilinx FPGAs and performance

Synthesis

Synopsys, Mentor

Pushbutton flow with scripting capabilities

Place & route

Completed by the user

Xilinx implementation tools

– ISE® software

Pushbutton flow, scripting capabilities


ASIC Verification

Key ASIC verification points

Behavioral simulation*

Post-synthesis static timing analysis

Post-synthesis equivalency checking

Post-place & route static timing analysis*

Post-place & route equivalency checking

Post-place & route timing simulation*

Verification of second- and third-order effects

Verify in circuit*

* Applies to both FPGA and ASIC design flows


FPGA Verification

Three key verification points for FPGA implementation

Behavioral simulation

Post-place & route static timing analysis

Download and verify in circuit

Post-synthesis gate-level simulation and post-place & route timing simulations can be done for production sign off

Post-place & route timing simulations are also often done to verify board- and system-level timing


Deep Sub-Micron Effects

Second- and third-order effects

Silicon-induced design flaws due to the small wire delays and narrow silicon of deep sub-micron processes

They include cross talk, interconnect delays, and Process variations

Xilinx FPGAs inherently have fewer deep sub-micron silicon issues

Pre-engineered standard product alleviates complex deep sub-micron design issues

Recovers design innovation time and facilitates time-to-market


Design for Test Logic

ASIC test-generation logic is not required in a Xilinx FPGA

Because of the capability to test in-circuit, automatic test pattern generation logic is normally not included

- This reduces the time spent on creating and inserting test logic, and allows more time to be spent “on the bench” testing the design

Xilinx FPGAs already contain JTAG (boundary scan) logic

Xilinx FPGAs have readback capability that is similar to scan logic

Readback can verify the configuration as well as the internal status of registers and memory


Firmware Development

Firmware development begins much earlier in the design cycle for FPGAs

No waiting time for prototypes

Hardware and software can develop in tandem

ASIC Design Flow


Design Flow Comparison

ASIC FPGA

Date post:	12-Aug-2020
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Introduction to VLSI Introduction to VLSI ITI Ismailia Detailed Design Choose the design entry...

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