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S3FM02G Inverter Motor Control (PMSM) Revision 1.00 February 2011 2011 Samsung Electronics Co., Ltd. All rights reserved.
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S3FM02G
Inverter Motor Control (PMSM)
Revision 1.00
February 2011
2011 Samsung Electronics Co., Ltd. All rights reserved.
Important Notice
The information in this publication has been carefully
checked and is believed to be entirely accurate at the
time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from the
use of the information contained herein.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
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guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of any
product or circuit and specifically disclaims any and all
liability, including without limitation any consequential
or incidental damages.
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
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Copyright 2011 Samsung Electronics Co., Ltd.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
Yongin-City, Gyeonggi-Do, Korea 446-711
Contact Us: [email protected]
TEL: (82)-(31)-209-4956
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Home Page: http://www.samsungsemi.com
Revision History
Revision No. Date Description Author(s)
1.00 Feb. 2011 Initial draft Juil Kim
Kwangsu Chun
Table of Contents
1 OVERVIEW OF S3FM02G ............................................................................. 1-1
2 SYSTEM ANALYSIS ..................................................................................... 2-1
2.1 S3FM02G Features ................................................................................................................................. 2-1 2.2 S3FM02G Pin Diagram ............................................................................................................................ 2-2 2.3 System Principle ...................................................................................................................................... 2-3 2.4 Inverter Motor Controller Block in S3FM02G ........................................................................................... 2-4 2.5 Encoder Block in S3FM02G ..................................................................................................................... 2-5 2.6 A/D Converter Block in S3FM02G ........................................................................................................... 2-6 2.7 Permanent Magnet Synchronous Motor .................................................................................................. 2-7
3 HARDWARE IMPLEMENTATION ................................................................. 3-1
3.1 Overview of Hardware Implementation .................................................................................................... 3-1 3.2 Voltage Sensing Circuit ............................................................................................................................ 3-2 3.3 Current Sensing Circuit ............................................................................................................................ 3-2 3.4 Intelligent Power Module Connection Circuit ........................................................................................... 3-3 3.5 Encoder Connection Circuit ..................................................................................................................... 3-3 3.6 Hall Sensor Connection Circuit ................................................................................................................ 3-3 3.7 Target Speed Setting Circuit .................................................................................................................... 3-4 3.8 Toggle Key Scan Circuit .......................................................................................................................... 3-4 3.9 Key Scan Circuit....................................................................................................................................... 3-4
4 SOFTWARE IMPLEMENTATION .................................................................. 4-1
4.1 Initialization Routine ................................................................................................................................. 4-1 4.2 Interrupt Routine ...................................................................................................................................... 4-6 4.3 Speed Calculation .................................................................................................................................... 4-7 4.4 Proportional and Integral Controller ......................................................................................................... 4-7
5 SYSTEM VALIDATION .................................................................................. 5-1
5.1 Test Criteria .............................................................................................................................................. 5-1 5.2 Interrupt Routine Time Measurement ...................................................................................................... 5-1
List of Figures
Figure Title Page
Number Number
Figure 2-1 S3FM02G Package Pin Assignments (128-ETQFP-1414) .............................................................. 2-2 Figure 2-2 Vector Control System Block ............................................................................................................ 2-3 Figure 2-3 Block Diagram of Inverter Motor Controller (IMC) ............................................................................ 2-4 Figure 2-4 Block Diagram of Encoder Counter .................................................................................................. 2-5 Figure 2-5 Block Diagram of A/D Converter ....................................................................................................... 2-6
Figure 3-1 Hardware Block................................................................................................................................. 3-1 Figure 3-2 Voltage Sensing Circuit .................................................................................................................... 3-2 Figure 3-3 Current Sensing Circuit ..................................................................................................................... 3-2 Figure 3-4 Intelligent Power Module Connection Circuit .................................................................................... 3-3 Figure 3-5 Encoder Connection Circuit .............................................................................................................. 3-3 Figure 3-6 Hall Sensor Connection Circuit ......................................................................................................... 3-3 Figure 3-7 Toggle Key Scan Circuit ................................................................................................................... 3-4 Figure 3-8 Toggle Key Scan Circuit ................................................................................................................... 3-4 Figure 3-9 Key Scan Circuit ............................................................................................................................... 3-4
Figure 4-1 Main Routine Flow Chart .................................................................................................................. 4-1 Figure 4-2 Interrupt Routine Flow Chart ............................................................................................................. 4-6
List of Conventions
Register RW Access Type Conventions
Type Definition Description
R Read Only The application has permission to read the Register field. Writes to read-only fields
have no effect.
W Write Only The application has permission to write in the Register field.
RW Read & Write The application has permission to read and writes in the Register field. The
application sets this field by writing 1’b1 and clears it by writing 1’b0.
Register Value Conventions
Expression Description
x Undefined bit
X Undefined multiple bits
? Undefined, but depends on the device or pin status
Device dependent The value depends on the device
Pin value The value depends on the pin status
Reset Value Conventions
Expression Description
0
1
x
Warning: Some bits of control registers are driven by hardware or write only. As a result the indicated reset
value and the read value after reset might be different.
List of Terms
Terms Descriptions
List of Acronyms
Acronyms Descriptions
S3FM02G_AN_REV 1.00 1 OVERVIEW OF S3FM02G
1-1
1 Overview of S3FM02G
The purpose of this application note is to describe how the S3FM02G can be used for inverter motor vector
control. Energy efficiency is an important reason for inverter motor vector control being popular.
Since S3FM02G can be operated in 75MHz with Cortex-M3 32-bit CPU core, DSP can be replaced with
S3FM02G for the most of vector controlled motor application. There are two special peripherals for motor
application such as Inverter Motor Controller (IMC) and Encoder (ENC) block. Even though IMC is specialized for
inverter motor, it can be used for all kinds of motor controller because IMC supports various type of PWM signal.
The target motor for this application note is Permanent Magnet Synchronous Motor (PMSM) with 8 poles. Encoder
calculates speed and position of target motor. The pulses per one revolution of encoder are 2000.
S3FM02G_AN_REV 1.00 2 SYSTEM ANALYSIS
2-1
2 System Analysis
2.1 S3FM02G Features
The key features of S3FM02G include:
Cortex-M3 CPU core
Built-in upto 384Kbyte Program Flash memory
Built-in upto 16Kbyte Data Flash memory
Internal upto 24KB SRAM for stack, data memory, or code memory
Interrupt controller: Dynamically reconfigurable Nested Vectored Interrupt Controller (NVIC)
Clock and Power Controller (CM)
10-ch DMA Controller (DMAC)
Watch-Dog Timer (WDT)
8-ch 16-bit Timer/Counters (TC)
32-bit Free-Running Timer (FRT)
8-ch 16-bit PWM
2-ch 16-bit Encoder Counter (ENC)
2-ch 6-Phase Inverter Motor Controller (IMC)
2-ch I2C, 2-ch SSP, 2-ch CAN and 4-ch USART
12-bit ADC (4 channels with OP-AMP)
10-bit ADC
5-ch OP-AMP
4com 40seg LCD Controller (LCDC)
Support Normal, High-speed, IDLE, and STOP mode
S3FM02G_AN_REV 1.00 2 SYSTEM ANALYSIS
2-2
2.2 S3FM02G Pin Diagram
S3FM02G
(128-ETQFP-1414)
12
6
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
33
34
35
36
37
38
39
40
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
10
8
10
9
11
0
11
1
11
2
11
3
11
4
11
5
11
6
11
7
11
8
11
9
12
0
12
1
12
2
12
3
12
4
12
5
12
7
nRESET
P2
.8/A
IN0
1
P1.23/OP0_O/USARTRXD1
SC
L0
/TC
AP
3/S
EG
7/P
0.1
4
21
22
23
24
25
26
27
28
29
30
31
32
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
85
86
87
88
90
91
92
93
94
95
96
89
97
98
99
10
0
10
1
10
2
10
3
10
4
10
5
10
6
10
7
12
8
XIN
XOUT
USARTRXD0/CLKOUT/VLCD1/P0.0
USARTTXD0/VLCD2/P0.1
USARTCLK0/TCAP7/VLCD3/P0.2
EXI14/TPWM7/COM0/P0.3
EXI15/TCAP6/COM1/P0.4
TPWM6/COM2/P0.5
TCAP5/COM3/P0.6
(for main IVC) VDDCORE1
ADTRG1/TPWM5/SEG0/P0.7
SSPFSS0/TCAP4/SEG1/P0.8
SSPCLK0/TPWM4/SEG2/P0.9
SSPMISO0/TCLK7/SEG3/P0.10
EX
I1/T
CL
K4
/SE
G6
/P0
.13
SD
A0
/TP
WM
3/S
EG
8/P
0.1
5
EX
I2/T
CL
K3
/SE
G9
/P0
.16
EX
I3/T
CL
K2
/SE
G1
0/P
0.1
7
CA
NT
X0
/TC
AP
2/S
EG
11
/P0
.18
CA
NR
X0
/TP
WM
2/S
EG
12
/P0
.19
US
AR
TC
LK
1/T
CL
K1
/SE
G1
3/P
0.2
0
US
AR
TR
XD
1/T
CA
P1
/SE
G1
4/P
0.2
1
US
AR
TT
XD
1/T
PW
M1
/SE
G1
5/P
0.2
2
PW
M0
/SE
G1
6/P
0.2
3
PW
M1
/SE
G1
7/P
0.2
4
PW
M2
/SE
G1
8/P
0.2
5
EX
I4/U
SA
RT
CL
K3
/SE
G1
9/P
0.2
6
US
AR
TR
XD
3/S
EG
20
/P0
.27
US
AR
TT
XD
3/S
EG
21
/P0
.28
PH
AS
EA
1/S
EG
22
/P0
.29
PH
AS
EB
1/S
EG
23
/P0
.30
PH
AS
EZ
1/S
EG
24
/P0
.31
SS
PM
OS
I1/S
EG
25
/P1
.0
SS
PM
ISO
1/S
EG
26
/P1
.1
SS
PC
LK
1/S
EG
27
/P1
.2
SS
PF
SS
1/S
EG
28
/P1
.3
SS
PM
OS
I0/S
CL
1/S
EG
29
/P1
.4
SS
PM
ISO
0/S
DA
1/S
EG
30
/P1
.5
SS
PC
LK
0/C
AN
RX
1/S
EG
31
//P
1.6
P1.24/OP0_N/USARTTXD1
P1.25/OP0_P/SDA0/SSPMOSI1
P1.26/OP1_O/SCL0/SSPMISO1
MODE0
MODE1
MODE2
P1.27/OP1_N/CANRX0/SSPCLK1
P1.28/OP1_P/CANTX0/SSPFSS1
P1.15/PWM1D2
P1.16/PWM1U2
P1.17/PWM1D1
P1.18/PWM1U1
P1.19/PWM1D0
P1.20/PWM1U0
P1.21/PWM1OFF
P1.14/SEG39/USARTCLK1/NMI
P1.29/OP2_O/USARTCLK0/ADTRG1
P1.30/OP2_N/USARTRXD0
AV
SS
1
AV
DD
1
P2.0/AIN10/OP3_O/EXI7
P2.1/AIN11/OP3_N/EXI8
P2.2/AIN12/OP3_P
P2.3/AIN13
P2.4/AIN14
P2.5/AIN15
P2
.9/A
IN0
2
P2
.10/A
IN0
3
P2
.11/A
IN0
4
P2
.12/A
IN0
5
P2
.13/A
IN0
6/O
P4
_O
/EX
I9
P2
.14/A
IN0
7/O
P4
_N
/EX
I10
P2
.15/A
IN0
8/O
P4
_P
/EX
I11
AV
SS
0
AV
DD
0
P2
.16/P
WM
0O
FF
P2
.17/P
WM
0U
0
P2
.18/P
WM
0D
0
P2
.19/P
WM
0U
1
P2
.20/P
WM
0D
1
P2
.21/P
WM
0U
2
P2
.22/P
WM
0D
2
P2
.23/P
HA
SE
A0
P2
.24/P
HA
SE
B0
P2
.25/P
HA
SE
Z0
XTIN
XTOUT
IVCOUT1
SS
PF
SS
0/C
AN
TX
1/S
EG
32
/P1
.7
EX
I5/U
SA
RT
CL
K2
/SE
G3
3/P
1.8
PW
M3
/US
AR
TR
XD
2/S
EG
34
/P1
.9
P1.11/SEG36/TCLK0/PWM5
P1.12/SEG37/TCAP0/PWM6
P1.13/SEG38/TPWM0/PWM7
P1.31/OP2_P/USARTTXD0
PW
M4
/US
AR
TT
XD
2/S
EG
35
/P1
.10
P1.22/ADTRG0/EXI6
TCK_SWCLK/P3.9
TMS_SWDIO/P3.8
TDI/P3.7
TDO_TRACESWO/P3.6
P3
.1/T
RA
CE
D2
P3
.0/T
RA
CE
D3
P2
.26/S
CL
1/E
XI1
2
P2
.27/S
DA
1/E
XI1
3
P3
.2/T
RA
CE
D1
P3
.3/T
RA
CE
D0
P3
.4/T
RA
CE
DC
LK
(for PLL IVC) VDDCORE2
VSS1
IVCOUT2
VDDIO1
VDDIO3
VSS3
AV
RE
F0
P2.7/AIN17
nTRST/P3.5
P2.6/AIN16
AVREF1
SSPMOSI0/TCLK6/SEG4/P0.11
EXI0/TCLK5/SEG5/P0.12
VD
DIO
2
VS
S2
VD
DIO
4
VS
S4
F_SCLK
F_SDAT
Figure 2-1 S3FM02G Package Pin Assignments (128-ETQFP-1414)
S3FM02G_AN_REV 1.00 2 SYSTEM ANALYSIS
2-3
2.3 System Principle
Figure 2-2 shows block diagram of vector control system.
PMSM
Speed
Controller1/ Kt
TorqueTarget SpeedDesired
Q current Q current
PI controller
D current
PI controller
Desired
D current
Q Voltage
D voltage
dq _to_
alphabeta
Transform
Alpha
Voltage
Beta
Voltage
alphabeta _
to _ abc
Transform
A Voltage
C voltage
B voltage PWM
generation
(IMC)
Inverter
Current
Sensing
(ADC)
Speed
Sensing
(ENC)
Rectifier
Power
supply
( AC)
Alpha
Current
Beta
Current
A Current
C Current
B Currentabc_to_
alphabeta
Transform
D Current
Q Current
alphabeta _
to_ dq
Transform
Power Module
Measured Speed
Figure 2-2 Vector Control System Block
In vector control there are several blocks such as:
Speed / Current PI controller
Current / Speed sensing part
abc_to_alphabeta transformation
alphabeta_to_dq transformation
dq_to_alphabeta transformation
alphabeta_to_abc transformation
PWM generation part
S3FM02G_AN_REV 1.00 2 SYSTEM ANALYSIS
2-4
2.4 Inverter Motor Controller Block in S3FM02G
Figure 2-3 Block Diagram of Inverter Motor Controller (IMC)
IMC block in S3FM02G is used for 6-ch PWM generation block. 6-ch PWM signal can be gate signal for inverter
switching element. The 6-ch PWM signals power on and power off the power transistor in sequence to generate
rotating magnetic flux. To support various types of motor both of triangular and saw tooth waveform are
supported. Set special function register to control powerful polarity, duty control and deadtime insertion.
PWMxOFF input pin in S3FM02G supports protection function for emergency such as short current and over
voltage. If emergency condition is met, IMC block makes 6-ch PWM signal floating.
Mode/
Polarity/
Dead-time
controller
16-bit
Comparator
INTInterrupt
Controller
PCLK
PWMxU0
mux
IMC_PACRR[15:0]: PACMPRDAT
IMC_PACFR[15:0]: PACMPFDAT
IMC_PBCRR[15:0]: PBCMPRDAT
IMC_PBCFR[15:0]: PBCMPFDAT
IMC_PCCRR[15:0]: PCCMPRDAT
IMC_PCCFR[15:0]: PCCMPFDAT
IMC_TCR[15:0]: TOPCMPDAT
IMC_ASTSR.1: 0SEL
IMC_ASCRR0[15:0]: ADCMPR0DAT
IMC_ASCFR0[15:0]: ADCMPF0DAT
IMC_ASCRR1[15:0]: ADCMPR1DAT
IMC_ASCFR1[15:0]: ADCMPF1DAT
IMC_ASCRR2[15:0]: ADCMPR1DAT
IMC_ASCFR2[15:0]: ADCMPF1DAT
16-bit
Comparator
IMC_DTCR[15:0]: DTCMPDAT
IMC_CR0.1: IMMODE
IMC_CR0.3: PWMSWAP
IMC_CR0.4: PWMPOLU
IMC_CR0.5: PWMPOLD
IMC_CR0[24:20]: NUMSKIP
INTPND
INTMASK
ADC0 start
SignalTo ADC0 block
IMC_ASTSR[7:0]
IMC_SR.0: FAULTSTAT
IMC_CR1[5:0]
PWMxD0
PWMxU1
PWMxD1
PWMxU2
PWMxD2
IMC_CR0[18:16]: IMCLKSEL
3-bit
Prescaler
IMC_CR0.0: IMEN
Clear
16-bit Up/Down Counter
IMC_CNTR[15:0]: CV
Clear
IMCLK
IMC_SR.1: UPDOWN
Filter
IMC_CR0[7:6]: ESELPWMOFF
PWMxOFF
IMC_CR0[12]: PWMOFFEN IMC_CR0[10:8]: IMFILTER
IMC_CR0[13]: PWMOUTOFFEN
INT_FAULTINTPND
INTMASK
IMC_CR0[14]: PWMOUTEN
From OP-AMP
block
IMC_SR.2: OPAMPEDGEDET
IMC_CR0[15]: PWMOFFENBYOPAMP
(Total 8 ea)
IMC_CR0[13]: PWMOUTOFFEN
S3FM02G_AN_REV 1.00 2 SYSTEM ANALYSIS
2-5
2.5 Encoder Block in S3FM02G
Figure 2-4 Block Diagram of Encoder Counter
ENC block in S3FM02G is used to sense rotor position of motor, rotating direction and speed information. The
ENC block in S3FM02G supports two kinds of functionality such as high speed and low speed. For high speed,
phase A, phase B and phase Z signals are counted and counted value is saved in position counter register and
speed counter register. For low speed, capture function and saved PA/ PB capture register measures the width of
phase A and phase B.
16-bit Up/ Down Counter(Position Counter)
PCV.15-. 0 : PCR
ENC_CR0.6-.4: ENCFILTER
PHASEA
PHASEB
PHASEZ
16- bit Up/ Down Counter
(Speed Counter)
SCV .15- . 0 : SPCRENC_CR0.1: SPCRCL
ENC_CR0.0 : PCRCL
ENCCLKClear
4-bit
Prescaler
ENCCLK Clear
ENC_CR1.9: PAEN
ENC_CR1.8: PACNTCL
ENC_CR1. 0: PBCNTCL
ENC_CR1.1: PBEN
PACLK
PBCLK
Clear
Clear
16-bitComparator
16-bitComparator
16- bit Reference Register
( Speed Reference)
SREFDAT.15-.0: SPRR
ENC_CR0.7: PZCLEN
16- bit Reference Register(Position Reference)
PREFDAT.15-.0 : PRR
ENC_RISR.0Clear
4-bitPrescaler
PA Capure Data Register
PACDAT.15- .0: PACDR
Clear
ENC_CR1. 8: PACNTCL
ENC_CR1.0 : PBCNTCL
ENC_CR1.11-. 10 : ESELA
ENC_CR1.3-.2 : ESELB
ENC_IMSCR.0
Clear
Clear
Clear
ENC_CR0.3: ESELZ
16- bit Up Counter
PACCV. 15- .0 :PACCR
PB Capure Register
PBCAP. 15-.0: PBCDR
FilterEdge
selector
16- bit Up Counter
PBCNT.15-0:PBCCR
ENC_MISR.0(PAOVF)
ENC_RISR.1
ENC_IMSCR.1
ENC_MISR.1(PACAP)
ENC_RISR.2
ENC_IMSCR.2
ENC_MISR.2(PBOVF)
ENC_RISR.3
ENC_IMSCR.3
ENC_MISR.3
(PBCAP)
ENC_RISR.4
ENC_IMSCR.4
ENC_MISR.4(PCMAT)
ENC_RISR.5
ENC_IMSCR.5
ENC_MISR.5(SCMAT)
ENC_RISR.7
ENC_IMSCR.7
ENC_MISR.7
(PHASEZ)
S3FM02G_AN_REV 1.00 2 SYSTEM ANALYSIS
2-6
2.6 A/D Converter Block in S3FM02G
OP_AMP3
SHA0
AIN01
INT_OVR0
Calibration 0
0000
Channel Selection
ADC_CRR0[11:0]
Conversion Data
0001
0010
0011
0100
0101
0110
0111
1000
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN00
12-bit
ADC00
Calibration En/Disable
INT_EOC0
IMCR: Interrupt Mask
Control Register
Conversion
Start
TRIG0
(Trigger SEL)
Tim
er M
atch
(H/W
)
IMC
AD
C T
rigg
er (H
/W)
AD
TR
G_
R?
F/B
(H/W
)
ST
AR
T (S
/W)
OP_AMP4
SHA1
AIN01
INT_OVR1
Calibration 1
0000
Channel Selection
ADC_CRR1[11:0]
Conversion Data
0001
0010
0011
0100
0101
0110
0111
1000
AIN02
AIN03
AIN04
AIN05
AIN06
AIN07
AIN08
AIN00
12-bit
ADC01
Calibration En/Disable
INT_EOC1
IMCR: Interrupt Mask
Control Register
Conversion
Start
TRIG1
(Trigger SEL)
Tim
er M
atch
(H/W
)
IMC
AD
C T
rigg
er (H
/W)
AD
TR
G_
R?
F/B
(H/W
)
ST
AR
T (S
/W)
1001
1010
OP_AMP2
OP_AMP4
1001
1010
OP_AMP2
OP_AMP3
AIN09
AIN0A
AIN09
AIN0A
1011OP_AMP1AIN0B
1011OP_AMP1AIN0B
Figure 2-5 Block Diagram of A/D Converter
The S3FM02G has two 12-bit ADC. It converts the analog input signal into 12-bit binary digital codes at a
maximum sampling rate of 5MHz. Maximum DNL error is 1.5 LSB and Maximum INL is 3.5 LSB.
The ADC block in S3FM02G is used for sensing current. Conversion type is 1us. The maximum ADC clock is
4MHz.
S3FM02G_AN_REV 1.00 2 SYSTEM ANALYSIS
2-7
2.7 Permanent Magnet Synchronous Motor
PMSM is the synchronous AC motor. A PMSM motor is similar to BrushLess DC (BLDC) motor. However, the
shape of back EMF is different. PMSM is sinusoidal and BLDC is trapezoidal. PMSM motor requires phase control
for getting constant torque because back EMF is sinusoidal.
S3FM02G_AN_REV 1.00 3 HARDWARE IMPLEMENTATION
3-1
3 Hardware Implementation
3.1 Overview of Hardware Implementation
There are several circuits in inverter motor control. This chapter describes voltage sensing circuit, current sensing
circuit, IPM connection circuit, ENC connection circuit and key scan circuit. Figure 3-1 shows hardware block.
PM
SM
IPM drive protection
circuit
Inverter
CurrentSensing
RectifierPower supply(AC)
Key
Scan
Power Module
VoltageSensingCircuit Circuit
ENC 0/1
4 x 40 LCD
PWM 0~7
Crystal/
Ceramic
Oscillator
AHB
PLL
SRAM
(24KB)
Flash-ROM
(384KB)
SSP 0/1
BRIDGE
IO
CONTROL
APB
IMC 0/1
Interruptcontroller
S3FM02G
Vbus
Encoder
Cortex-
M3 Core
12 bit
ADC 0/1
Timer 0~7
I2C 0/1
USART
0/1/2/3CAN 0/1
OP amp
0~4
Figure 3-1 Hardware Block
S3FM02G_AN_REV 1.00 3 HARDWARE IMPLEMENTATION
3-2
3.2 Voltage Sensing Circuit
If AC is 220V, Vbus is 220 1.414. If R1is 1097.8k and R2 is 12.4k, the voltage to ADC is 3.474V. Because
ADC input can be 5V, 450V is the maximum value for Vbus. Figure 3-2 shows the voltage sensing circuit.
Vbus
( to AIN04)
Vadc _voltage
12.4K
R1
R2
1097.8K
Figure 3-2 Voltage Sensing Circuit
3.3 Current Sensing Circuit
Because current sensing voltage is small, the internal OP-AMP is used to amplify the sensing voltage. The gain of
internal op amp is set to 7.09. OP1_P is for PhaseA, OP2_P is for PhaseB and OP3_P is for PhaseC. Figure 3-3
shows current sensing circuit.
5V
68K
5.1K
( to OP1_P(P1.28),Vsense
Vadc_current240
4700pOP2_P(P1.31),OP3_P(P2.2))
Figure 3-3 Current Sensing Circuit
S3FM02G_AN_REV 1.00 3 HARDWARE IMPLEMENTATION
3-3
3.4 Intelligent Power Module Connection Circuit
The Intelligent Power Module (IPM) includes several power transistors. IPM supports protection function such as
short circuit and under voltage. The control signals in S3FM02G for power transistor (IMC output signals:
PWMxU0/1/2, and PWMxD0/1/2) are connected to IPM input signals. To ensure 6-ch PWM signal is floating,
protection signal of IPM is connected to PWMxOFF signal of S3FM02G. Figure 3-4 shows IPM connection circuit.
IPM
PWMxU0PWMxD0PWMxU1PWMxD1PWMxU2PWMxD2
PWMxOFF
S3FM02G
Phase APhase BPhase C
Motor
Figure 3-4 Intelligent Power Module Connection Circuit
3.5 Encoder Connection Circuit
Encoder has three output pins, namely, Channel A, Channel B and index Z. Figure 3-5 shows encoder connection
circuit.
Channel A
Encoder
Phase A
Phase B
Phase Z
S3FM02G
Channel B
Index Z
Figure 3-5 Encoder Connection Circuit
3.6 Hall Sensor Connection Circuit
Hall sensor has three output pins, namely, Phase A, Phase B and Phase C. Hall sensor signals are used for
initialization of rotor position angle and clear rotor position angle at the rising edge of phase A. Figure 3-6 shows
encoder connection circuit.
Channel A
Encoder
Phase A
Phase B
Phase Z
S3FM02G
Channel B
Index Z
Figure 3-6 Hall Sensor Connection Circuit
S3FM02G_AN_REV 1.00 3 HARDWARE IMPLEMENTATION
3-4
3.7 Target Speed Setting Circuit
To set target speed, variable resistor and ADC block are used. Figure 3-7 shows toggle key scan circuit.
5V
AIN1310KR1
Figure 3-7 Toggle Key Scan Circuit
3.8 Toggle Key Scan Circuit
To start motor and set direction of motor rotation, toggle key scan circuit is implemented. Figure 3-8 shows toggle
key scan circuit.
5V
(to P0.24 for Run/Stop,
P0.25 for CW/CCW)
Switch input
10KR1
0.01uC1
Figure 3-8 Toggle Key Scan Circuit
3.9 Key Scan Circuit
To clear fault status flag, key scan circuit is implemented. If fault condition was disappeared and flag is cleared,
motor can be re-stared. Figure 3-9 shows key scan circuit.
5V
(to P0.20)Switch input
10KR1
0.01uC1
Figure 3-9 Key Scan Circuit
S3FM02G_AN_REV 1.00 4 SOFTWARE IMPLEMENTATION
4-1
4 Software Implementation
4.1 Initialization Routine
The function of main routine is to initialize system, key scan and fault checking. Key bouncing technique is
included in the key scan routine. Figure 4-1 shows the main routine flow chart.
main
LED toggle
command handling
I/O status checking
Figure 4-1 Main Routine Flow Chart
S3FM02G_AN_REV 1.00 4 SOFTWARE IMPLEMENTATION
4-2
In the variable initialization routine, all variables related to system status, voltage, current, torque, position, speed
and low pass filter coefficient are initialized, as in the following example.
enc.Elec_Offset_CMD = 0x0;
enc.EncPulse = 2000; // ppr
mot.Pole = 8;
mot.Irated_A = 2.1;
mot.I_MAX = 9.375;
mot.Trated_Nm = 0.672966;
mot.MotorL_mH = 8.1;
mot.MotorR_ohm = 1.34;
mot.MotorJ_kgm21e_4 = 0.096938776; // kg m^2 1e-4
mot.Rpm_Rated_rpm = 3000.0;
mot.Rpm_Max_rpm = 5000.0;
mot.Kt = mot.Trated_Nm / mot.Irated_A;
mot.I_Band_Width_RpS = 3000.0; // [rad/sec]
mot.Current_Ts = 0.0001; // [sec]
mot.S_Band_Width_Hz = 100.0; // [Hz]
mot.Speed_Ts = 0.001; // [sec]
enc.Float_S_dGain = 0.1; // [%]
lpf.Tsamp_SPEED = 0.001; // [sec]
lpf.Tsamp_CURRENT = 0.0001; // [sec]
lpf.Tsamp_1msec = 0.001; // [sec]
lpf.Tc_Vdc = 0.001; // [sec]
lpf.Tc_Speed = 0.003; // [sec]
lpf.Tc_3msec = 0.003; // [sec]
In the peripheral initialization routine, The operating mode is set to high speed and system clock is set to 75MHz
using 8MHz crystal oscillator, as in the following example.
clock_init(SysPLLCLK, 0, 0, PMS(6, 67, 0)); /* HCLK(75Mhz), PCLK(75Mhz) */
S3FM02G_AN_REV 1.00 4 SOFTWARE IMPLEMENTATION
4-3
IMC is set to triangular mode, immediate write mode and PWM output off enable. ADC trigger signal is set to IMC
counter zero point. Because TOPCMP is set to 3750, the period of current control is set to 100us.
CSP_IMC_SET_CEDR(IMC1, IMC_CLKEN); // clock enable
if (!(CSP_IMC_GET_CEDR(IMC1) & IMC_CLKEN)) error_u32++;
CSP_IMC_SET_SRR(IMC1, IMC_SWRST); // software reset
CSP_IMC_SET_CR0(IMC1, IMC_IMEN | IMC_WMODE | IMC_PWMPOLD | IMC_PWMSWAP | IMC_ESELPWMOFF(0x0)|
IMC_PWMOFFEN |IMC_PWMOUTOFFEN |IMC_SYNCSEL(0x1) );
PWM_OFF();
NVICConfig.NVIC_IRQChannel = NVIC_IMC1;
NVICConfig.NVIC_IRQChannelPreemptionPriority = 0;
NVICConfig.NVIC_IRQChannelSubPriority = 0;
NVICConfig.NVIC_IRQChannelCmd = ENABLE;
CSP_NVICConfigInterrupt(&NVICConfig);
CSP_IMCConfigInterrupt(IMC1, (IMC_FAULT|IMC_ZERO) , ENABLE);
CSP_IMC_SET_TCR(IMC1, PWM_Period);
CSP_IMC_SET_DTCR(IMC1, Dead_Time);
CSP_IMC_SET_ASTSR(IMC1, IMC_0SEL);
Signal from IMC block initiates ADC and initiates DMA block for reading ADC result.
CSP_ADC0_SET_SRR(ADC0, ADC0_SWRST);
CSP_ADC0_SET_CEDR(ADC0, ADC0_CLKEN); // ADC0 Clock Enable
CSP_ADC0_SET_CSR(ADC0, (ADC0_ADCEN0|ADC0_ADCEN1) ); // ADC0 Macro Engine Enable
while( !( CSP_ADC0_GET_SR( ADC0 ) & ADC0_ADCSTABLE0 ) );
while( !( CSP_ADC0_GET_SR( ADC0 ) & ADC0_ADCSTABLE1 ) );
CSP_ADC0_SET_CDR(ADC0, ADC0_CDIV(0xE)); //(ADC0, div(75[MHz]/(14+1)=5[MHz]), ch, trig, cnt);
// ADC0 clock divider
CSP_ADC0_SET_CCSR0(ADC0, (ADC0_ICNUM0(0x1)) | ADC0_ICNUM1(0x3) );
CSP_ADC0_SET_CCSR1(ADC0, (ADC0_ICNUM0(0x2)) );
CSP_ADC0_SET_MR(ADC0, (ADC0_TRIG0(ADC0_IMC1)| ADC0_CCNT0(0x1)) |(ADC0_TRIG1(ADC0_IMC1)|
ADC0_CCNT1(0x0)) ) ;
CSP_ADC0_SET_DMACR(ADC0, ADC0_DMAE0);
CSP_DMADisableChannel(1);
pSrc_u32 = (U32_T *)(ADC0_BASE_ADDRESS + 0x038);
pDest_u32 = (U32_T *)(&ADC0_Result[0]);
CSP_DMAAddressConfiguration(1, (U32_T)pSrc_u32, (U32_T)pDest_u32);
/* Increment option configuration for source address */
high_addr_control_src =1;
low_addr_control_src =1;
CSP_DMASrcAddressControl(1, high_addr_control_src, low_addr_control_src);
/* Increment option configuration for destination address */
high_addr_control_dest = 0;
low_addr_control_dest = 0;
CSP_DMADestAddressControl(1, high_addr_control_dest, low_addr_control_dest);
/* Data Size Selection */
S3FM02G_AN_REV 1.00 4 SOFTWARE IMPLEMENTATION
4-4
data_size =0x1;
CSP_DMADataSizeConfiguration(1, data_size);
/* Transfer Count */
high_transfer_count =1;
low_transfer_count =2;
CSP_DMATransferCountConfiguration(1, high_transfer_count, low_transfer_count);
/* Auto-Reload Enable/Disable Configuration */
auto_reload = 1;
CSP_DMAAutoReload(1, auto_reload);
/* Selection service mode single or continuous mode */
serv_mode =0;
CSP_DMAServiceModeConfiguration(1, serv_mode);
/* Selection transfer size unit or burst */
trans_mode =0;
CSP_DMATransferSizeConfiguration(1, trans_mode);
/* Trigger Type Selection, Software or Hardware */
CSP_DMATriggerTypeConfiguration(1, Hardware);
/* Hardware Trigger Source Selection */
CSP_DMAHardwareTrigConfiguration(1, 0x16);
/* Interrupt Enable/Disable Selection */
CSP_DMAConfigChannelInterrupt(1, DISABLE, DISABLE);
CSP_DMAEnableChannel(1);
Timer 2 is set to 1ms interval mode for speed control, as in the following example.
CSP_TC16Init(TC2);
CSP_TC16Configure(TC2, scntsiz, sclkdiv, TC16_REPEAT|TC16_STOPCLEAR, speriod);
NVICConfig.NVIC_IRQChannel = NVIC_TC2;
NVICConfig.NVIC_IRQChannelPreemptionPriority = 2;
NVICConfig.NVIC_IRQChannelSubPriority = 0;
NVICConfig.NVIC_IRQChannelCmd = ENABLE;
CSP_NVICConfigInterrupt(&NVICConfig);
CSP_TC16ConfigInterrupt(TC2, TC16_PENDI, ENABLE); //interrupt
CSP_TC16Enable(TC2);
S3FM02G_AN_REV 1.00 4 SOFTWARE IMPLEMENTATION
4-5
P0.20 ~ P0.25 are used for key scan. P0.20 ~ P0.23 detect edge of key. P0.24 and P0.25 detect level of key, as
in the following example.
void Read_IO(){
U16_T IO_Read_tmp;
IO_Read_tmp = ( (CSP_GPIO_GET_PDSR(GPIO0) >> 20) & 0x3f ) | ((CSP_GPIO_GET_PDSR(GPIO2) >>1) &
0x8000) ;
if(IO_Read_Buffer == IO_Read_tmp){
if(IO_Read_Cnt == 10){IO_State.Read_GPIO.all = IO_Read_Buffer;}
else{IO_Read_Cnt++;}
}
else{
IO_Read_Cnt = 0;
IO_Read_Buffer = IO_Read_tmp;
}
if(!IO_State.Read_GPIO.bit.SEL0 && DRIVE_State.STATUS_BIT.bit.Ready){
OP_CMD.PWM_On_Off = ENABLE_STATUS;
}
else{OP_CMD.PWM_On_Off = DISABLE_STATUS;}
}
S3FM02G_AN_REV 1.00 4 SOFTWARE IMPLEMENTATION
4-6
4.2 Interrupt Routine
There are two main interrupt routine for vector control algorithm, namely, Zero Interrupt of IMC interrupt for current
control and Timer interrupt for 1ms speed control. Figure 4-2 shows flow chart of interrupt routine.
Timer ISR
Speed
measurement
Speed PI
control
Iq setting
IRET
IMC Zero ISR
DC bus voltage
sensing
Encoder position sensing
abc_to_alphabeta transformation
alphabeta _dq transformation
PWM generation
IRET
Over-current
Detected?
Current d PI controlCurrent q PI control
Dq_to_alphabeta transformationalphabeta_abc transformation
Sin/Cos
calculation
ADC EOC set?No
Yes
Yes
Current sensing
Current offset
Calibration Done?
Current offset
calibration
No
IRET
Fault Flag Set
Yes
IRET
No
(M/T method)
(SVPWM)
Figure 4-2 Interrupt Routine Flow Chart
S3FM02G_AN_REV 1.00 4 SOFTWARE IMPLEMENTATION
4-7
4.3 Speed Calculation
Speed control routine is executed at every 1ms. Speed can be calculated by counting encoder pulses and time for
1ms. Equation to measure rpm speed is as follows:
MeasuredSpeed = CountedPulse MT_SCALE / CapturedTime;
SCALE is defined by ‘enc.F0S_mtfactor = 60 CaptureClock 4 PULSES_PER_REVOLUTION’ in the
Main_init.c file. CaptureClock is 75000000 (= 75MHz) and PULSES_PER_REVOLUTION is 2000.
4.4 Proportional and Integral Controller
Proportional and Integral (PI) is used for current/ speed control.
Proportional control reduces error. The proportional term changes the output that is proportional to the current
error value. To adjust the proportional responses multiply the error by a constant Kp, known as proportional gain.
Integral control reduces or eliminates steady state errors. Summing the instantaneous error over time (integrating
the error) gives the accumulated offset that should have been corrected previously. The accumulated error is then
multiplied by the integral gain and added to the controller output. The integral gain, Ki determines the magnitude of
contribution of the integral term to overall control action.
S3FM02G_AN_REV 1.00 5 SYSTEM VALIDATION
5-1
5 System Validation
5.1 Test Criteria
To start the PMSM motor, toggle SEL1 (P0.24) key. To change the direction of motor, toggle SEL2 (P0.25). To
change the speed of motor, rotate VR1. Target speed of motor is from 25rpm to 3000rpm.
5.2 Interrupt Routine Time Measurement
Use port toggle to measure the time of current/speed control interrupt routine.
Current control routine (ISR_IMC_PWM_IMC1 routine, IMC_ZERO): 9us
Speed control routine (ISR_TMR16_SPD_TC2 routine): 5us
