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Liao 1 Isolated Buck-Boost Converter with NI myRIO Control ECE469 Final Project Report 12/18/2014 Zitao Liao Partner: Yukun Ren, TA: Yue Cao
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Page 1: Isolated Buck-Boost Converter with NI myRIO Controlliaozitao.org/blog/final project.pdf · Liao 1 Isolated Buck-Boost Converter with NI myRIO Control ECE469 Final Project Report 12/18/2014

Liao

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Isolated Buck-Boost Converter with NI

myRIO Control

ECE469 Final Project Report

12/18/2014

Zitao Liao

Partner: Yukun Ren, TA: Yue Cao

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CONTENTS

Abstract ......................................................................................................................................................... 3

1. Design Process .......................................................................................................................................... 3

1.1 Design Specifications .......................................................................................................................... 3

1.2 Topology Simulation and Current Mode Selection ............................................................................ 3

1.3 Discrete Components Selection .......................................................................................................... 6

1.3.1 MOSFET ...................................................................................................................................... 6

1.3.2 Output Diode ................................................................................................................................ 7

1.3.3 Input Interface Capacitor ............................................................................................................. 7

1.3.4 Output Capacitor .......................................................................................................................... 7

1.4 Transformer Design ............................................................................................................................ 8

1.5 Feedback Control Design .................................................................................................................. 10

1.5.1 Control Algorithm ...................................................................................................................... 10

1.5.2 NI myRIO and LabVIEW GUI ................................................................................................... 11

1.6 Final Package and Demo Setup ........................................................................................................ 14

2. Test Results Discussion .......................................................................................................................... 15

2.1 Efficiency .......................................................................................................................................... 15

2.2 Input Step Response .......................................................................................................................... 18

2.3 Transformer Performance ................................................................................................................. 18

2.4 Input Voltage Disturbance Rejection ................................................................................................ 20

3. Conclusions and Future Improvements ................................................................................................... 21

4. Reference ................................................................................................................................................ 22

Appendix ..................................................................................................................................................... 23

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ABSTRACT

A fly-back DC-DC converter operating in Discontinuous Current Mode was built for ECE469-

Power Electronics Lab final project. The converter was designed with specifications listed in the

lab manual. The design process includes topology selection, simulation, discrete components

selection, transformer design and feedback control design. The National Instrument myRIO and

labVIEW were used to implement the close-loop control, which provided friendly development

environment for tuning various parameters in the control system software. This report will cover

every aspect of the design process stated above and give theoretical analysis and explanation to

the test results and performances of the converter, as well as discuss rooms for future

improvements.

1. DESIGN PROCESS

1.1 Design Specifications

The converter specifications are listed in the table below.

Table 1. Converter Specifications

Input Voltage 10V to 18V

Output Voltage 13.8V ±1% (Isolated)

Load Range 0W to 50W

The challenges associated with such specifications are output voltage ripple control, transformer

current saturation limit design, device rating design, and among others.

1.2 Topology Simulation and Current Mode Selection

Since it is required that the converter should accept input from 10V to 18V and generate an isolated

output voltage of 13.8V, a fly-back converter topology shown in Figure. 1 is chosen such that the

converter can step up and down voltages and isolate input and output with the transformer in

between.

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For a fly-back converter, the transformer can operate in two different inductor current modes:

Continuous Current Mode and Discontinuous Current Mode. Both modes will work to create the

required voltage. In Continuous Current Mode (CCM), the inductor current never falls to zero,

while in Discontinuous Mode (DCM), the inductor current falls to zero during the period that the

input-side switch is off. The differences between these two modes should be considered during

actual transformer design, which will be discussed later. The critical inductance of this converter

system, which is the inductance that allows operation at the boundary of DCM and CCM, is

calculated under the condition of 10V input, maximum load and switching frequency at 25 KHz.

𝐿 =𝑅𝑙𝑜𝑎𝑑𝑇

2(1−𝐷)2 (1)

𝑉𝑜𝑢𝑡 =𝑉𝑖𝑛∗𝐷

1−𝐷 (2)

The result turned out to be around 14µH. Simulations are setup in LTSPICE for both current modes

with transformer inductance being less (11.5 µH) and greater (100 µH) than 14 µH.

Figure 1. Fly-back Converter Topology [4]

Figure 2. Simulation Circuit (CCM)

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Figure 3.1. DCM Step Response Figure 3.2. CCM Step Response

As can be obviously seen from Figure 3, though both showed large overshoot, the CCM step

response has much longer settling time because of larger inductors’ charging and discharging time.

Another point to be noticed is that DCM provides a higher output voltage under the same switching

duty cycle. This simulation results are consistent with the conclusion from [2] that DCM has

advantages over CCM in the following aspects: 1. Fast response; 2. Only a small inductor is needed

(much fewer turns); 3. DCM tends to provide higher output voltage, thus it’s especially suitable

for boost converter applications.

The trade-offs were hard to decide. As stated in [2], first of all it’s harder to achieve load regulation

in DCM, and this can be proved later in the control algorithm design process. Second, high current

variation in inductor will increase losses in magnetic parts, and can lead to magnetic saturation,

though in this application the current should not be high enough to cause core saturation. While in

CCM, though the leakage inductance is lower and current variation is milder, the large inductance

value requires more turns of wire, which, first of all, will be hard to manufacture because of the

limitation of window area of core geometry. Second, longer wire will introduce larger series

resistance and generate resistive heat loss.

The CCM and DCM transformers were both designed and tested later in the actual project and

results will be discussed in later chapters.

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1.3 Discrete Components

This project requires the discrete components selected to be able to handle extreme operating

conditions. The actual specifications of the components should be higher than the theoretical

limitations because unideal devices, poor connections, ground-loops and many other unstable

factors during design process can lead to overshoot of current or voltage. Below is the table for all

the discrete components chosen to be applied in this project and design considerations for each of

them will be discussed in sub-chapters

Component Part number Quantity Spec (where applicable)

Power MOSFET MTP36N06V 1 32 , 60d dsI A V V

Low-side gate driver 4424BN(non-inverting) 1

Diode 1N5822 2 , 3 , 0.525f AVE fwdI A V V

Capacitor (Input/output) Electrolytic cap 2 1 mF

Magnetic Core P36/22-3F3-E40 1 400 3% , 84L eA nH

1.3.1 MOSFET

The MOSFET on the input side should be able to block input voltage when the switch is off and

should be able to carry peal current under DCM.

These requirements lead to the design specifications of the MOSFET that Its Vds should be higher

than 20V and should be able to handle around 30A (current calculation can be found in the 2.3)

Among the available parts in the Power Lab, MTP36N06V meets the requirements as it can handle

continuous current of 32A and can block up to 60V.

Table 2. Discrete Component List

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In final circuit, a snubber circuit, as described in [2], was implemented to protect the MOSFET

from large overshoot and ring effect, as well as reduce switching loss.

1.3.2 Output Diode

On the output side, the diode should be able to handle continuous DC output current drawn by the

load resistor. The maximum power of 50W will draw around 3.7A through the diode, so the current

rating should be around this value. However, in the power lab the diode with maximum current

rating available is 1N5822 with 3A average current rating. In early design, only single diode was

used to handle the current. In the final testing with highest current, two diodes were placed in

parallel to allow more current flow.

1.3.3 Input Interface Capacitor

As it is suggested in [2], input interface capacitor is needed to minimize the current spikes drawn

from the power supply to reduce extreme transient behavior. A large electrolytic capacitor with

1mF capacitance is added.

1.3.4 Output Capacitor

Similar to input capacitor, output capacitor reduces the output voltage ripple because of the low-

pass filtering characteristic. A large electrolytic capacitor with 1mF capacitance is added.

Figure 4. MOSFET Snubber Circuit

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1.4 Transformer Design

The transformer provides isolation between input and output. The voltage range of input and output

are close to each other such that a transformer with 1:1 ratio is sufficient for this converter.

As mentioned above, both DCM and CCM transformer were manufactured and tested in the design

process. Both of the transformers were winded with turn ratio close to 1:1.

In magnetics design, there are two main constrains that set the limit of frequency, voltage, and

current rating of the transformer. The two constrains as stated in [2] are volt-sec and amp-turn as

described by following inequalities:

𝑉𝑑𝑐∆𝑡 < 𝐵𝑠𝑎𝑡𝑁𝐴𝑐𝑜𝑟𝑒 (3)

𝑁𝑖 <𝐵𝑠𝑎𝑡𝑙

𝑢=

𝐵𝑠𝑎𝑡𝐴

𝐴𝑙 (4)

In Figure. 4, the transformer showed a nearly perfect 1:1 ratio at frequency around 20KHz as

channel 1 (input) and channel 2 (output) matched in both phase and amplitude. The transformer

has to operate at the correct frequency range to achieve best energy transfer. Thus 20KHz should

be the main switching frequency of the converter.

Figure 5. 1:1 Transformer Iinput/Output Waveform

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The inductance of DCM transformer should be less than the critical inductance calculated earlier.

The magnetic core P36/22-3F3-E40 was selected for winding. It has specific inductance 𝐴𝑙 value of

400nH. Based on equation:

𝐿 = 𝑁2𝐴𝑙 (5)

Only 5 turns on each side of the transformer were needed to reach a proper inductance of 11µH.

And according to (4), small value of turns will allow high saturation current. At the same time,

the winding wires can have larger gauge numbers to fit in the window area of the core, also

allowing more current flow. In the final design, 16 AWG wires were used for winding. The core

also has permeability µ of value 84 and effective area of 202 𝑚𝑚2. According to [3], the

datasheet of 3F3, the saturation limit of B field is greater than 315mT under the test condition in

the second column. For worst case calculation, the B field is set to 0.3 Tesla. By plugging

effective area, effective inductance, saturation B field, and number of turns into equation (4), the

maximum current turned out to be around 30A. Since the operating condition of this converter

should be less severe than conditions listed in column two of the datasheet table, the actual

current limit should be higher than 30A. This was later proved in the test results.

The CCM transformer was winded with toroid core. During the design process, the large

transformer in the power lab was tested first. With inductance of 1mH and hundreds of turns of

winding, the current saturated quickly as soon as it reached 2A. Again, (4) could explain the

present of such low saturation current. Toroid cores usually have large permeability µ in the order

of magnitude of 103, thus even smaller number of turns is needed to allow high saturation current.

However, small number of turns on toroid cores can also lead to very large flux leakage and cause

more energy loss.

Table 3. 3F3 Operating Parameters [3]

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Based on all the calculations and practical consideration, the DCM transformer was chosen to be

inserted into the final design.

1.5 Feedback Control Design

1.5.1 Control Algorithm

Feedback control is necessary to meet the design specifications that require stable output voltage

under different input voltages. Control is also important to protect power devices from large

transient spikes.

A control algorithm was implemented with similar algorithm purposed for buck converter in [1].

The only difference is that simple PID was used instead of Fuzzy PID control.

Instead of just measuring output voltage and feed it into PID controller, the input voltage was

also sensed such that it will first calculate the ideal duty cycle to reach desired output voltage and

Figure 6. CCM Transformer Current Saturation

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then sum together with PID control block.

CCM and DCM have different equations to calculate the ideal duty cycle. And by natural, CCM

is easier to implement load regulation because the duty cycle is not related to load, as it’s described

in equation (2), whereas the duty cycle in DCM is harder to control because the duty cycle is

related to load in the following way:

𝐷 = 13.8

𝑉𝑖𝑛∗√𝑅𝑇2𝐿

(6)

While in CCM, the ideal duty cycle can be calculated by just using input voltage:

𝐷 =𝑉𝑖𝑛

𝑉𝑖𝑛 + 13.8 (7)

A simple PID control will work in both cases, but for this algorithm to function properly, in DCM,

the information of load variation is also needed to calculate the ideal duty cycle. However, since

current sensing function was quite difficult to implement with the components in the lab, the load

resistor is manually input into the software.

1.5.2 NI myRIO and LabVIEW GUI

National Instrument myRIO is used as the data acquisition and control hardware for this application.

LabVIEW is the graphical programming tools that is also developed by National Instrument. The

advantage of myRIO is that it has very robust data acquisition ability that can handle instability

such as spikes during measuring. It has high resolution Analog-to-Digital Converter that can

allows for highly precise control. The advantage of LabVIEW is that first of all it has built-in PID

Figure 7. Control Block Diagram

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control block, secondly, the virtual instrument graphic interface allows fast prototyping of control

algorithm, debugging and data analysis.

The following pins on myRIO are connected for this application:

Table 4. Pinout for myRIO

myRIO Pins Purpose

Analog Input (0) Input Monitoring

Analog Input (1) Output Monitoring

Digital Output (3) PWM

Digital/Analog Ground Ground Reference

With built-in features of LabVIEW, a Graphical User Interface was developed to control and

monitor the operation and performance of the converter in real time.

Figure 8. LabVIEW GUI

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The following paragraphs will explain all the labelled function blocks shown above in the picture

(sorry for inconsistency in letter cases).

pid output: The waveform plot monitors the value from PID controller in real-time such that the

control effort can be monitored in real-time.

DCM enable: This button selects the algorithm for calculating ideal duty cycle under CCM and

DCM.

DCM load resistor: To calculate ideal duty cycle in DCM, the load resistor value should be input

into the software. If current sense is available on the output side, this manual input is not needed

anymore.

Frequency: PWM switching frequency.

Manuel test duty: This button enables manual debugging mode, in other words, open-loop

operation.

Test duty: To adjust duty ratio in open-loop condition.

PID gains: Proportional, integral and derivation gains.

Input/output Monitor: input and output voltage reading.

With all the hardware and software implementation, the step response and input voltage regulation

performed as expected. The results will be discussed in later chapters. And labVIEW code is

attached.

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1.6 Final Package and Demo Setup

Following the design process discussed above, the final schematic is designed as following:

The input and output voltages were divided by half to feed into Analog Input pins on myRIO. The

low-side driver amplified PWM signal from myRIO to 12V level to drive the MOSFET.

All the capacitors, MOSFET, snubber circuits and sensing resistors were tightly placed on a vector

board. The transformer was connected with banana plugs because the wire gauge was too large for

it to be soldered on the vector board.

The overall bench setup follows the block diagram below:

Figure 9. Fly-back Converter Schematic

Figure 10. Final Demo Setup

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This setup turned out to be very robust compared to the earlier breadboard version. It was able to

handle highest current output, and thanks to the compact layout of the vector board, the inductive

reaction was reduced to a reasonable level.

2. TEST RESULTS DISCUSSION

The converter met all the design specifications expect that the maximum power was slightly lower

than expectation. The main reason was that the output diode has current limit of 3A. This problem

was fixed during later data collection test by adding another diode in parallel. The transformer

functioned as expected and was able to transfer a very high peak current in DCM. The control

algorithm, after careful tuning, was able to react against input variation and load variation.

2.1 Efficiency

Due to the nature of DCM, the efficiency was not able to reach a very high value. The efficiency

was measured at steady state under the setups of fixed input voltage with various loads, and fixed

load with varying input voltages.

Figure 11. Demo Photos

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Load

(Ohm)

Input

Current(A)

Input

Voltage(V)

Output

Current(A)

Output

Voltage

(V)

Output

Power (W)

Efficiency

65 0.46 9.97 0.21 13.82 2.95 0.643

45 0.7 10 0.31 13.80 4.28 0.611

30 1.05 9.85 0.45 13.80 6.25 0.604

20 1.62 9.85 0.68 13.80 9.43 0.591

10 3.5 9.9 1.36 13.70 19 0.548

The efficiency deceases with increasing current output. This might be caused by higher core losses

under higher current. And the losses of operating in DCM are much greater in general than in CCM.

As shown in the output voltage column, the output stayed at around 13.8V under all the load values

thanks to the feedback control. The digital value of 13.8V on wattmeter was so accurate that it

reached the last digit of precision thanks to high resolution ADC in myRio.

For next test, the load was fixed to 65ohm for safety purpose, and the converter was tested at

different input voltages.

Table 5.Converter Efficiency Test (10V input, Varying Load)

0.54

0.56

0.58

0.6

0.62

0.64

0.66

0 10 20 30 40 50 60 70

Effi

cien

cy

Load Resistor (Ohm)

Efficiency V.S. Load (Fix Input)

Figure 12. Efficiency V.S. Load (Fix Input

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Input

Voltage(V)

Input

Current(A)

Output

Current(A)

Output

Voltage (V)

Output

Power (W)

Efficiency

9.97 0.46 0.21 13.80 2.95 0.643

11.99 0.39 0.21 13.80 2.95 0.630

14.00 0.32 0.21 13.80 2.95 0.658

16.00 0.3 0.21 13.80 2.95 0.615

18.00 0.26 0.21 13.80 2.95 0.630

As can be seen from the table, under the same load, the converter would constantly deliver steady

power with regard to varying input voltage. The efficiency didn’t vary much since the output

current remained at the same level.

Table 6.Converter Efficiency Test (10V-18V input, Fixed 65 Ohm Load)

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

0.6

0.65

0.7

8 10 12 14 16 18 20

Effi

cien

cy

Input Voltage (V)

Efficiency V.S. Input Voltage (Fixed Load)

Figure 13. Efficiency V.S. Input Voltage (Fixed Load)

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2.2 Input Step Response

The input step response was measured by setting the oscilloscope to video mode.

Step response was tested with 65ohm load

resistor and 12V input voltage. Compare to the simulated open-loop result, the control algorithm

can achieve a similar rising time. During the actual demo, the overshoot was found to be very large.

The reason was later found out that the load resistor value was not input correctly such that the

ideal duty cycle calculation gave a very large initial duty ratio. This correct waveform above was

obtained by setting the DCM load resistor value to 65 in the LabVIEW GUI.

The step response was also tested using CCM transformer, however, since CCM transformer was

not used in the final design, the step response was not recorded. In CCM, the control system was

also able to reduce oscillation and generate a very flat rising curve with very fast settling time

under light load situation.

2.3 Transformer Performance

The DCM transformer is designed to deliver maximum average current of 5A from the input.

Based on previous calculation, the maximum peak current should be above 20A to compensate for

imperfect efficiency.

Figure 14.1. Actual Step Response Figure 14.2. Simulated Step Response

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The transformer current was recorded at different duty ratio with 10V input and 10 Ohm load.

The waveforms showed very clean and typical DCM current without much noise, and they also

matched theoretical values very well. For example, at 48% duty ratio, the output average current

can be calculated as following:

< 𝐼𝑖𝑛 > = 𝐷 ∗𝑖𝑝𝑒𝑎𝑘

2= 3.7𝐴 (8)

And output average current is:

< 𝐼𝑜𝑢𝑡 >=13.8

10= 1.38𝐴 (9)

Relation between input and output current:

𝑉𝑖𝑛 ∗ 𝐼𝑖𝑛 ∗ 𝐸𝑓𝑓𝑖𝑐𝑖𝑒𝑛𝑐𝑦 = 𝑉𝑜𝑢𝑡 ∗ 𝐼𝑜𝑢𝑡 (10)

Figure 15.1. 20% Duty Cycle 10V input& 10 Ohm load Figure 15.1. 40% Duty Cycle 10V input& 10 Ohm load

Figure 15.3. 50% Duty Cycle 10V input& 10 Ohm load

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The actual ideal input current is calculated to be 1.9A from (10), which yielded an efficiency

around 1.9/3.7= 0.51. This result showed the same efficiency level as the wattmeter measurements

discussed in Chapter 2.1

2.4 Input Voltage Disturbance Rejection

The control system implemented should be able to control the output voltage within a reasonable

range with regard to input voltage variations. The performance of input voltage disturbance

rejection can be evaluated by swiping input voltage and monitoring output voltage ripple.

The input voltage was gently swiped from 12V to 15V within 20s during this test. As can be seen

from the waveform above, the output voltage showed a little rise when the input voltage increased

from 12V. The control system came into effect later as output began to drop back to the original

level of 13.8V.

In the test above, the input voltage increased with a very slow rate, and the output voltage in this

situation still showed a very obvious rise because the control can’t decrease the duty cycle quickly

Output

Voltage

Varying

Duty Ratio

Figure 16. Output Voltage With Input Regulation

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enough to counteract increased input voltage. If under certain circumstances that a very abrupt

change in input voltage presents, the control system might not be capable of reacting to such

variation, thus causing large output voltage ripple.

3. CONCLUSIONS AND FUTURE IMPROVEMENTS

The converter was able to meet all the required specifications and was able to perform all the tests

during the demonstration. However, the drawbacks of this project are also very obvious.

First of all, the converter is not packaged in a compact form. It requires an independent power

supply for gate driving, a power wall-plug for NI myRio and a laptop to load LabVIEW software

into myRIO if the software is not burned onto the FPGA. This setup is convenient for testing

different control algorithms, but it is still far from an independent converter. An independent

converter should only take input from the source and generate output as required.

To improve this project into a more compact converter, a voltage-source circuit should be designed

to drive the gate. A possible solution is to use linear regulators and regulate input voltage to

constant 10V. At the same time, switches with proper gate voltage below 10V should be chosen

for easy driving.

Second, since NI myRIO can operate on a battery source, a charging circuit that takes input from

the output of the converter can be designed to constantly charge the battery such that myRIO can

be powered in an indirect way from the input source.

Lastly, the output is not truly isolated from the input since they share the same ground. A possible

solution to this is to add a voltage-to-frequency converter and then converts frequency back to

voltage with an optocoupler isolated sensing circuit.

As discussed in earlier chapters, the control algorithm should also be analyzed more

mathematically to find the optimum solution.

To conclude, this project was successful overall. Theoretical calculation, practical circuit design

considerations, software implementation and control system design were all well applied and

contributed to the final demo success.

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4. REFERENCE

[1] Journal of Electrical Engineering & Technology Vol. 7, No. 5, pp. 724~729, 2012. Simple Fuzzy PID

Controllers for DC-DC Converter. K.-W. Seo and Han Ho Choi

[2] Krein, Philip T. Elements of Power Electronics. New York: Oxford UP, 1998. Print. [3] P. T. Krein.

[3] Philips Components, Product Specification, URL: http://www.datasheetarchive.com/dl/Datasheet-

054/DSA0011651.p

[4 ] Flyback converter, Wikipedia, URL: http://en.wikipedia.org/wiki/Flyback_converter

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APPENDIX

LabVIEW Code:


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