ADVANCE PROGRAM 2012 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE FEBRUARY 19, 20, 21, 22, 23 CONFERENCE THEME: SILICON SYSTEMS FOR SUSTAINABILITY SAN FRANCISCO MARRIOTT MARQUIS HOTEL IEEE SOLID-STATE CIRCUITS SOCIETY 5-DAY PROGRAM THURSDAY ALL-DAY 4 FORUMS on data communications, computational imaging, biolectronics, and many-core SoC optmization A SHORT-COURSE on low-power analog signal processing ® NEW THIS YEAR: DEMOS EXTENDED TO AN ACADEMIC DEMONSTRATION SESSION (ADS) SUNDAY ALL-DAY 2 FORUMS on RF beamforming, and green circuit design 9 TUTORIALS on RF mixers, Flash-memory, mobile GHz processors, wideband delta-sigma, jitter, integrated voltage regulators, digital calibration for RF, offset and flicker noise, and MEMS 2 EVENING EVENTS on graduate student research in progress, and smarter robotics
Transcript
ADVANCE PROGRAM
2012 IEEE
INTERNATIONALSOLID-STATE
CIRCUITSCONFERENCE
FEBRUARY19, 20, 21, 22, 23
CONFERENCE THEME:
SILICON SYSTEMS
FOR SUSTAINABILITY
SAN FRANCISCOMARRIOTT MARQUIS HOTEL
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ISSCC VISION STATEMENTThe International Solid-State Circuits Conference is the foremost global forum for presentationof advances in solid-state circuits and systems-on-a-chip. The Conference offers a uniqueopportunity for engineers working at the cutting edge of IC design and application to maintaintechnical currency, and to network with leading experts.
CONFERENCE TECHNICAL HIGHLIGHTSOn Sunday, February 19th, the day before the official opening of the Conference, ISSCC 2012offers:
• A choice of up to 4 of a total of 9 Tutorials• A choice of 1 of 2 Advanced-Circuit-Design Forums
The 90-minute tutorials offer background information and a review of the basics in specificcircuit-design topics. In the all-day Advanced-Circuit-Design Forums, leading experts presentstate-of-the-art design strategies in a workshop-like format. The Forums are targeted at designers experienced in the technical field.
On Sunday evening, there are two events: A Special-Topic Session entitled, “What’s Next inRobots?.....” will be offered starting at 8:00pm. In addition, the Student Research Preview,featuring short presentations followed by a poster session from selected graduate-studentresearchers from around the world will begin at 7:30 pm. A distinguished circuit designer,Professor Willy Sansen will provide introductory remarks at the Preview.
On Monday, February 20th, ISSCC 2012 offers four plenary papers on the theme: “SiliconSystems for Sustainability”. On Monday at 12:15 pm, there will be a Women’s NetworkingEvent, a luncheon. On Monday afternoon, there will be five parallel technical sessions, followed by a Social Hour open to all ISSCC attendees. The Social Hour held in conjunctionwith the Book Display will also include the Academic Demonstration Session (ADS), featuringposters and live demonstrations for selected papers from universities. Monday evening features a panel discussion on “Is RF Doomed to Digitization?…..”, as well as two Special-Topic Sessions on “Technologies that Could Change the World…..”, and “Optical PCB Interconnects…..”.
On Tuesday, February 21st, there are five parallel morning and afternoon technical sessions.A Social Hour open to all ISSCC attendees will follow. The Social Hour held in conjunctionwith the Book Display will include the Industrial Demonstration Session (IDS), featuringposters and live demonstrations for selected papers from industry. Tuesday evening sessionsinclude two evening panels on “Little-Known Features of Well-Known Creatures”, and “Whatis the Next RF Frontier?”, as well as one Special-Topic Session on “Vision for Future Television”.
On Wednesday, February 22nd, there will be five parallel sessions morning and afternoon.
On Thursday, February 23rd, ISSCC offers a choice of five events: • A Short Course on “Low-Power Analog Signal Processing”• Four Advanced-Circuit-Design Forums on high-speed data communications, computational imaging, bioelectronics, and many-core SoC optimization
Registration for educational events will be filled on a first-come, first-served basis. Use ofthe ISSCC Web-Registration Site (http://www.isscc.org) is strongly encouraged. Registrantswill be provided with immediate confirmation on registration for Tutorials, Advanced-Circuit-Design Forums, and the Short Course.
FORUMSF1 Beamforming Techniques and RF Transceiver Design..........................................7F2 Robust VLSI Circuit Design and Systems for Sustainable Society .......................8
EVENING SESSIONSES1 Student Research Preview ...................................................................................9ES2 What’s Next in Robots? ~ Sensing, Processing, Networking Toward Human Brain and Body .................10
PAPER SESSIONS1 Plenary Session............................................................................................11-142 High-Bandwidth DRAM & PRAM .......................................................................153 Processors.........................................................................................................164 RF Techniques....................................................................................................175 Audio and Power Converters .............................................................................186 Medical, Displays and Imagers ..........................................................................19
EVENING SESSIONSES3 Technologies that Could Change the World – You Decide!..................................21ES4 Optical PCB Interconnects, Niche or Mainstream?.............................................22EP1 “Is RF Doomed to Digitization? What Shall RF Circuit Designers Do?” ...............................................................22
PAPER SESSIONS7 Multi Gb/s Receiver and Parallel I/O Techniques ................................................238 Delta-Sigma Converters .....................................................................................249 Wireless Transceiver Techniques .......................................................................2510 High-Performance Digital...................................................................................2611 Sensors & MEMs...............................................................................................2712 Multimedia & Communications SoCs ................................................................2813 High-Performance Embedded SRAM.................................................................2914 Digital Clocking & PLLs .....................................................................................3015 mm-Wave & THz Techniques .............................................................................31
16 Switching Power Control Techniques.................................................................3417 Diagnostic & Therapeutic Technologies for Health.............................................35
Industry Demonstration Session ..................................................................................36
EVENING SESSIONSES5 Vision for Future Television................................................................................37EP2 Little-Known Features of Well-Known Creatures ................................................38EP3 What is the Next RF Frontier? ............................................................................38
PAPER SESSIONS18 Innovative Circuits in Emerging Technologies....................................................3919 20+Gb/s Wireline Transceivers & Injection-Locked Clocking .............................4020 RF Frequency Generation ...................................................................................4121 Analog Techniques.............................................................................................4222 Image Sensors...................................................................................................4323 Advances in Heterogeneous Integration.............................................................4424 10GBASE-T & Optical Frontends........................................................................4525 Non-Volatile Memory Solutions .........................................................................4626 Short-Range Wireless Transceivers ...................................................................4727 Data Converter Techniques ................................................................................4828 Adaptive & Low-Power Circuits .........................................................................49
SHORT COURSE Low-Power Analog Signal Processing ..........................................................50-51
FORUMSF3 10-40 Gb/s I/O Design for Data Communications ..............................................52F4 Computational Imaging......................................................................................53F5 Bioelectronics for Sustainable Healthcare ..........................................................54F6 Power/Performance Optimization of Many-Core Processor SoCs......................55
Conference Information ...........................................................................................61-63
T1: RF Mixers: Analysis and Design Trade-offsMixers are essential building blocks of every RF transceiver, often compromising the noiseand linearity performance of the entire receive or transmit chain. Specifically, the switchingaction involved in mixing typically dictates the choice of the radio architecture and proper fre-quency planning to avoid the receiver desensitization. In this tutorial various mixer architectu-res such as passive and active, current-mode and voltage-mode, and their properties areanalyzed and discussed. Of special importance is the noise response of mixers, which is notvery well understood due to the nonlinear and time varying nature of the block, and the factthat conventional linear noise analysis applicable to amplifiers often does not hold. We willfocus on intuitive and qualitative ways of analyzing the noise of both passive and active mixersas well.
Instructor: Hooman Darabi Hooman Darabi received the BS and MS degrees both in Electrical Engineering from SharifUniversity of Technology, Tehran, Iran, in 1994, and 1996, respectively. He received the Ph.D.degree in electrical engineering from the University of California, Los Angeles, in 1999. He iscurrently a Sr. Technical Director and a Fellow with Broadcom Corporation, Irvine, CA, as apart of the mobile and wireless group. His interests include analog and RF IC design for wi-reless communications. Dr. Darabi holds over 170 issued or pending patents with Broadcom,and has published over 50 peer-reviewed journal and conference papers.
T2: Flash-Memory Based Circuit, System, and Platform DesignApplications using flash memory are rapidly increasing in number. Different applications offlash memory demand various Circuit, System, Software and Platform Co-Design to optimizeusage. Even for a given application these tradeoffs should be considered. Unlike tutorials onflash memory in the past that mostly focus on circuit design, this tutorial will consider Sys-tem, Software, and Platform Design from the application perspective. The tutorial will alsobe of interest to the broader audience with interests beyond memory field.
Instructor: Mark BauerMark Bauer is a Fellow at Micron working in the NAND Solutions Group where he is respon-sible for the vertical integration of Non Volatile Memory and memory systems. He joined Mi-cron in 2010 as part of the Numonyx aqusition. Prior to Micron he spent three years atNumonyx on advanced Phase Change Memory designs in technology. From 1985 to 2008he worked at Intel developing EPROM, NOR Flash, NAND Flash and Phase Change Memorydesigns. He holds more than 30 US Patents, has published numerous technical papers in thefield of Non Volitile Memory, has been an invited speaker at technical conferences, served onthe ISSCC Memory Technical Program Committee for 11 years and is currently on the VLSISymposium Technical Program Committee. He recieved the BSEE from the University of Ca-lifornia in 1985.
T3: Mobile GHz Processor Design Techniques Mobile computing devices such as smart-phones and smart-pads open up new challengesin mobile processor designs in terms of their speed and power targets. Mobile processorsare getting more powerful in order to run increasingly complex software. Therefore, the designof high-speed low-power mobile processors is becoming the major challenge. In this tutorial,design techniques for high-speed mobile CPU and GPU are discussed at several design levels.The talk will go through the architecture, circuit, device level optimization and also considerchip-wise power management techniques. Special considerations for cost-effective micro-architectures, high-speed logic, low-power arithmetic, and DVFS will be highlighted.
Instructor: Byeong-Gyu NamByeong-Gyu Nam received his Ph.D. degree in electrical engineering from Korea AdvancedInstitute of Science and Technology (KAIST), Daejeon, Korea, in 2007. His Ph.D. work focusedon low-power GPU design for mobile devices. From 2007 to 2010, he was with SamsungElectronics, Giheung, Korea, where he worked on the world’s first low-power 1-GHz ARM mi-croprocessor design. Dr. Nam is currently with Chungnam National University, Daejeon, Korea,as an assistant professor. His current interests include mobile GPU, embedded CPU, low-power SoC, and their associated SW platforms. He is serving as a program committee mem-ber of the IEEE ISSCC, A-SSCC, COOL Chips, and VLSI-DAT.
TUTORIALS Sunday February 19th
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T4: Wideband Delta-Sigma ModulatorsThe application space of delta-sigma analog-to-digital converters has been greatly extendedduring the last few decades with applications ranging from traditional applications such asaudio and hearing aids that require only a few (tens of) kHz bandwidth to a multitude of cellularstandards that need up to 40MHz bandwidth. To enable this bandwidth range of four ordersof magnitude, new innovative wideband delta-sigma architectures and circuits have been de-veloped that operate at GHz rate sampling frequencies. This tutorial gives an introduction tothe system design and implementation of wideband delta-sigma modulators. A review ofwideband delta-sigma architectures, loop stability, filter implementations and circuit designsis presented. Some case studies illustrate wideband delta-sigma modulators that have band-widths in the range from several tens of MHz to beyond 100MHz.
Instructor: Lucien Breems Lucien Breems received the M.Sc. degree and the Ph.D. degree in Electrical Engineering fromthe Delft University of Technology, The Netherlands, in 1996 and 2001, respectively. From2000 to 2007 he was with Philips Research, Eindhoven the Netherlands and in 2007 he joinedNXP Semiconductors where he currently leads a team working on delta-sigma A/D converters.Since 2008, he has been a lecturer at the Delft University of Technology on the topic of delta-sigma modulation and since 2011 he is a part-time Professor at the Eindhoven University ofTechnology. His research interests are in the field of mixed-signal circuit design. In 2001, hereceived the ISSCC “Van Vessem Outstanding Paper Award”.
T5: Jitter: Basic and Advanced Concepts, Statistics, and ApplicationsJitter and phase noise are key factors that deeply impact the performance of circuits in moderncommunication applications. Within the industry, many types of jitter must be and are con-sidered, including cycle-to-cycle, accumulated, deterministic, random, total, absolute, inte-grated, TIE, and more. Understanding the implications of each of these jitter types demandsclear jitter term definitions as well as a common understanding of their practical meaning. Inresponse to this need, this tutorial will presents basic and advanced concepts of jitter. Thefirst part of the tutorial will focus on jitter definitions, statistics, and the relationship of jitterto phase noise. The second part of the tutorial will explore the impact of jitter on a variety ofapplications, drawing on examples from wireline as well as other technical areas. The overallgoal of the tutorial is to provide a solid understanding of what jitter is, how to correctly specifyit, and to enhance understanding of jitter specifications for different applications.
Instructor: Nicola Da Dalt Nicola Da Dalt received the Master degree from University of Padova, Italy, in 1994 and thePhD degree from RWTH Aachen, Germany, in 2007, both in Electronic Engineering. From1996 to 1998 he was with Telecom Italia, Italy, as concept engineer for architectures and syn-chronization of data transmission networks and satellite communications. Since 1998 he hasbeen with Infineon Technologies, Austria, as an IC design and concept engineer for clock sys-tems in applications ranging from wireline, to memory and wireless. Since March 2005 heleads the Clocking and Interface Systems group. He received the 2010 IEEE Guillemin-CauerBest Paper Award. He holds four granted patents and is the author of several publications inconferences and journals.
T6: Power Management Using Integrated Voltage RegulatorsAggressive technology scaling has enabled very high levels of transistor integration. Managingtotal power consumption has emerged as the most challenging task in today’s highly complexmicroprocessor systems. In this tutorial, we will review power management techniques im-plemented in recent designs. Independent per-core dynamic voltage scaling is proven to bean effective way to minimize power consumption. Due to the size and routing planes, thenumber of independent platform rails is limited to a very small number. Near-load voltageregulators provide a practical solution. This tutorial includes a survey of recent innovationsin near-load voltage regulators.
Instructor: Tanay KarnikTanay Karnik is Principal Engineer and Program Director in Intel Lab’s Academic ResearchOffice. He received his Ph.D. in Computer Engineering from University of Illinois at Urbana-Champaign in 1995. His research interests are in the areas of variation tolerance, power de-livery, soft errors and physical design. He has published 50 technical papers, has 44 issuedand 33 pending patents. He received an Intel Achievement Award for the pioneering work onintegrated power delivery. Tanay was the General Chair of ASQED’10, ISQED’09, ISQED’08and ICICDT’08. Tanay is IEEE Senior Member, Associate Editor for TVLSI and Guest Editorfor JSSC.
TUTORIALS Sunday February 19th
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T7: Digital Calibration for RF TransceiversDesigning high-precision RF transceivers in deep submicron technologies is increasinglychallenging due to reduced supply headroom, non-linearities of transistors, and large processparameter spread. By taking advantage of the cheaper and faster digital computing power,digital calibration is becoming an increasingly common practice to overcome such challengesand enhance transceiver performance. Calibration techniques covered include I/Q mismatchcalibration, DC offset and LO leakage removal, closed-loop power control and envelope tra-cking, analog filter response calibration, digital pre-distortion for PAs, and antenna tuning.The tutorial will also cover DSP methods and algorithms and provide specific examples ofdigitally calibrated transceivers.
Instructor: Albert JerngAlbert Jerng received his BSEE, MSEE from Stanford University, and his PhD EE from MIT in1994, 1996, and 2006, respectively. While at MIT, he conducted research on CMOS VCO de-sign and digital TX architectures for Gb/s OFDM systems. Since 2007, he has been withRalink Technologies as Sr. Director for Advanced Circuits and Systems working on Bluetoothand WiFi products, and is now employed as Deputy Director at Mediatek, responsible for theWiFi RF transceiver division, after their merger with Ralink. He is also serving as GeneralChair for the IEEE RFIC Symposium in 2012.
T8: Managing Offset and Flicker NoiseA large number of circuits require DC accuracy and low noise at low frequencies. Sensor in-terfaces are a good example, but comparators, ADC’s, and many other blocks need it too.This tutorial will provide a review of techniques to achieve low offset and flicker noise.Techniques such as chopper stabilization, correlated double sampling, auto-zero, digitalstartup calibration, and digital background calibration will be reviewed. Implementation exam-ples will be shown and noise and aliasing and other artifacts will be analyzed. Techniques tomaster these artifacts will be discussed. The ideas will then be taken into the mixed signaldomain.
Instructor: Axel ThomsenAxel Thomsen received his PhD from the Georgia Institute of Technology in 1992. He hasheld positions at the University of Alabama in Huntsville, University of Texas, and Cirrus Logic.Currently he is a Distinguished Engineer at Silicon Laboratories in Austin, TX. He has workedon chips for industrial measurement, timing, isolation and power applications. He has a stronginterest in precision measurement. Currently he is working in the Embedded Mixed SignalDivision on data converters and amplifiers. He holds more than 40 patents.
T9: Getting In Touch with MEMS: The Electromechanical InterfaceMEMS systems include mechanical structures and electronic sense and drive circuits. Be-tween these is an electromechanical interface, which can be capacitive, piezoresistive, piezo-electric, ferroelectric, electromagnetic, thermal, optical or can take some other form. Theselection of this interface is the single most critical decision in the system definition, and itdetermines the eventual capabilities and limits of the device. The interface fundamentally setsthe device’s sensitivity, accuracy, drift, ageing, temperature behavior, and environmental ca-pabilities. The interface determines the MEMS production technology and hence the fab se-lection, the cost structure, and the time to market. This tutorial examines and compares theavailable options and application drivers. Which interface technologies can be used? Why isone more suitable for a particular application than another? How do they scale? What is onthe horizon? The goal is to expand the attendee’s potential role from circuit designer to systemdesigner. From “Here is the MEMS device, design the interface circuit.” into “Here is the prob-lem, define an optimal solution.”
Instructor: Aaron PartridgeAaron Partridge received the B.S., M.S., and Ph.D. degrees in Electrical Engineering fromStanford University, Stanford, CA, in 1996, 1999, and 2003, respectively. In 2004 he co-founded SiTime Corp. where he is Chief Science Officer. SiTime is the leading supplier ofMEMS oscillators, resonators, and timing devices. From 2001 through 2004 he was ProjectManager at Robert Bosch Research and Technology Center, Palo Alto, CA, where he coordi-nated the MEMS resonator research. He serves on the IEEE International Solid-State CircuitsConference IMMD subcommittee and is the Editorial Chair of the IEEE International FrequencyControl Symposium.
TUTORIALS Sunday February 19th
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F1: Beamforming Techniques and RF Transceiver Design
Organizers: Eric Klumperink, University of Twente, Enschede, The NetherlandsDomine Leenaerts, NXP Semiconductors, Eindhoven, The Netherlands
Committee: Albert Jerng, Ralink, Jhubei, TaiwanYorgos Palaskas, Intel, Hillsboro, ORDidier Belot, ST Microelectronics, Crolles, France
Phased arrays exploit electronic beamforming to create an electronically steerable beam pattern. This reinforces antenna gain in certain directions and reduces gain in others, i.e. spatial filtering. Until recently, phased-array systems exploited dedicated RF technologiesleading to relatively costly systems, e.g. for nautical systems, airplane radar systems, andsatellite communication. More recently, low-cost highly integrated beamforming conceptsreceived considerable interest in academia but also industry, enabling consumer applicationse.g. in base stations for macro- and femto-cells, car radar and 60GHz wideband radio links.(Bi-)CMOS beamforming techniques are at the heart of such systems. This forum reviewsbeamforming techniques suitable for IC integration, and discusses related (Bi-)CMOS transceiver designs. Several techniques will be discussed, e.g. RF phase shifting, LO phaseshifting, I/Q vector modulation and digital processing. Also the relation between key radarand communication system requirements and transceiver IC requirements will be considered.Finally, trends and challenges will be discussed in a panel.
Forum AgendaTime Topic
08:00 Breakfast
08:30 Introductory Overview of BeamformingGabriel Rebeiz, UC San Diego, LaJolla, CA
09:00 S-Band Phased-Array Radar with 2-D Digital BeamformingWim de Heij, THALES Nederland BV, Hengelo, The Netherlands
09:30 SiGe BiCMOS Single-Chip Receiver for S-Band Phased-Array RadarsFrank van Vliet, TNO, The Hague, The Netherlands
10:00 Break
10:30 Silicon RF Phased-Arrays at X-, Q-, W-Band and BeyondKwang-Jin Koh, Virginia Tech, Blacksburg, VA
1:00 Silicon-Based Integrated Beamforming and On-Chip RadiatorsAli Hajimiri, California Institute of Technology, Pasadena, CA
1:45 Vector Modulation Techniques and Interference NullingJeyanandh Paramesh, Carnegie Mellon University, Pittsburgh, PA
2:15 Break
2:45 RF Beamforming and 60GHz BiCMOS ChipsetsScott Reynolds, IBM T.J. Watson Research Center,
Yorktown Heights, NY
3:30 Panel Discussion: Challenges for the future?
4:00 Closing Remarks (Chair)
FORUM Sunday February 19th, 8:00 AM
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F2: Robust VLSI Circuit Design and Systems for Sustainable Society
Organizer/Chair: Ken Takeuchi, University of Tokyo, Tokyo, JapanCo-Chair: Jan Crols, AnSem, Heverlee, Belgium
Committee: Ken Takeuchi, University of Tokyo, Tokyo, JapanJan Crols, AnSem, Heverlee, BelgiumKevin Zhang, Intel, Hillsboro, ORMike Clinton, Texas Instruments, Dallas, TXTadaaki Yamauchi, Renesas Electronics, Itami, Japan
Technology scaling brings new challenges to the design of reliable and robust VLSI circuitsand systems – challenges that arise at the system, circuit and device levels.
This Forum provides an overview of such challenges, as well as overviews recent advancesin the domain of reliable and robust VLSI systems. Topics covered include the fault-tolerancerequirements for microcontrollers in automotive applications, recent trends in CMOS varia-bility, design techniques for robust non-volatile and volatile memories, as well as directionsfor improving the robustness of analog, communications, and voltage regulator circuits andsystems.
Forum AgendaTime Topic
8:00 Breakfast
8:20 IntroductionKen Takeuchi, University of Tokyo, Tokyo, Japan
8:30 Future Development of Robustness and Fault Tolerance Requirements for Microcontrollers in Safety Relevant Automotive Applications
Bernd Müller, Robert Bosch GmbH, Stuttgart, Germany
9:20 Understanding CMOS Variability and Soft errors for Robust Circuit DesignHidetoshi Onodera, Kyoto University, Kyoto, Japan
10:10 Break
10:25 Robust SRAM Design in Nano-Scale CMOS: Circuit and TechnologyYih Wang, Intel, Portland, OR
11:15 Embedded Non-Volatile Memory Design for Highly Reliable ApplicationsTakashi Kono, Renesas Electronics, Itami, Japan
12:05 Lunch
1:00 Dependable SSD DesignHiroshi Sukegawa, Toshiba, Yokohama, Japan
1:50 Robust System Design: Overcoming Complexity and Reliability ChallengesSubhasish Mitra, Stanford University, Stanford, CA
2:40 Break
2:55 Reliability Considerations in Deep Submicron Analog Circuit DesignTerry Mayhugh, Texas Instruments, Richardson, TX
3:45 Channel Coding in WirelessMartin Bossert, Ulm University, Ulm, Germany
4:35 Voltage Regulator Circuits and System Energy ManagementDave Freeman, Texas Instruments, Dallas, TX
5:25 Conclusion
FORUM Sunday February 19th, 8:00 AM
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ES1: STUDENT RESEARCH PREVIEW (SRP)
The Student Research Preview (SRP) will highlight selected student research projectsin progress. The SRP consists of 23 one-minute presentations followed by a PosterSession, by graduate students (Masters and PhDs) from around the world, which havebeen selected on the basis of a short submission concerning their on-going research.Selection is based on the technical quality and innovation of the work. This year, theSRP will be presented in three sessions: Analog, Mixed-Signal and RF Circuits; High-Performance Systems and Imagers; Techniques for Ultra-Low-Power Sensors.
The Student Research Preview will begin with a brief talk by the distinguished circuitdesigner, Professor Willy Sansen, K.U. Leuven. His talk on careers in solid-state circuitsis scheduled for Sunday,February 19th, starting at 7:30pm, and is open to all ISSCC registrants.
EVENING SESSIONS Sunday February 19th, 7:30 PM
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Bryan Ackland Stevens Institute of Technology, USABharadwaj Amrutur IISC, IndiaBevan Baas University of California, Davis, USAAndrea Baschirotto University of Milan-Bicocca, ItalyBill Bowhill Intel, USAEugenio Cantatore Tech University Eindhoven, The NetherlandsSeongHwan Cho KAIST, KoreaDenis Daly Cambridge Analog TechnologiesVasantha Erraguntla Intel, IndiaVincent Gaudet University of Waterloo, CanadaMakoto Ikeda University. of Tokyo, JapanAdreas Kaiser ISEN, FranceTakayuki Kawahara Hitachi, JapanShen-Iuan Liu National Taiwan University, TaiwanKofi Makinwa Tech. University Delft, The NetherlandsAkira Matsuzawa Tokyo Inst. Tech., JapanDejan Markovic' UCLA, USAShahriar Mirabbasi University of British Columbia, CanadaBoris Murmann Stanford University, USABing Sheu TSMC, TaiwanSameer Sonkusale Tufts University, USAJan Van der Spiegel University of Pennsylvania, USAMarian Verhelst Kath. University of Leuven, BelgiumZhihua Wang Tsinghua University, P.R. China
Chair: Jan Van der Spiegel University of PennsylvaniaCo-Chair: Makoto Ikeda University of Tokyo, JapanCo-Chair: Eugenio Cantatore Technical University Eindhoven,
The NetherlandsSecretary: SeongHwan Cho KAIST, KoreaAdvisor: Kenneth C. Smith University of Toronto, Canada Media/Publications: Laura Fujino University of Toronto, Canada A/V: John Trnka Rochester, MN
COMMITTEE MEMBERS
ES2: What’s Next in Robots? ~ Sensing, Processing, Networking Toward Human Brain and Body
Organizer: Kazutami Arimoto, Renesas Electronics, Itami, Hyogo, Japan
Organizer: Sam Kavusi, Bosch Research, Palo Alto, CA
Chair: Kenneth Salisbury, Stanford University, Stanford, CA
Most of us dreamt about robots in our childhood interacting and assisting us in our daily life.They are way beyond fiction and have emerged to become unavoidable in minimally-invasivesurgery and industrial automation. There is also an explosion in research areas around autonomous cars, humanoid/android, and personal assistance robots. Such advances arelargely due to the advances in semiconductor technologies driven by consumer and automotive electronics. Increasingly robotic platforms are also benefiting from the wirelesslyconnected infrastructure and the cloud. This session provides an overview of the major areasand their challenges that may be addressed by semiconductor technologies.
Time Topic
8:00 Robot Society with Teleoperated Robots and AndroidsHiroshi Ishiguro, Osaka University and ATR,
Osaka and Kyoto, Japan
8:25 Robotics for Minimally-Invasive Surgery and Therapy Simon DiMaio, Intuitive Surgical, Sunnyvale, CA
8:50 Advancing Personal RoboticsGünter Niemeyer, Willow Garage, Menlo Park, CA
9:15 Humanoid Robotics for ServicesBruno Maisonnier, ALDEBARAN Robotics, Paris, France
EVENING SESSIONS Sunday February 19th, 8:00 PM
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PLENARY SESSION — INVITED PAPERS
Chair: Anantha Chandrakasan, Massachusetts Institute of Technology, Cambridge, MAISSCC Conference Chair
Associate Chair: Hideto Hidaka, Renesas Electronics, Itami, Japan
ISSCC Program Committee Chair
FORMAL OPENING OF THE CONFERENCE 8:30AM
1.1 Flash Memory — The Great Disruptor! 8:45AMEli Harari, Co-Founder, Former CEO, and Chairman (retired),
SanDisk , Milpitas, CA
Since its commercial introduction in 1988 Flash-memory chip density has advanced through19 technology nodes, doubling the number of bits per chip with each successive node, withsub 20nm 128Gb Flash chips entering volume production in 2012. This incredible pace hasbeen made possible by the use of the industry-workhorse floating-gate Fowler-Nordheim tunneling cell, first employed in EEPROM, then in NOR and NAND Flash EEPROM. The convergence of NAND Flash with System-Flash and Multi Level Cells (MLC) in the past decadetransformed Flash from primarily a code-store memory to a highly-reliable low-cost data-store medium, bringing enormous price reductions and capacity growth to consumers.Flash became an enabling technology to, as well as a prime beneficiary from, the digital consumer electronics revolution, the rise of the Internet, and the proliferation of wireless mobile devices (most recently, smartphones and tablets), fueling the rapid growth of Flashstorage into a $25 billion industry today.
Over the past decade, Flash storage profoundly disrupted analog film, floppy disks, magnetictapes, micro-drives, and optical CDs. Price elasticity drove rapid growth in consumer demandfor Flash units and megabytes. Fierce competition among Flash suppliers ensured an amplesupply, and created Flash-card format standards developed by Industry Associations, therebyopen to all. Billions of units of SD, micro-SD, USB Flash-drive, and embedded Flash are soldby the industry each year, working seamlessly in literally tens of thousands of different hostdevices that are used in a broad spectrum of industries and applications.
I have been fortunate to have been involved with the semiconductor Non-Volatile-Memoryindustry over its 40-year history, first as a device physicist, then as an entrepreneur and businessman. In this presentation, I will provide my personal recollections of some of thepast milestones of this industry, and commentary on the profound impact that Flash has hadon Consumer Electronics and Mobile Computing. Looking forward, I will briefly discuss thesubstantial opportunities, as well as the considerable challenges for NAND Flash and post-NAND 3D Flash in the sub-20nm era ahead. I foresee that technology and manufacturingchallenges will be overcome through device and architectural innovations, and that in thecoming decade NAND and post-NAND 3D Flash will grow to eclipse all other storage media,whether semiconductor, magnetic, or optical, thereby completing a breathtaking odysseyspanning 50 years!
SESSION 1 Monday February 20th, 8:30 AM
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1.2 The Role of Semiconductors in the Energy Landscape 9:20AM Carmelo Papa, Senior Executive VP/GM, STMicroelectronics,
Geneva, Switzerland
The exponential increase of world energy demand, with a forecasted rise in electricity consumption of 45% between 2010 and 2030, makes energy management one of the mosturgent topics of this century, and a key driver of the evolution semiconductors and electronicscomponents.
Furthermore, the Kyoto Protocol on Climate Change targets a limitation of global temperatureincrease to 2°C maximum, within 2030, through two primary interventions: by increasingelectricity production from renewable and bio-fuel sources, and by increasing energy efficiency, using a wider adoption of microelectronics. Energy efficiency can contribute upto 54% of the required CO2 reduction.
From the application point of view, electricity consumption comes from 3 major areas of use:Power Supply (24%), Lighting (21%), and Motor Control (55%). Semiconductors will playan essential role in this scenario, thanks to a continuous improvement in silicon technologies,innovative IC topologies, and system design methodologies.
For example, for the past 10 years, appliances have seen a progressive replacement of universal motors with brushless motors using powerful and cost-efficient microcontrollerswith embedded advanced software algorithms, such as the ultimate Field-Oriented Controls.
Thanks to this development, the market welcomes new Class-A+ Home Appliances with average energy efficiency increase by 30% or more, that provide a saving of up to 50TWh by2020, today’s equivalent electricity consumption of Portugal and Latvia.
Cost-effective IC solutions make today’s CFL (Compact Fluorescent Lamp) and LED lightingtechnology adoption more affordable, with corresponding power-consumption reduction.For instance, the replacement of incandescent lamps with CFL in Europe will allow a savingof 11.5TWh by 2025, that is, one third of Denmark’s current electricity consumption.
“More Moore” and “More than Moore” technologies will play an important role in the energyrevolution involving aspects of the Smart Grid, particularly in Power-Conversion and Connectivity Systems. The first, with the adoption of finer lithography geometries, will allowminiaturization and integration at the component level, while the latter withheterogeneous system integration will allow the introduction of more functions like micro-batteries, smart sensors, plastic electronics, energy harvesting, and so on.
What we see is a kind of revolution, with an enormous impact on sustainability, quality oflife, and societal change!
ISSCC, SSCS, IEEE AWARD PRESENTATIONS 9:55AM
BREAK 10:20AM
SESSION 1 Monday February 20th, 9:20 AM
12
1.3 Take the Expressway to Go Greener 10:35AMYoichi Yano, Executive VP, Renesas Electronics, Tokyo, Japan
Society is going green! Increasingly, people commit to choosing equipment with lower energydemands. Historically, the growth of green has been repeatedly motivated by various economic shocks, such as the 1973 oil crisis. More recently, the Lehman Brothers crisis in2008 inspired green initiatives in various industry sectors: surges in solar-power generation,eco-friendly white-goods products, consumer electronics, and green hybrid cars. Most recently, the 3.11 earthquake and tsunami in Japan triggered another wave in energy-savinglife style motivated by the shortage of electric power. Now, the world is demanding greenerproducts for a greener society on a scale never seen before. How can we reduce power consumption?
Over time, microelectronics has evolved to save power. Semiconductor technology has beenin the lead in the reduction of power consumption, by enabling monitoring, controlling, andmanaging of energy consumption. The key product in this advance has been a less-commonly-known semiconductor device called the microcontrollers.
Microcomputers were introduced to the market in the early 1970s, firstly for electronic calculators, then in electro-mechanical controllers such as in cash registers, white goods,and consumer electronics. Then, microcomputers evolved along two different paths – one,called Microprocessors (MPU), for Personal Computers and Servers, and another called Microcontrollers (MCUs) for embedded controls. Beginning in 1987, market research firmsbegan to track world-wide shipment data for these two categories. Thus, we know that in2010, 500 million MPUs and 13 billion MCUs were shipped — the latter being 20x expansionsince 1987. Currently, about 400 MCUs are shipped EVERY SECOND!
Now, that MCUs are “everywhere you imagine”, we see more than one hundred such devicesin every modern home – in white goods, consumer electronics, remote controllers, metering,and so on. We find approximately one hundred MCUs in a modern car – in engine control,transmission control, body electronics, HVAC, window control, mirror control, Hybrid and allElectric Vehicle, and so on. Wide acceptance of MCUs in various embedded applications results from their ease of use, the availability of a wide range of products, and their self containment – everything needed is integrated on a tiny piece of silicon. In short, MCUs arelow-power, small in foot print, adequate in performance, and low-cost.
Technology-wise, the strength of an MCU comes from its programmability via on-board Flash-memory technology. While the introduction of Flash-based MCUs goes back to the early1990s, its widespread use in low-end microcontrollers was delayed to the early 2000s. Flash-based MCUs changed the world because of their programmability within a very smallfoot print and at low power. Thus, the huge current market! Most recently an MCU has beendeveloped that can operate from one lemon as a battery source. Such MCUs can save tremendous amounts of power through their vast use in a myriad of applications. They aretruly the core technology for everything going greener! Yet, MCUs will evolve further to savepower, in wide spread applications including the “energy harvesting” environment. On theother hand, the automotive industry requires higher real-time performance with a much higherlevel of functional safety in addition to lower power. Such requirements will drive the development of next generation Flash MCUs on the expressway to going green!
SESSION 1 Monday February 20th, 10:35 AM
13
1.4 Sustainability in Silicon and Systems Development 11:10AMDavid Perlmutter, Executive VP, Intel, Santa Clara, CA
It has been predicted that Moore’s Law will continue to double transistor-integration capacityevery two years, providing the abundance of transistors needed to realize novel architecturesfor future platforms. These platforms will enable more more-intelligent electronic gadgetsand devices to enrich our lives. Harnessing Moore’s Law and sustaining this growth overthe last four decades has not been easy. The task has been challenging; overcoming design-productivity limitations in the 80s; power dissipation in the 90s; and leakage powerin the last decade. However, we have persevered! But now, the major challenge we will facein the coming decade is not just power, but energy efficiency. Imagine a 100 giga-operations-per-second mobile device, a product that we would expect by the end of thedecade, consuming hundreds of watts of power! Likewise, with present techniques, a high-end exascale supercomputer would be expected to consume in excess of 1 gigawatts ofpower; not a practical solution. While Moore’s Law continues to provide more transistors,power budgets limit our ability to use them.
However, there are several technologies on the horizon which provide relief, and that we mustexploit. Advances in transistor structures such as 3D tri-gate transistors in 22nm, 3D diestacking, and future heterogeneous technologies, will provide higher performance at lowerenergy and leakage. Circuit technologies such as near-threshold-voltage logic can boost energy efficiency by an order of magnitude. Novel architectures can implement fine-grainpower and energy management. System software can be smarter and self-aware to managethe entire platform with an order-of-magnitude improvement in energy efficiency. Clearly, inthe expansion of the compute continuum, the energy-efficiency challenge is best served withthe co-design spirit; from top to bottom and from applications to process technology, all inharmony.
Energy efficiency of the compute sector will become increasingly important, with exponentialgrowth, and we must make smart choices about resource consumption that can help savethe environment. Intel recognizes the importance of caring for the planet by developing technological solutions to reducing the environmental impact of computing. This talk willaddresses energy efficiency, and outlines challenges, solutions, and opportunities in the nextdecade for the compute continuum.
PRESENTATION TO PLENARY SPEAKERS 11:45AM
CONCLUSION 11:55AM
SESSION 1 Monday February 20th, 11:10 AM
14
HIGH-BANDWIDTH DRAM & PRAM
Session Chair: Joo Sun Choi, Samsung Electronics, Hwasung, KoreaAssociate Chair: Daisaburo Takashima, Toshiba, Yokohama, Japan
2.1 A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with 1:30 PMDual-Error Detection and PVT-Tolerant Data-Fetch Scheme
K. Sohn, T. Na, I. Song, Y. Shim, W. Bae, S. Kang, D. Lee, H. Jung, H. Jeoung, K-W. Lee, J. Park, J. Lee, B. Lee, I. Jun, J. Park, J. Park, H. Choi, S. Kim, H. Chung, Y. Choi, D-H. Jung, J. Choi, B. Moon, J-H. Choi, B. Kim, S-J. Jang, J. Choi, K. OhSamsung Electronics, Hwasung, Korea
2.2 A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with Bank Group 2:00 PMand ×4 Half-Page Architecture
K. Koo, S. Ok, Y. Kang, S. Kim, C. Song, H. Lee, H. Kim, Y. Kim, J. Lee, S. Oak, Y. Lee, J. Lee,J. Lee, H. Lee, J. Jang, J. Jung, B. Choi, Y. Kim, Y. Hur, Y. Kim, B. Chung, Y. KimHynix Semiconductor, Icheon, Korea
2.3 A 1.2V 23nm 6F2 4Gb DDR3 SDRAM with Local-Bitline Sense 2:30 PMAmplifier, Hybrid LIO Sense Amplifier and Dummy-Less Array Architecture
K-N. Lim, W-J. Jang, H-S. Won, K-Y. Lee, H. Kim, D-W. Kim, M-H. Cho, S-L. Kim, J-H. Kang,K-W. Park, B-T. JeongHynix Semiconductor, Icheon, Korea
Break 3:00 PM
2.4 A 1.2V 30nm 1.6Gb/s/pin 4Gb LPDDR3 SDRAM with Input 3:15 PMSkew Calibration and Enhanced Control Scheme
Y-C. Bae, J-Y. Park, S. Rhee, S. Ko, Y. Jeong, K-S. Noh, Y. Son, J. Youn, Y. Chu, H. Cho, M. Kim, D. Yim, H-C. Kim, S-H. Jung, H-I. Choi, S. Yim, J-B. Lee, J. Choi, K. OhSamsung Electronics, Hwasung, Korea
2.5 A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth 3:45 PMY. Choi, I. Song, M-H. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo,J. Shin, Y. Rho, C. Lee, M. Kang, J. Lee, Y. Kwon, S. Kim, J. Kim, Y-J. Lee, Q. Wang, S. Cha,S. Ahn, H. Horii, J. Lee, K. Kim, H. Joo, K. Lee, Y-T. Lee, J. Yoo, G. JeongSamsung Electronics, Hwasung, Korea
2.6 A 283.2µW 800Mb/s/pin DLL-Based Data Self-Aligner for 4:15 PMThrough-Silicon Via (TSV) Interface
H-W. Lee1,2, S-B. Lim1, J. Song1, J-B. Koo1, D-H. Kwon2, J-H. Kang2, Y. Kim2, Y-J. Choi2, K. Park2, B-T. Chung2, C. Kim1
1Korea University, Seoul, Korea 2Hynix Semiconductor, Icheon, Korea
2.7 An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band 4:30 PMSimultaneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression
Y. Kim1, G-S. Byun2, A. Tang1, C-P. Jou3, H-H. Hsieh3, G. Reinman1, J. Cong1, M-C. Chang1
1University of California, Los Angeles, Los Angeles, CA2West Virginia University, Morgantown, WV3TSMC, Hsinchu, Taiwan
2.8 A 7Gb/s/Link Non-Contact Memory Module for Multi-Drop Bus 4:45 PMSystem Using Energy-Equipartitioned Coupled Transmission Line
W-J. Yun, S. Nakano, W. Mizuhara, A. Kosuge, N. Miura, H. Ishikuro, T. KurodaKeio University, Yokohama, Japan
Conclusion 5:00 PM
SESSION 2 Monday February 20th, 1:30 PM
15
PROCESSORS
Session Chair: Joshua Friedrich, IBM, Austin, TXAssociate Chair: Luke Shin, Oracle, Santa Clara, CA
3.1 A 22nm IA Multi-CPU and GPU System-on-Chip 1:30 PMS. Damaraju1, V. George1, S. Jahagirdar1, T. Khondker1, R. Milstrey1, S. Sarkar1, S. Siers1, I. Stolero2, A. Subbiah1
1Intel, Folsom, CA2Intel, Haifa, Israel
3.2 A 32-Core RISC Microprocessor with Network Accelerators, 2:00 PMPower Management and Testability Features
B. Miller, D. Brasili, T. Kiszely, R. Kuhn, R. Mehrotra, M. Salvi, M. Kulkarni, A. Varadharajan,S-H. Yin, W. Lin, A. Hughes, B. Stysiack, V. Kandadi, I. Pragaspathi, D. Hartman, D. Carlson,V. Yalala, T. Xanthopoulos, S. Meninger, E. Crain, M. Spaeth, A. Aina, S. Balasubramanian,J. Vulih, P. Tiwary, D. Lin, R. Kessler, B. Fishbein, A. JainCavium, Marlboro, MA
3.3 The Next-Generation 64b SPARC Core in a T4 SoC Processor 2:30 PMJ. Shin, H. Park, H. Li, A. Smith, Y. Choi, H. Sathianathan, S. Dash, S. Turullols, S. Kim, R. Masleid, G. Konstadinidis, R. Golla, M. Doherty, G. Grohoski, C. McAllisterOracle, Santa Clara, CA
Break 3:00 PM
3.4 32nm x86 OS-Compliant PC On-Chip with Dual-Core Atom® 3:15 PMProcessor and RF WiFi Transceiver
H. Lakdawala1, M. Schaecher2, C-T. Fu1, R. Limaye3, J. Duster1, Y. Tan1, A. Balankutty1, E. Alpman1, C. Lee1, S. Suzuki1, B. Carlton1, H. Kim1, M. Verhelst1, S. Pellerano1, T. Kim2, D. Srivastava1, S. Venkatesan3, H-J. Lee1, P. Vandervoorn1, J. Rizk1, C-H. Jan1, K. Soumyanath1, S. Ramamurthy1
1Intel, Hillsboro, OR; 2Intel, Chandler, AZ; 3Intel, Santa Clara, CA
3.5 An 800MHz 320mW 16-Core Processor with Message-Passing 3:45 PMand Shared-Memory Inter-Core Communication Mechanisms
Z. Yu, K. You, R. Xiao, H. Quan, P. Ou, Y. Ying, H. Yang, M. Jing, X. ZengFudan University, Shanghai, China
3.6 A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor 4:15 PMin 32nm CMOS
S. Jain1, S. Khare1, S. Yada1, A. V1, P. Salihundam1, S. Ramani1, S. Muthukumar1, S. M1, A. Kumar1, S. Gb1, R. Ramanarayanan1, V. Erraguntla1, J. Howard2, S. Vangal2, S. Dighe2, G. Ruhl2, P. Aseron2, H. Wilson2, N. Borkar2, V. De2, S. Borkar2
1Intel, Bangalore, India; 2Intel, Hillsboro, OR
3.7 Resonant Clock Design for a Power-Efficient High-Volume 4:45 PMx86-64 Microprocessor
V. Sathe1, S. Arekapudi2, A. Ishii3, C. Ouyang2, M. Papaefthymiou3,4, S. Naffziger1
1AMD, Fort Collins, CO 2AMD, Sunnyvale, CA3Cyclos Semiconductor, Berkeley, CA; 4University of Michigan, Ann Arbor, MI
3.8 A Reconfigurable Distributed All-Digital Clock Generator Core 5:00 PMwith SSC and Skew Correction in 22nm High-k Tri-Gate LP CMOS
Y. Li1, C. Ornelas2, H. Kim1, H. Lakdawala1, A. Ravi1, K. Soumyanath1
4.1 A Blocker-Tolerant Wideband Noise-Cancelling Receiver 1:30 PMwith a 2dB Noise Figure
D. Murphy1,2, A. Hafez1,2, A. Mirzaei2, M. Mikhemar2, H. Darabi2, M-C. Chang1, A. Abidi11University of California, Los Angeles, Los Angeles, CA2Broadcom, Irvine, CA
4.2 8-Path Tunable RF Notch Filters for Blocker Suppression 2:00 PMA. Ghaffari, E. Klumperink, B. NautaUniversity of Twente, Enschede, The Netherlands
4.3 A Wideband IM3 Cancellation Technique for CMOS Attenuators 2:30 PMW. Cheng, M. Oude Alink, A. Annema, G. Wienk, B. NautaUniversity of Twente, Enschede, The Netherlands
4.4 A 1-to-2.5GHz Phased-Array IC Based on gm-RC All-Pass 2:45 PMTime-Delay Cells
S. Garakoui, E. Klumperink, B. Nauta, F. Van VlietUniversity of Twente, Enschede, The Netherlands
Break 3:00 PM
4.5 A Fully Integrated Dual-Mode CMOS Power Amplifier 3:15 PMfor WCDMA Applications
B. Koo1, T. Joo1, Y. Na2, S. Hong1
1KAIST, Daejeon, Korea2Samsung Electro-Mechanics, Suwon, Korea
4.6 A 28.3mW PA-Closed Loop for Linearity and Efficiency 3:45 PMImprovement Integrated in a +27.1dBm WCDMA CMOS Power Amplifier
S. Kousai, K. Onizuka, T. Yamaguchi, Y. Kuriyama, M. NagaokaToshiba, Kawasaki, Japan
4.7 A Fully Integrated Triple-Band CMOS Power Amplifier 4:15 PMfor WCDMA Mobile Handsets
K. Kanda1, Y. Kawano2, T. Sasaki2, N. Shirai2, T. Tamura2, S. Kawai2, M. Kudo2, T. Murakami2,H. Nakamoto1, N. Hasegawa2, H. Kano2, N. Shimazui2, A. Mineyama3, K. Oishi1, M. Shima4,N. Tamura4, T. Suzuki3, T. Mori1, K. Niratsuka2, S. Yamaura2
4.8 A 45nm SOI CMOS Class-D mm-Wave PA with 4:45 PM>10Vpp Differential Swing
I. Sarkas, A. Balteanu, E. Dacquay, A. Tomkins, S. VoinigescuUniversity of Toronto, Toronto, ON, Canada
Conclusion 5:15 PM
SESSION 4 Monday February 20th, 1:30 PM
17
AUDIO AND POWER CONVERTERS
Session Chair: Wing-Hung Ki, HKUST, Hong Kong, ChinaAssociate Chair: Jed Hurwitz, Consultant, Edinburgh, United Kingdom
5.1 An 8Ω 2.5W 1%-THD 104dB(A)-Dynamic-Range 1:30 PMClass-D Audio Amplifier with an Ultra-Low EMI System and Current Sensing for Speaker Protection
A. Nagari, E. Allier, F. Amiard, V. Binet, C. FraisseST-Ericsson, Grenoble, France
5.2 A 1.5W 10V-Output Class-D Amplifier Using a Boosted Supply 2:00 PMFrom a Single 3.3V Input in Standard 1.8V/3.3V 0.18µm CMOS
B. Serneels, E. Geukens, B. De Muer, T. PiessensICsense, Leuven, Belgium
5.3 A 0.028% THD+N, 91% Power-Efficiency, 3-Level PWM 2:30 PMClass-D Amplifier with a True Differential Front-End
S. Kwon1, I. Kim2, S. Yi1, S. Kang1, S. Lee1, T. Hwang1, B. Moon1, Y. Choi1, H. Sung1, J. Koh1
1Dongbu Hitek, Seoul, Korea2Samsung Electronics, Kyunggi-Do, Korea
5.4 A 41-Phase Switched-Capacitor Power Converter with 2:45 PM3.8mV Output Ripple and 81% Efficiency in Baseline 90nm CMOS
G. Villar PiquéNXP Semiconductors, Eindhoven, The Netherlands
Break 3:00 PM
5.5 A High-Voltage CMOS IC and Embedded System for Distributed 3:15 PMPhotovoltaic Energy Optimization with Over 99% Effective Conversion Efficiency and Insertion Loss Below 0.1%
J. Stauth1,2, M. Seeman2, K. Kesarwani21Dartmouth College, Hanover, NH2Solar Semiconductor, Sunnyvale, CA
5.6 A Maximum Power-Point Tracker without Digital Signal 3:45 PMProcessing in 0.35µm CMOS for Automotive Applications
R. Enne, M. Nikolic, H. ZimmermannVienna University of Technology, Vienna, Austria
5.7 A 40mV Transformer-Reuse Self-Startup Boost Converter 4:15 PMwith MPPT Control for Thermoelectric Energy Harvesting
1KAIST, Daejeon, Korea2Siliconworks, Daejeon, Korea
5.8 A 330nA Energy-Harvesting Charger with Battery 4:45 PMManagement for Solar and Thermoelectric Energy Harvesting
K. Kadirvel1, Y. Ramadass2, U. Lyles1, J. Carpenter1, A. Chandrakasan3, B. Lum-Shue-Chan1
1Texas Instruments, Melbourne, FL2Texas Instruments, Dallas, TX3Massachusetts Institute of Technology, Cambridge, MA
Conclusion 5:15 PM
SESSION 5 Monday February 20th, 1:30 PM
18
IDS
IDS
MEDICAL, DISPLAYS AND IMAGERS
Session Chair: Yusuke Oike, Sony, Atsugi, JapanAssociate Chair: Maysam Ghovanloo, Georgia Institute of Technology, Atlanta, GA
6.1 A Sampling-Based 128×128 Direct Photon-Counting X-Ray Image 1:30 PMSensor with 3 Energy Bins and Spatial Resolution of 60µm/pixel
H-S. Kim1, S-W. Han2, J-H. Yang1, S. Kim2, Y. Kim2, S. Kim2, D-K. Yoon2, J-S. Lee2, J-C. Park2,Y. Sung2, S-D. Lee2, S-T. Ryu1, G-H. Cho1
1KAIST, Daejeon, Korea; 2Samsung Advanced Institute of Technology, Yongin, Korea
6.2 A 1.36µW Adaptive CMOS Image Sensor with Reconfigurable 2:00 PMModes of Operation From Available Energy/Illuminationfor Distributed Wireless Sensor Network
J. Choi, S. Park, J. Cho, E. Yoon; University of Michigan, Ann Arbor, MI
6.3 A 0.5V 4.95µW 11.8fps PWM CMOS Imager with 82dB Dynamic 2:30 PMRange and 0.055% Fixed-Pattern-Noise
M-T. Chung, C-C. Hsieh; National Tsing Hua University, Hsinchu, Taiwan
6.4 A Capacitive Touch Controller Robust to Display Noise 2:45 PMfor Ultrathin Touch Screen Displays
K-D. Kim, S-H. Byun, Y-K. Choi, J-H. Baek, H-H. Cho, J-K. Park, H-Y. Ahn, C-J. Lee, M-S. Cho,J-H. Lee, S-W. Kim, H-D. Kwon, Y-Y. Choi, H. Na, J. Park, Y-J. Shin, K. Jang, G. Hwang, M. LeeSamsung Electronics, Yongin, Korea
Break 3:00 PM
6.5 A 160μA Biopotential Acquisition ASIC with Fully 3:15 PMIntegrated IA and Motion-Artifact Suppression
N. Van Helleputte1, S. Kim1, H. Kim1, J. Kim2, C. Van Hoof1,3, R. Yazicioglu1
1imec, Heverlee, Belgium; 2Samsung Advanced Institute of Technology, Yongin, Korea3KU Leuven, Leuven, Belgium
6.6 CMOS Capacitive Biosensor with Enhanced Sensitivity 3:45 PMfor Label-Free DNA Detection
K-H. Lee, S. Choi, J. Lee, J-B. Yoon, G-H. Cho; KAIST, Daejeon, Korea
6.7 A 100Mphoton/s Time-Resolved Mini-Silicon Photomultiplier 4:00 PMwith On-Chip Fluorescence Lifetime Estimation in 0.13μm CMOS Imaging Technology
D. Tyndall1, B. Rae2, D. Li3, J. Richardson4, J. Arlt1, R. Henderson1
1University of Edinburgh, Edinburgh, United Kingdom2STMicroelectronics, Edinburgh, United Kingdom3University of Sussex, Brighton, United Kingdom4Dialog Semiconductor, Edinburgh, United Kingdom
6.8 A Wireless Magnetoresistive Sensing System for 4:15 PMan Intra-Oral Tongue-Computer Interface
H. Park1, B. Gosselin2, M. Kiani1, H-M. Lee1, J. Kim1, X. Huo1, M. Ghovanloo1
1Georgia Institute of Technology, Atlanta, GA; 2Laval University, Quebec, QC, Canada
6.9 A CMOS 10kpixel Baseline-Free Magnetic Bead Detector 4:45 PMwith Column-Parallel Readout for Miniaturized Immunoassays
S. Gambini, K. Skucha, P. Liu, J. Kim, R. Krigel, R. Mathies, B. BoserUniversity of California at Berkeley, Berkeley, CA
Conclusion 5:15 PM
SESSION 6 Monday February 20th, 1:30 PM
19
IDS
ADS
ACADEMIC DEMONSTRATION SESSION (ADS)*
Monday, February 20th6.8 A Wireless Magnetoresistive Sensing System for 4:15 PM
an Intra-Oral Tongue-Computer Interface
Tuesday, February 21st10.6 3D-MAPS: 3D Massively Parallel Processor 10:45 AM
with Stacked Memory
10.7 Centip3De: A 3930DMIPS/W Configurable Near-Threshold 11:15 AM3D Stacked System with 64 ARM Cortex-M3 Cores
11.5 A ±0.4°C (3σ) -70 to 200°C Time-Domain Temperature 10:15 AMSensor Based on Heat Diffusion in Si and SiO2
12.4 A 320mW 342GOPS Real-Time Moving Object Recognition 3:15 PMProcessor for HD 720p Video Streams
15.1 A 1kPixel CMOS Camera Chip for 25fps Real-Time 1:30 PMTerahertz Imaging Applications
16.8 Voltage-Boosting Wireless Power Delivery System with Fast 5:00 PMLoad Tracker by ΔΣ-Modulated Sub-Harmonic Resonant Switching
17.2 A 259.6μW Nonlinear HRV-EEG Chaos Processor with Body Channel 2:00 PMCommunication Interface for Mental Health Monitoring
17.3 A Sub-10nA DC-Balanced Adaptive Stimulator IC with Multimodal 2:30 PMSensor for Compact Electro-Acupuncture System
Wednesday, February 22nd22.2 A Global-Shutter CMOS Image Sensor with Readout 9:00 AM
Speed of 1Tpixel/s Burst and 780Mpixel/s Continuous
25.2 Over-10×-Extended-Lifetime 76%-Reduced-Error Solid-State 2:00 PMDrives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme
26.4 An Interference-Aware 5.8GHz Wake-Up Radio for ETCS 3:15 PM
28.4 A 200mV 32b Subthreshold Processor with Adaptive 2:45 PMSupply Voltage Control
2020
ISSCC 2012 is expanding the industrial demonstration event introduced last year to includethe Academic Demonstration Session (ADS), to be held on Monday February 20th, from 4 to7 pm, Golden Gate Hall. ADS will feature live demonstrations of selected ICs presented byacademics in regular paper sessions. ADS is intended to demonstrate real-life applicationsmade possible by new ICs presented this year. In the Advance Program, papers for whichdemonstrations are available will be notated by the symbol ADS,
*ADS may include additional demonstrations of work reported at the Student Research Preview.
ADS
ES3: Technologies that Could Change the World – You Decide!
Organizer: Jed Hurwitz, Broadcom, Edinburgh, United Kingdom
Chair: Jafar Savoj, Xilinx, San Jose, CA
Often a new technology comes along that is just plain different than incumbent solutions orapproaches. This session looks at a number of recent ideas that are asking us to re-assessthe way things are done today. It should be an entertaining evening, providing an overview ofthe new technologies, their key benefits (and weaknesses) and an update on where they nowsit, and which barriers and markets they may conquer.
There will be an opportunity for the audience to question the speakers, as there will undoubt-edly be interesting alternative viewpoints!
Time Topic
8:00 MEMS-Based Resonators and Oscillators are Now Replacing QuartzAaron Partridge, SiTime, Sunnyvale, CA
8:25 Thermal Diffusivity Sensors: Temperature Sensors that Scale! Kofi Makinwa, Delft University of Technology,
Delft, The Netherlands
8:50 VCO-Based Quantizers: Has Their Time Arrived? Michael H. Perrott, Masdar Institute of Science and Technology,
Abu Dhabi, United Arab Emirates
9:15 Continuous Time DSPs Yannis Tsividis, Columbia University, New York, NY
9:40 Analog Syntheses: Computer-Aided Design to Secure Analog Design Qualityand Productivity
Georges Gielen, Katholik University of Leuven, Leuven, Belgium
EVENING SESSIONS Monday February 20th, 8:00 PM
21
ES4: Optical PCB Interconnects, Niche or Mainstream?
Efforts in the area of optical backplane technology have been underway for several years, generating significant interest. Recently, these efforts have led to discussions regarding therole of embedded optics for chip-to-chip communication on printed circuit boards. A consensus appears to be emerging that PCB interconnects for mainframes and high-end ser-vers will leverage optical technologies, but will these approaches ever go mainstream? Inthis evening session, we will review the latest in optical interconnect-related circuit design,the prospects for optics use in mainstream I/O applications, and to provide comparison tocopper-based solutions and associated roadmaps.
Time Topic
8:00 Optical Interconnects – Why We Will Have To Use ThemDavid Miller Stanford University, Stanford, CA
8:30 Optical PCB Interconnects For Computing Applications: From Niche to Mainstream
Bert Offrein IBM Research, Zurich, Switzerland
9:00 Integrated Silicon Photonics and Applications In and Around PC/Servers
Mario Paniccia, Intel, Santa Clara, CA
9:30 The Final Push to Mainstream; Can Integrated Optics Learn From Integrated Magnetics?
Keishi Ohashi, NEC, Tsukuba, Japan
EP1: “Is RF Doomed to Digitization? What Shall RF Circuit Designers Do?”
Organizer: R. Bogdan Staszewski, Delft University of Technology, Delft, The Netherlands
Moderator: Jacques Rudell, University of Washington, Seattle, WA
The most recent trend in RF design is toward more and more digital content. This is very in-triguing but, at the same time, it could be quite challenging to traditionally-minded designersas well as new entrants who have been educated using contemporary textbooks that are yetto be updated. What is the ultimate destiny of RF architectural and circuit design? Will RFshare the same digitization fate as, for example, the audio on cellular phones? Are there anyalternatives or safe havens far from the digital encroachment? Seven leading experts fromindustry and academia will debate this controversial topic.
Panelists:Borivoje Nikolic, UC Berkeley, Berkeley, CAOren Eliezer, Xtendwave, Plano, TXKen Hansen, Freescale, Austin, TXRik Jos, NXP, Nijmegen, The NetherlandsAndreas Kaiser, IEMN-ISEN, Lille, FranceLawrence Loh, Mediatek, Hsinchu, TaiwanAkira Matsuzawa, Tokyo Institute of Technology, Tokyo, Japan
EVENING SESSION Monday February 20th, 8:00 PM
22
MULTI GB/s RECEIVER AND PARALLEL I/O TECHNIQUES
Session Chair: Bob Payne, Texas Instruments, Dallas, TXAssociate Chair: Tatsuya Saito, Hitachi, Kawasaki, Kanagawa, Japan
7.1 An 18.6Gb/s Double-Sampling Receiver in 65nm CMOS 8:30 AMfor Ultra-Low-Power Optical Communication
M. Honarvar Nazari, A. Emami-NeyestanakCalifornia Institute of Technology, Pasadena, CA
1Pohang University of Science and Technology, Pohang, Korea2Samsung Electronics, Hwasung, Korea
7.5 A 4.1pJ/b 16Gb/s Coded Differential Bidirectional 10:45 AMParallel Electrical Link
A. Amirkhany1, K. Kaviani1, A. Abbasfar1, F. Shuaeb2, W. Beyene1, C. Hoshino3, C. Madden1,K. Chang1, C. Yuan1
1Rambus, Sunnyvale, CA2Rambus, Bangalore, India3Rambus, Tokyo, Japan
7.6 A 5Gb/s Single-Ended Parallel Receiver with Adaptive 11:15 AMFEXT Cancellation
S-K. Lee, H. Ha, H-J. Park, J-Y. SimPohang University of Science and Technology, Pohang, Korea
7.7 A Compact Low-Power 3D I/O in 45nm CMOS 11:45 AMY. Liu, W. Luk, D. FriedmanIBM T. J. Watson, Yorktown Heights, NY
Conclusion 12:15 PM
SESSION 7 Tuesday February 21st, 8:30 AM
23
IDS
DELTA-SIGMA CONVERTERS
Session Chair: Brian Brandt, Maxim Integrated Products, North Chelmsford, MAAssociate Chair: Gerhard Mitteregger, Intel Mobile, Villach, Austria
8.1 An LC Bandpass ΔΣ ADC with 70dB SNDR Over 20MHz Bandwidth 8:30 AMUsing CMOS DACs
J. Harrison1, M. Nesselroth1, R. Mamuad1, A. Behzad2, A. Adams1, S. Avery1
1Broadcom, Sydney, Australia2Broadcom, San Diego, CA
8.2 A 12mW Low-Power Continuous-Time Bandpass ΔΣ Modulator 9:00 AMwith 58dB SNDR and 24MHz Bandwidth at 200MHz IF
H. Chae1,2, J. Jeong1, G. Manganaro2, M. Flynn1
1University of Michigan, Ann Arbor, MI2Analog Devices, Wilmington, MA
8.3 A DC-to-1GHz Tunable RF ΔΣ ADC Achieving DR = 74dB 9:30 AMand BW = 150MHz at f0 = 450MHz Using 550mW
H. Shibata1, R. Schreier1, W. Yang2, A. Shaikh2,3, D. Paterson2, T. Caldwell1, D. Alldred1, P. Lai21Analog Devices, Toronto, ON, Canada2Analog Devices, Wilmington, MA3now independent consultant, Lahore, Pakistan
Break 10:00 AM
8.4 A 16mW 78dB-SNDR 10MHz-BW CT-ΔΣ ADC Using 10:15 AMResidue-Cancelling VCO-Based Quantizer
K. Reddy, S. Rao, R. Inti, B. Young, A. Elshazly, M. Talegaonkar, P. HanumoluOregon State University, Corvallis, OR
8.5 A 72dB-DR ΔΣ CT Modulator Using Digitally Estimated Auxiliary 10:45 AMDAC Linearization Achieving 88fJ/conv in a 25MHz BW
P. Witte1, J. Kauffman1, J. Becker1, Y. Manoli2, M. Ortmanns1
1Ulm University, Ulm, Germany2University of Freiburg - IMTEK, Freiburg, Germany
8.6 A 15mW 3.6GS/s CT-ΔΣ ADC with 36MHz Bandwidth 11:15 AMand 83dB DR in 90nm CMOS
P. Shettigar, S. PavanIIT Madras, Chennai, India
8.7 A 20mW 61dB SNDR (60MHz BW) 1b 3rd-Order Continuous-Time 11:45 AMDelta-Sigma Modulator Clocked at 6GHz in 45nm CMOS
V. Srinivasan, V. Wang, P. Satarzadeh, B. Haroun, M. CorsiTexas Instruments, Dallas, TX
Conclusion 12:15 PM
SESSION 8 Tuesday February 21st, 8:30 AM
24
WIRELESS TRANSCEIVER TECHNIQUES
Session Chair: Sven Mattisson, Ericsson, Lund, SwedenAssociate Chair: Shouhei Kousai, Toshiba, Kawasaki, Japan
9.1 A 40MHz-to-1GHz Fully Integrated Multistandard Silicon 8:30 AMTuner in 80nm CMOS
J. Greenberg1, F. De Bernardinis2, C. Tinella2, A. Milani2, J. Pan1, P. Uggetti2, M. Sosio3, S. Dai1, S. Tang1, G. Cesura2, G. Gandolfi2, V. Colonna2, R. Castello2,3
1Marvell, Santa Clara, CA2Marvell, Pavia, Italy3University of Pavia, Pavia, Italy
9.2 A Multiband Multimode Transmitter without Driver Amplifier 9:00 AMO. Oliaei, M. Kirschenmann, D. Newman, K. Hausmann, H. Xie, P. Rakers, M. Rahman, M. Gomez, C. Yu, B. Gilsdorf, K. SakamotoFujitsu Semiconductor Wireless, Tempe, AZ
9.3 Active Feedback Receiver with Integrated Tunable RF Channel 9:30 AMSelectivity, Distortion Cancelling, 48dB Stopband Rejection and >+12dBm Wideband IIP3, Occupying <0.06mm2 in 65nm CMOS
S. Youssef, R. Van der Zee, B. NautaUniversity of Twente, Enschede, The Netherlands
Break 10:00 AM
9.4 A 20dBm 2.4GHz Digital Outphasing Transmitter for WLAN 10:15 AMApplication in 32nm CMOS
P. Madoglio1, A. Ravi1, H. Xu1, K. Chandrashekar1, M. Verhelst1, S. Pellerano1, L. Cuellar2, M. Aguirre2, M. Sajadieh3, O. Degani4, H. Lakdawala1, Y. Palaskas1
1Intel, Hillsboro, OR2Intel, Guadalajara, Mexico3Intel, Santa Clara, CA4Intel, Haifa, Israel
9.5 A 60GHz Outphasing Transmitter in 40nm CMOS 10:30 AMwith 15.6dBm Output Power
D. Zhao, S. Kulkarni, P. ReynaertKU Leuven, Leuven, Belgium
9.6 A 4-in-1 (WiFi/BT/FM/GPS) Connectivity SoC with Enhanced 10:45 AMCo-Existence Performance in 65nm CMOS
Y-H. Chung1, M. Chen1, W-K. Hong1, J-W. Lai1, S-J. Wong2, C-W. Kuan1, H-L. Chu1, C. Lee1,C-F. Liao1, H-Y. Liu1, H-K. Hsu1, L-C. Ko1, K-H. Chen1, C-H. Lu1, T-M. Chen1, Y. Hsueh1,C. Chang1, Y-H. Cho1, C-H. Shen1, Y. Sun2, E-C. Low2, X. Jiang2, D. Hu2, W. Shu2, J-R. Chen1,J-L. Hsu1, C-J. Hsu1, J-H. Zhan1, O. Shana¡¦A2, G-K. Dehng1, G. Chien3
1MediaTek, Hsinchu, Taiwan2MediaTek, Singapore3MediaTek, San Jose, CA
9.7 A 1.5-to-5.0GHz Input-Matched +2dBm P1dB All-Passive 11:15 AMSwitched-Capacitor Beamforming Receiver Front-End in 65nm CMOS
M. Soer1, E. Klumperink1, B. Nauta1, F. Van Vliet1,2
1University of Twente, Enschede, The Netherlands2TNO Science and Industry, The Hague, The Netherlands
Conclusion 11:30 AM
SESSION 9 Tuesday February 21st, 8:30 AM
25
HIGH-PERFORMANCE DIGITAL
Session Chair: Lew Chua-Eoan, Qualcomm, San Diego, CAAssociate Chair: Se-Hyun Yang, Samsung Electronics, Yongin, Korea
10.1 A 280mV-to-1.1V 256b Reconfigurable SIMD Vector 8:30 AMPermutation Engine with 2-Dimensional Shuffle in 22nm CMOS
S. Hsu, A. Agarwal, M. Anders, S. Mathew, H. Kaul, F. Sheikh, R. KrishnamurthyIntel, Hillsboro, OR
10.2 A Source-Synchronous 90Gb/s Capacitively Driven Serial 9:00 AMOn-Chip Link Over 6mm in 65nm CMOS
D. Walter, S. Höppner, H. Eisenreich, G. Ellguth, S. Henker, S. Hänzsche, R. Schüffny, M. Winter, G. FettweisTechnical University Dresden, Dresden, Germany
10.3 A 1.45GHz 52-to-162GFLOPS/W Variable-Precision 9:30 AMFloating-Point Fused Multiply-Add Unit with Certainty Tracking in 32nm CMOS
H. Kaul, M. Anders, S. Mathew, S. Hsu, A. Agarwal, F. Sheikh, R. Krishnamurthy, S. BorkarIntel, Hillsboro, OR
10.4 A 2.05GVertices/s 151mW Lighting Accelerator 9:45 AMfor 3D Graphics Vertex and Pixel Shading in 32nm CMOS
F. Sheikh, S. Mathew, M. Anders, H. Kaul, S. Hsu, A. Agarwal, R. Krishnamurthy, S. BorkarIntel, Hillsboro, OR
Break 10:00 AM
10.5 A 3D System Prototype of an eDRAM Cache Stacked Over 10:15 AMProcessor-Like Logic Using Through-Silicon Vias
M. Wordeman1, J. Silberman1, G. Maier2, M. Scheuermann1
1IBM T. J. Watson, Yorktown Heights, NY2IBM Systems and Technology Group, Fishkill, NY
10.6 3D-MAPS: 3D Massively Parallel Processor 10:45 AMwith Stacked Memory
D. Kim1, K. Athikulwongse1, M. Healy1, M. Hossain1, M. Jung1, I. Khorosh1, G. Kumar1,Y-J. Lee1, D. Lewis1, T-W. Lin1, C. Liu1, S. Panth1, M. Pathak1, M. Ren1, G. Shen1, T. Song1,D. Woo1, X. Zhao1, J. Kim2, H. Choi3, G. Loh1, H-H. Lee1, S. Lim1
1Georgia Institute of Technology, Atlanta, GA2KAIST, Daejeon, Korea3Amkor Technology, Seoul, Korea
10.7 Centip3De: A 3930DMIPS/W Configurable Near-Threshold 11:15 AM3D Stacked System with 64 ARM Cortex-M3 Cores
D. Fick, R. Dreslinski, B. Giridhar, G. Kim, S. Seo, M. Fojtik, S. Satpathy, Y. Lee, D. Kim, N. Liu, M. Wieckowski, G. Chen, T. Mudge, D. Sylvester, D. BlaauwUniversity of Michigan, Ann Arbor, MI
10.8 K Computer: 8.162 PetaFLOPS Massively Parallel Scalar 11:45 AMSupercomputer Built with Over 548k Cores
H. Miyazaki1, Y. Kusano1, H. Okano1, T. Nakada1, K. Seki1, T. Shimizu1, N. Shinjo1, F. Shoji2, A. Uno2, M. Kurokawa2
1Fujitsu, Kanagawa, Japan2RIKEN, Hyogo, Japan
Conclusion 12:15 PM
SESSION 10 Tuesday February 21st, 8:30 AM
26
IDS
ADS
ADS
SENSORS & MEMs
Session Chair: Christoph Hagleitner, IBM Research, Ruschlikon, SwitzerlandAssociate Chair: Maurits Ortmanns, University of Ulm, Ulm, Germany
11.1 A ΔΣ Interface for MEMS Accelerometers Using Electrostatic 8:30 AMSpring-Constant Modulation for Cancellation of Bondwire Capacitance Drift
P. Lajevardi1, V. Petkov2, B. Murmann1
1Stanford University, Stanford, CA2Robert Bosch, Palo Alto, CA
11.2 A Capacitance-to-Digital Converter for Displacement Sensing 9:00 AMwith 17b Resolution and 20µs Conversion Time
S. Xia, K. Makinwa, S. NihtianovDelft University of Technology, Delft, The Netherlands
11.3 A 50μW Biasing Feedback Loop with 6ms Settling Time 9:15 AMfor a MEMS Microphone with Digital Output
J. Van den BoomNXP Semiconductors, Nijmegen, The Netherlands
11.4 ASIC for a Resonant Wireless Pressure-Sensing System 9:30 AMfor Harsh Environments Achieving ±2% Error Between -40 and 150°C Using Q-Based Temperature Compensation
11.5 A ±0.4°C (3σ) -70 to 200°C Time-Domain Temperature 10:15 AMSensor Based on Heat Diffusion in Si and SiO2
C. Van Vroonhoven1, D. D’Aquino2, K. Makinwa1
1Delft University of Technology, Delft, The Netherlands2National Semiconductor, Santa Clara, CA
11.6 A Temperature-to-Digital Converter for a MEMS-Based 10:45 AMProgrammable Oscillator with Better Than ±0.5ppm Frequency Stability
M. Perrott1, J. Salvia2, F. Lee3, A. Partridge2, S. Mukherjee2, C. Arft2, J-T. Kim2, N. Arumugam2,P. Gupta2, S. Tabatabaei2, S. Pamarti4, H. Lee2, F. Assaderaghi21Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates2SiTime, Sunnyvale, CA3Fairchild Semiconductor, San Jose, CA4University of California, Los Angeles, Los Angeles, CA
11.7 A CMOS Temperature Sensor with a Voltage-Calibrated 11:15 AMInaccuracy of ±0.15°C (3σ) From -55 to 125°C
K. Souri, Y. Chae, K. MakinwaDelft University of Technology, Delft, The Netherlands
J. Shor, K. Luria, D. ZilbermanIntel, Yakum, Israel
Conclusion 12:15 PM
SESSION 11 Tuesday February 21st, 8:30 AM
27
IDS
ADS
MULTIMEDIA & COMMUNICATIONS SOCs
Session Chair: Byeong-Gyu Nam, Chungnam National University, Daejeon, KoreaAssociate Chair: Shannon Morton, Nvidia, Bristol, United Kingdom
12.1 A 32nm High-k Metal Gate Application Processor 1:30 PMwith GHz Multi-Core CPU
S-H. Yang, S. Lee, J. Lee, J. Cho, H-J. Lee, D. Cho, J. Heo, S. Cho, Y. Shin, S. Yun, E. Kim,U. Cho, J. Son, C. Kim, J. Youn, Y. Chung, S. Park, S. HwangSamsung Electronics, Yongin, Korea
12.2 A 335Mb/s 3.9mm2 65nm CMOS Flexible MIMO 2:00 PMDetection-Decoding Engine Achieving 4G Wireless Data Rates
M. Winter1, S. Kunze1, E. Perez Adeva1, B. Mennenga1, E. Matûs1, G. Fettweis1, H. Eisenreich1,G. Ellguth1, S. Höppner1, S. Scholze1, R. Schüffny1, T. Kobori21Technical University Dresden, Dresden, Germany2NEC, Tokyo, Japan
12.3 A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion 2:30 PMTransceiver with Low-Power Analog and Digital Baseband Circuitry
K. Okada1, K. Kondou2, M. Miyahara1, M. Shinagawa2, H. Asada1, R. Minami1, T. Yamaguchi1,A. Musa1, Y. Tsukui1, Y. Asakura2, S. Tamonoki2, H. Yamagishi2, Y. Hino2, T. Sato1, H. Sakaguchi1, N. Shimasaki1, T. Ito1, Y. Takeuchi1, N. Li1, Q. Bu1, R. Murakami1, K. Bunsen1, K. Matsushita1, M. Noda2, A. Matsuzawa1
1Tokyo Institute of Technology, Tokyo, Japan2Sony, Tokyo, Japan
Break 3:00 PM
12.4 A 320mW 342GOPS Real-Time Moving Object Recognition 3:15 PMProcessor for HD 720p Video Streams
J. Oh, G. Kim, J. Park, I. Hong, S. Lee, H-J. YooKAIST, Daejeon, Korea
12.5 A 464GOPS 620GOPS/W Heterogeneous Multi-Core 3:45 PMSoC for Image-Recognition Applications
Y. Tanabe, M. Sumiyoshi, M. Nishiyama, I. Yamazaki, S. Fujii, K. Kimura, T. Aoyama, M. Banno, H. Hayashi, T. MiyamoriToshiba, Kawasaki, Japan
12.6 A 2Gpixel/s H.264/AVC HP/MVC Video Decoder Chip 4:15 PMfor Super Hi-Vision and 3DTV/FTV Applications
D. Zhou1, J. Zhou1, J. Zhu2, P. Liu2, S. Goto1
1Waseda University, Kitakyushu, Japan2Shanghai Jiao Tong University, Shanghai, China
12.7 A True Multistandard, Programmable, Low-Power, 4:45 PMFull HD Video-Codec Engine for Smartphone SoC
M. Mehendale1, S. Das1, M. Sharma1, M. Mody1, R. Reddy1, J. Meehan2, H. Tamama3, B. Carlson3, M. Polley3
Session Chair: Leland Chang, IBM T.J. Watson, Yorktown Heights, NYAssociate Chair: Michael Clinton, Texas Instruments, Dallas, TX
13.1 A 4.6GHz 162Mb SRAM Design in 22nm Tri-Gate CMOS Technology 1:30 PMwith Integrated Active VMIN-Enhancing Assist Circuitry
E. Karl, Y. Wang, Y-G. Ng, Z. Guo, F. Hamzaoglu, U. Bhattacharya, K. Zhang, K. Mistry, M. BohrIntel, Hillsboro, OR
13.2 A 6T SRAM with a Carrier-Injection Scheme to Pinpoint 2:00 PMand Repair Fails That Achieves 57% Faster Read and 31% Lower Read Energy
K. Miyaji1, T. Suzuki2, S. Miyano2, K. Takeuchi11University of Tokyo, Tokyo, Japan2Semiconductor Technology Academic Research Center, Yokohama, Japan
13.3 Capacitive-Coupling Wordline Boosting with Self-Induced 2:30 PMVCC Collapse for Write VMIN Reduction in 22-nm 8T SRAM
J. Kulkarni, B. Geuskens, T. Karnik, M. Khellah, J. Tschanz, V. DeIntel, Hillsboro, OR
13.4 A 28nm 360ps-Access-Time Two-Port SRAM with a Time-Sharing 2:45 PMScheme to Circumvent Read Disturbs
Y. Ishii1, Y. Tsukamoto1, K. Nii1, H. Fujiwara1, M. Yabuuchi1, K. Tanaka2, S. Tanaka1, Y. Shimazaki11Renesas Electronics, Kodaira, Tokyo, Japan2Renesas Electronics, Itami, Hyogo, Japan
Break 3:00 PM
SESSION 13 Tuesday February 21st, 1:30 PM
29
DIGITAL CLOCKING & PLLs
Session Chair: Anthony Hill, Texas Instruments, Dallas, TXAssociate Chair: Hiroo Hayashi, Toshiba Semiconductor, Kawasaki, Japan
14.1 A 0.004mm2 250µW ΔΣ TDC with Time-Difference Accumulator 3:15 PMand a 0.012mm2 2.5mW Bang-Bang Digital PLL Using PRNG for Low-Power SoC Applications
J-P. Hong, S-J. Kim, J. Liu, N. Xing, T-K. Jang, J. Park, J. Kim, T. Kim, H. ParkSamsung Electronics, Yongin, Korea
14.2 A 1.5GHz 890μW Digital MDLL with 400fsrms Integrated Jitter, 3:45 PM-55.6dBc Reference Spur and 20fs/mV Supply-Noise Sensitivity Using 1b TDC
A. Elshazly, R. Inti, B. Young, P. HanumoluOregon State University, Corvallis, OR
14.3 A 6.7MHz-to-1.24GHz 0.0318mm2 Fast-Locking All-Digital 4:15 PMDLL in 90nm CMOS
15.1 A 1kPixel CMOS Camera Chip for 25fps Real-Time 1:30 PMTerahertz Imaging Applications
H. Sherry1,2,3, J. Grzyb2, Y. Zhao2, R. Al Hadi2, A. Cathelin1, A. Kaiser3, U. Pfeiffer2
1STMicroelectronics, Crolles, France; 2University of Wuppertal, Wuppertal, Germany3IEMN / ISEN, Lille, France
15.2 280GHz and 860GHz Image Sensors Using Schottky-Barrier 2:00 PMDiodes in 0.13µm Digital CMOS
R. Han1,2, Y. Zhang3, Y. Kim3, D. Kim3, H. Shichijo3, E. Afshari2, K. O3
1University of Florida, Gainesville, FL; 2Cornell University, Ithaca, NY3University of Texas at Dallas, Richardson, TX
15.3 A 0.28THz 4×4 Power-Generation and Beam-Steering Array 2:30 PMK. Sengupta, A. Hajimiri; California Institute of Technology, Pasadena, CA
15.4 A 283-to-296GHz VCO with 0.76mW Peak Output 2:45 PMPower in 65nm CMOS
Y. M. Tousi, O. Momeni, E. Afshari; Cornell University, Ithaca, NYBreak 3:00 PM
15.5 A 1V 19.3dBm 79GHz Power Amplifier in 65nm CMOS 3:15 PMK-Y. Wang, T-Y. Chang, C-K. WangNational Taiwan University, Taipei, Taiwan
15.6 A 9% Power Efficiency 121-to-137GHz Phase-Controlled 3:30 PMPush-Push Frequency Quadrupler in 0.13µm SiGe BiCMOS
Y. Wang1,2, W. Goh1, Y-Z. Xiong2,3
1Nanyang Technological University, Singapore; 2Institute of Microelectronics, Singapore3MicroArray Technologies, Chengdu, China
15.7 A 144GHz 0.76cm-Resolution Sub-Carrier SAR Phase Radar 3:45 PMfor 3D Imaging in 65nm CMOS
A. Tang1, G. Virbila1, D. Murphy1, F. Hsiao1, Y. Wang1, Q. Gu2, Z. Xu3, Y. Wu4, M. Zhu1, M-C. Chang1
1University of California, Los Angeles, Los Angeles, CA; 2University of Florida, Gainsville, FL3HRL, Malibu, CA; 4Northrop Grumman Aerospace Systems, Los Angeles, CA
15.8 A 2Gb/s-Throughput CMOS Transceiver Chipset with In-Package 4:15 PMAntenna for 60GHz Short-Range Wireless Communication
T. Mitomo, Y. Tsutsumi, H. Hoshino, M. Hosoya, T. Wang, Y. Tsubouchi, R. Tachibana, A. Sai,Y. Kobayashi, D. Kurose, T. Ito, K. Ban, T. Tandai, T. TomizawaToshiba, Kawasaki, Japan
15.9 A Low-Power 57-to-66GHz Transceiver in 40nm LP CMOS 4:45 PMwith -17dB EVM at 7Gb/s
V. Vidojkovic1, G. Mangraviti1,2, K. Khalaf1,2, V. Szortyka1,2, K. Vaesen1, W. Van Thillo1, B. Parvais1, M. Libois1, S. Thijs1, J. Long3, C. Soens1, P. Wambacq1,2
1imec, Heverlee, Belgium; 2Vrije Universiteit Brussel, Brussel, Belgium3Delft University of Technology, Delft, The Netherlands
15.10 A 4-Path 42.8-to-49.5GHz LO Generation with Automatic 5:00 PMPhase Tuning for 60GHz Phased-Array Receivers
L. Wu, A. Li, H. LuongHong Kong University of Science and Technology, Hong Kong, China
16.1 Near Independently Regulated 5-Output Single-Inductor 1:30 PMDC-DC Buck Converter Delivering 1.2W/mm2 in 65 nm CMOS
C-W. Kuan, H-C. LinMediaTek, Hsinchu, Taiwan
16.2 A High-Stability Emulated Absolute Current Hysteretic 2:00 PMControl Single-Inductor 5-Output Switching DC-DC Converter with Energy Sharing and Balancing
S-W. Wang1, G-H. Cho2, G-H. Cho1
1KAIST, Daejeon, Korea2JDA, Daejeon, Korea
16.3 Off-the-Line Primary-Side Regulation LED Lamp Driver 2:30 PMwith Single-Stage PFC and TRIAC Dimming Using LED Forward Voltage and Duty Variation Tracking Control
J. Hwang, M. Jung, D. Kim, J. Lee, M. Jung, J. ShinAnaperior Technology, Seoul, Korea
Break 3:00 PM
16.4 A 0.18μm CMOS 91%-Efficiency 0.1-to-2A Scalable 3:15 PMBuck-Boost DC-DC Converter for LED Drivers
P. Malcovati1, M. Belloni1, F. Gozzini2, C. Bazzani2, A. Baschirotto3
1University of Pavia, Pavia, Italy2Mindspeed, Newport Beach, CA3University of Milano-Bicocca, Milano, Italy
16.5 A 92% Efficiency Wide-Input Voltage Range Switched-Capacitor 3:45 PMDC-DC Converter
V. Ng, S. SandersUniversity of California at Berkeley, Berkeley, CA
16.6 An Optimized Driver for SiC JFET-Based Switches Delivering 4:15 PMMore Than 99% Efficiency
K. Norling, C. Lindholm, D. DraxelmayrInfineon Technologies, Villach, Austria
16.7 An Adaptive Reconfigurable Active Voltage Doubler/Rectifier 4:45 PMfor Extended-Range Inductive Power Transmission
H-M. Lee, M. GhovanlooGeorgia Institute of Technology, Atlanta, GA
16.8 Voltage-Boosting Wireless Power Delivery System 5:00 PMwith Fast Load Tracker by ΔΣ-Modulated Sub-Harmonic Resonant Switching
R. Shinoda, K. Tomita, Y. Hasegawa, H. IshikuroKeio University, Yokohama, Japan
17.1 An 8-Channel Scalable EEG Acquisition SoC with Fully Integrated 1:30 PMPatient-Specific Seizure Classification and Recording Processor
J. Yoo1, L. Yan2, D. El-Damak3, M. Bin Altaf1, A. Shoeb4, H-J. Yoo5, A. Chandrakasan3
1Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates2imec, Leuven, Belgium3Massachusetts Institute of Technology, Cambridge, MA4Massachusetts General Hospital, Harvard Medical School, Cambridge, MA5KAIST, Daejeon, Korea
17.2 A 259.6μW Nonlinear HRV-EEG Chaos Processor 2:00 PMwith Body Channel Communication Interface for Mental Health Monitoring
T. Roh, S. Hong, H. Cho, H-J. YooKAIST, Daejeon, Korea
17.3 A Sub-10nA DC-Balanced Adaptive Stimulator IC 2:30 PMwith Multimodal Sensor for Compact Electro-Acupuncture System
K. Song, H. Lee, S. Hong, H. Cho, H-J. YooKAIST, Daejeon, Korea
Break 3:00 PM
17.4 A Batteryless 19μW MICS/ISM-Band Energy Harvesting 3:15 PMBody Area Sensor Node SoC
F. Zhang1, Y. Zhang2, J. Silver1, Y. Shakhsheer2, M. Nagaraju1, A. Klinefelter2, J. Pandey1, J. Boley2, E. Carlson1, A. Shrivastava2, B. Otis1, B. Calhoun2
1University of Washington, Seattle, WA2University of Virginia, Charlottesville, VA
17.5 A 1V 5mA Multimode IEEE 802.15.6/Bluetooth Low-Energy WBAN 3:45 PMTransceiver for Biotelemetry Applications
A. Wong, M. Dawkins, G. Devita, N. Kasparidis, A. Katsiamis, O. King, F. Lauria, J. Schiff, A. BurdettToumaz, Abingdon, United Kingdom
17.6 A mm-Sized Wirelessly Powered and Remotely Controlled 4:15 PMLocomotive Implantable Device
A. Yakovlev, D. Pivonka, T. Meng, A. PoonStanford University, Stanford, CA
17.7 A CMOS Impedance Cytometer for 3D Flowing Single-Cell 4:45 PMReal-Time Analysis with ΔΣ Error Correction
K-H. Lee1, J. Nam2, S. Choi1, H. Lim2, S. Shin2, G-H. Cho1
1KAIST, Daejeon, Korea2Korea University, Seoul, Korea
Conclusion 5:15 PM
SESSION 17 Tuesday February 21st, 1:30 PM
35
ADS
ADS
INDUSTRY DEMONSTRATION SESSION (IDS)
36
ISSCC 2012 continues this year with the Industry Demonstration Session (IDS), to be held on Tuesday February 21st, from 4 to 7 pm, Golden Gate Hall. IDS will feature live demonstrations of selected ICs presented by industry in regular paper sessions. IDS is intended to demonstrate real-life applications made possible by new ICs presented this year.In the Advance Program, papers for which demonstrations are available will be notated bythe symbol IDS. IDS
Monday, February 20th3.1 A 22nm IA Multi-CPU and GPU System-on-Chip 1:30 PM
3.6 A 280mV-to-1.2V Wide-Operating-Range IA-32 Processor 4:15 PMin 32nm CMOS
5.1 An 8Ω 2.5W 1%-THD 104dB(A)-Dynamic-Range 1:30 PMClass-D Audio Amplifier with an Ultra-Low EMI System and Current Sensing for Speaker Protection
5.8 A 330nA Energy-Harvesting Charger with Battery Management 4:45 PMfor Solar and Thermoelectric Energy Harvesting
6.5 A 160μA Biopotential Acquisition ASIC with Fully 3:15 PMIntegrated IA and Motion-Artifact Suppression
Tuesday, February 21st
7.5 A 4.1pJ/b 16Gb/s Coded Differential Bidirectional 10:45 AMParallel Electrical Link
10.3 A 1.45GHz 52-to-162GFLOPS/W Variable-Precision 9:30 AMFloating-Point Fused Multiply-Add Unit with Certainty Tracking in 32nm CMOS
11.6 A Temperature-to-Digital Converter for a MEMS-Based 10:45 AMProgrammable Oscillator with Better Than ±0.5ppm Frequency Stability
12.1 A 32nm High-k Metal Gate Application Processor 1:30 PMwith GHz Multi-Core CPU
12.5 A 464GOPS 620GOPS/W Heterogeneous Multi-Core 3:45 PMSoC for Image-Recognition Applications
12.7 A True Multistandard, Programmable, Low-Power, 4:45 PMFull HD Video-Codec Engine for Smartphone SoC
Wednesday, February 22nd
19.3 A 40nm CMOS Single-Chip 50Gb/s DP-QPSK/BPSK Transceiver with 9:30 AMElectronic Dispersion Compensation for Coherent Optical Channels
22.9 A 1920×1080 3.65μm-Pixel 2D/3D Image Sensor with 12:00 PMSplit and Binning Pixel Structure in 0.11μm Standard CMOS
26.6 A Meter-Range UWB Transceiver Chipset for 4:15 PMAround-the-Head Audio Streaming
26.8 A 915MHz 120µW-RX/900µW-TX Envelope-Detection 5:00 PMTransceiver with 20dB In-Band Interference Tolerance
Chair: Masaitsu Nakajima, Panasonic, Moriguchi, Japan
Until recently, TV technology (e.g. analog color TV and broadcast by air) was seen to havematured. However, the introduction of digital TV technology, including high-speed IP-basednetworking, has given consumers additional “freedom” to view content, and is presentingnew technological challenges. Users experience this freedom through multiple types of devices and sources of content.
The introduction of 3D imaging displays represents a great advance for TV receiver equipment.However, the gap between current TV capabilities and customer demand remains large andadditional technology is necessary.
The aim of this Evening Session is to discuss future technologies that could close the customer demand gap, from the viewpoints of service, platform and device.
Time Topic
8:00 Television Futures Brendan Traw, Intel, Portland, OR
8:30 3D and Smart TV in the Future David K. Min, LG Electronics, Seoul, Korea
9:00 Glasses-Free 3D Technologies for Future Digital TV SystemsYuzo Hirayama, Toshiba, Kawasaki, Japan
9:30 FTV (Free-Viewpoint Television) as the Ultimate 3D TVMasayuki Tanimoto, Nagoya University, Nagoya, Japan
EVENING SESSIONS Tuesday February 21st, 8:00 PM
37
EP2: Little-Known Features of Well-Known Creatures
Organizer: Un-Ku Moon, Oregon State University, Corvallis, ORCo-Organizer: Shanthi Pavan, Indian Institute of Technology, Madras, India
Moderator: Shanthi Pavan, Indian Institute of Technology, Madras, India
This panel discussion will feature experts from academia and industry, spanning the broadlandscape of solid state circuits - analog, digital, microwave, mixed signal and RF. They willunleash their bag of tricks - things you thought you knew, but probably did not quite appre-ciate, an interesting way of looking at a well known circuit or a system, a less known facet ofa commonly used idea, little known facts now finding increasing application
Panelists:Asad A. Abidi, University of California, Los Angeles, CAA. Paul Brokaw, Integrated Device Technology, Tucson, AZRinaldo Castello, University of Pavia, Pavia, ItalyMark Horowitz, Stanford University, Stanford, CAThomas H. Lee, DARPA, Arlington, VADavid Robertson, Analog Devices, Wilmington, MA
EP3: What is the Next RF Frontier?
Organizer: Gangadhar Burra, Texas Instruments, Dallas, TXCo-Organizer: Hossein Hashimi, University of Southern California,
What are the next BIG ideas in wireless communications? What will you see at ISSCC, fiveyears from now? Will these new ideas be adopted by consumers? A panel of experts willmake their predictions, focusing on applications ranging from low power to high speed, including:
Medical RF/nano-power – after tele-health, what is next? Energy-scavenged ultra-low-power wireless techniques and integrated bio-sensors may become the frontier for thenext generation of wireless technologies.
mm-Wave & TerraHertz – ultra-high-frequency RF circuits beyond mm-Wave frequencies show promise in medical (diagnostic), security and consumer applications.
Connected home – is “Internet of Things” going to be viable – what are the challenges?
Panelists:Jan Rabaey, University of California at Berkeley, Berkeley, CAJerald Yoo, Masdar Institute of Science & Technology, Abu Dhabi, UAEChris Toumazou, Imperial College, London, United KingdomUllrich Pfeiffer, University of Wuppertal, Wuppertal, GermanyAjith Amerasekera, Texas Instruments, Dallas, TXInyup Kang, Samsung Electronics, Gyeonggi-do, South Korea
18.1 Insole Pedometer with Piezoelectric Energy Harvester 8:30 AMand 2V Organic Digital and Analog Circuits
K. Ishida1, T-C. Huang1, K. Honda1, Y. Shinozuka1, H. Fuketa1, T. Yokota1, U. Zschieschang2,H. Klauk2, G. Tortissier1, T. Sekitani1,3, M. Takamiya1, H. Toshiyoshi1, T. Someya1,3, T. Sakurai11University of Tokyo, Tokyo, Japan2Max Planck Institute for Solid State Research, Stuttgart, Germany3JST/ERATO, Tokyo, Japan
18.2 1D and 2D Analog 1.5kHz Air-Stable Organic Capacitive 9:00 AMTouch Sensors on Plastic Foil
H. Marien1, M. Steyaert1, E. Van Veenendael2, P. Heremans1,3
1KU Leuven, Heverlee, Belgium2Polymer Vision, Eindhoven, The Netherlands3imec, Heverlee, Belgium
18.3 Bidirectional Communication in an HF Hybrid 9:30 AMOrganic/Solution-Processed Metal-Oxide RFID Tag
K. Myny1,2, M. Rockelé1,2, A. Chasin1,2, D-V. Pham3, J. Steiger3, S. Botnaras3, D. Weber3,B. Herold4, J. Ficker4, B. Van der Putten5, G. Gelinck5, J. Genoe1,6, W. Dehaene1,2, P. Heremans1,2
18.4 A 6b 10MS/s Current-Steering DAC Manufactured 10:15 AMwith Amorphous Gallium-Indium-Zinc-Oxide TFTs Achieving SFDR > 30dB up to 300kHz
D. Raiteri1, F. Torricelli1, K. Myny2, M. Nag2, B. Van der Putten3, E. Smits3, S. Steudel2, K. Tempelaars3, A. Tripathi3, G. Gelinck3, A. Van Roermund1, E. Cantatore1
1Eindhoven University of Technology, Eindhoven, The Netherlands2imec, Leuven, Belgium3TNO Science and Industry, Eindhoven, The Netherlands
18.5 A Low-Overhead Self-Healing Embedded System for 10:45 AMEnsuring High Yield and Long-Term Sustainability of 60GHz 4Gb/s Radio-on-a-Chip
A. Tang1, F. Hsiao1, D. Murphy1, I-N. Ku1, J. Liu1, S. D’Souza1, N-Y. Wang1, H. Wu1, Y-H. Wang1,M. Tang1, G. Virbila1, M. Pham1, D. Yang1, Q. Gu2, Y-C. Wu1, Y-C. Kuan1, C. Chien3, M-C. Chang1
1University of California, Los Angeles, Los Angeles, CA2University of Florida, Gainsville, FL3CreoNex Systems, Westlake Village, CA
18.6 Power-Efficient Readout Circuit for Miniaturized Electronic Nose 11:15 AMV. Petrescu, J. Pettine, D. Karabacak, M. Vandecasteele, M. Crego Calama, C. Van Hoofimec - Holst Centre, Eindhoven, The Netherlands
18.7 Towards Ultra-Dense Arrays of VHF NEMS with FDSOI-CMOS 11:45 AMActive Pixels for Sensing Applications
G. Arndt, C. Dupré, J. Arcamone, G. Cibrario, O. Rozeau, L. Duraffourg, E. Ollier, E. ColinetCEA-LETI-MINATEC, Grenoble, France
Session Chair: Ken Chang, Xilinx, San Jose, CAAssociate Chair: SeongHwan Cho, KAIST, Daejeon, Korea
19.1 A 28Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver 8:30 AMin 32nm SOI CMOS Technology
J. Bulzacchelli1, T. Beukema1, D. Storaska2, P-H. Hsieh1,3, S. Rylov1, D. Furrer4, D. Gardellini4,A. Prati4, C. Menolfi5, D. Hanson2, J. Hertle4, T. Morf5, V. Sharma4, R. Kelkar6, H. Ainspan1,W. Kelly2, G. Ritter2, J. Garlett2, R. Callan2, T. Toifl5, D. Friedman1
1IBM Research, Yorktown Heights, NY2IBM Systems and Technology Group, Hopewell Junction, NY3National Tsing Hua University, Hsinchu, Taiwan; 4Miromico, Zurich, Switzerland5IBM Research, Zurich, Switzerland6IBM Systems and Technology Group, Essex Junction, VT
19.2 A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB 9:00 AMof Analog Equalization for 100GBASE-LR4 and Optical Transport Lane 4.4 Applications
M. Harwood1, S. Nielsen2, A. Szczepanek1, R. Allred2, S. Batty1, M. Case2, S. Forey1,K. Gopalakrishnan3, L. Kan3, B. Killips1, P. Mishra2, R. Pande3, H. Rategh3, A. Ren3,J. Sanders2, A. Schoy3, R. Ward3, M. Wetterhorn2, N. Yeung2
1Inphi, Northampton, United Kingdom; 2Inphi, Westlake Village, CA3Inphi, Santa Clara, CA
19.3 A 40nm CMOS Single-Chip 50Gb/s DP-QPSK/BPSK 9:30 AMTransceiver with Electronic Dispersion Compensation for Coherent Optical Channels
D. Crivelli1,2, M. Hueda1,2, H. Carrer1,2, J. Zachan3, V. Gutnik3, M. Del Barco1, R. Lopez1,G. Hatcher3, J. Finochietto2, M. Yeo3, A. Chartrand3, N. Swenson3, P. Voois3, O. Agazzi1,3
1ClariPhy, Cordoba, Argentina; 2National University of Cordoba, Cordoba, Argentina3ClariPhy, Irvine, CA
Break 10:00 AM
19.4 A Dual 23Gb/s CMOS Transmitter/Receiver Chipset 10:15 AMfor 40Gb/s RZ-DQPSK and CS-RZ-DQPSK Optical Transmission
D. Cui, B. Raghavan, U. Singh, A. Vasani, Z. Huang, M. Khanpour, A. Nazemi, H. Maarefi,T. Ali, N. Huang, W. Zhang, B. Zhang, A. Momtaz, J. CaoBroadcom, Irvine, CA
19.5 A Versatile Multi-Modality Serial Link 10:45 AMY. Tanaka1, Y. Hino1, Y. Okada1, T. Takeda1, S. Ohashi1, H. Yamagishi1, K. Kawasaki1, A. Hajimiri21Sony, Tokyo, Japan; 2California Institute of Technology, Pasadena, CA
19.6 A 28Gb/s Source-Series Terminated TX in 32nm CMOS SOI 11:15 AMC. Menolfi1, J. Hertle2, T. Toifl1, T. Morf1, D. Gardellini2, M. Braendli1, P. Buchmann1, M. Kossel11IBM, Rueschlikon, Switzerland; 2Miromico, Zurich, Switzerland
19.7 An All-Digital Clock Generator Using a Fractionally 11:30 AMInjection-Locked Oscillator in 65nm CMOS
P. Park1, H. Park2, J. Park2, S. Cho1
1KAIST, Daejeon, Korea; 2Samsung Electronics, Yongin, Korea
Session Chair: Bogdan Staszewski, TU Delft, Delft, The NetherlandsAssociate Chair: Taizo Yamawaki, Renesas Mobile, Takasaki, Japan
20.1 A 20Mb/s Phase Modulator Based on a 3.6GHz Digital 8:30 AMPLL with -36dB EVM at 5mW Power
G. Marzin, S. Levantino, C. Samori, A. LacaitaPolitecnico di Milano, Milan, Italy
20.2 A 14.2mW 2.55-to-3GHz Cascaded PLL with Reference 9:00 AMInjection, 800MHz Delta-Sigma Modulator and 255fsrmsIntegrated Jitter in 0.13µm CMOS
D. Park, S. ChoKAIST, Daejeon, Korea
20.3 A 40nm CMOS All-Digital Fractional-N Synthesizer without 9:30 AMRequiring Calibration
F. Opteynde, F. OpteyndeAudax-Technologies, Leuven, Belgium
Break 10:00 AM
20.4 A 36mW/9mW Power-Scalable DCO in 55nm CMOS for 10:15 AMGSM/WCDMA Frequency Synthesizers
A. Liscidini1, L. Fanori1, P. Andreani2, R. Castello1
1University of Pavia, Pavia, Italy2Lund University, Lund, Sweden
20.5 A Clip-and-Restore Technique for Phase Desensitization 10:45 AMin a 1.2V 65nm CMOS Oscillator for Cellular Mobile and Base Stations
A. Visweswaran, R. Staszewski, J. LongDelft University of Technology, Delft, The Netherlands
20.6 A 32nm CMOS All-Digital Reconfigurable Fractional 11:15 AMFrequency Divider for LO Generation in Multistandard SoC Radios with On-the-Fly Interference Management
K. Chandrashekar, S. Pellerano, P. Madoglio, A. Ravi, Y. PalaskasIntel, Hillsboro, OR
Session Chair: David Stoppa, Fondazione Bruno Kessler, Trento, ItalyAssociate Chair: Robert Johansson, Aptina Imaging, Oslo, Norway
22.1 An 83dB-Dynamic-Range Single-Exposure Global-Shutter 8:30 AMCMOS Image Sensor with In-Pixel Dual Storage
M. Sakakibara1, Y. Oike1, T. Takatsuka1, A. Kato1, K. Honda1, T. Taura1, T. Machida1, J. Okuno2, A. Ando2, T. Fukuro2, T. Asatsuma1, S. Endo2, J. Yamamoto2, Y. Nakano2, T. Kaneshige2, I. Yamamura1, T. Ezaki1, T. Hirayama1
1Sony, Atsugi, Japan; 2Sony Semiconductor, Kumamoto, Japan
22.2 A Global-Shutter CMOS Image Sensor with Readout 9:00 AMSpeed of 1Tpixel/s Burst and 780Mpixel/s Continuous
Y. Tochigi1, K. Hanzawa1, Y. Kato1, R. Kuroda1, H. Mutoh2, R. Hirose3, H. Tominaga3,K. Takubo3, Y. Kondo3, S. Sugawa1
22.3 A 0.7e-rms-Temporal-Readout-Noise CMOS Image Sensor 9:30 AM
for Low-Light-Level ImagingY. Chen1, Y. Xu1, Y. Chae1, A. Mierop2, X. Wang3, A. Theuwissen1,4
1Delft University of Technology, Delft, The Netherlands2Teledyne DALSA Semiconductors, Eindhoven, The Netherlands3CMOSIS NV, Antwerp, Belgium; 4Harvest Imaging, Bree, Belgium
Break 10:00 AM
22.4 A 256×256 CMOS Image Sensor with ΔΣ-Based 10:15 AMSingle-Shot Compressed Sensing
Y. Oike1,2, A. El Gamal1; 1Stanford University, Stanford, CA; 2Sony, Atsugi, Japan
22.5 A 33Mpixel 120fps CMOS Image Sensor Using 12b 10:45 AMColumn-Parallel Pipelined Cyclic ADCs
T. Watabe1, K. Kitamura1, T. Sawamoto2, T. Kosugi3, T. Akahori3, T. Iida3, K. Isobe3, T. Watan-abe3, H. Shimamoto1, H. Ohtake1, S. Aoyama3, S. Kawahito2,3, N. Egami11NHK Science & Technology Research Laboratories, Tokyo, Japan2Shizuoka University, Hamamatsu, Japan; 3Brookman Technology, Hamamatsu, Japan
22.6 A 14b Extended Counting ADC Implemented in a 24MPixel 11:00 AMAPS-C CMOS Image Sensor
J-H. Kim, W-K. Jung, S-H. Lim, Y-J. Park, W-H. Choi, Y-J. Kim, C-E. Kang, J-H. Shin, K-J. Choo, W-B. Lee, J-K. Heo, B-J. Kim, S-J. Kim, M-H. Kwon, K-S. Yoo, J-H. Seo, S-H. Ham, C-Y. Choi, G-S.HanSamsung Electronics, Yongin, Korea
22.7 A 1.5Mpixel RGBZ CMOS Image Sensor for Simultaneous 11:15 AMColor and Range Image Capture
W. Kim1, W. Yibing2, I. Ovsiannikov2, S. Lee1, Y. Park1, C. Chung1, E. Fossum1,2
1Samsung Electronics, Hwasung, Korea; 2Samsung Semiconductor, Pasadena, CA
22.8 A QVGA-Range Image Sensor Based on Buried-Channel 11:45 AMDemodulator Pixels in 0.18μm CMOS with Extended Dynamic Range
L. Pancheri, N. Massari, M. Perenzoni, M. Malfatti, D. StoppaFondazione Bruno Kessler, Trento, Italy
22.9 A 1920×1080 3.65μm-Pixel 2D/3D Image Sensor with 12:00 PMSplit and Binning Pixel Structure in 0.11μm Standard CMOS
S-J. Kim, B. Kang, J. Kim, K. Lee, C-Y. Kim, Kinam KimSamsung Advanced Institute of Technology, Yongin, Korea
23.1 A 2.5D Integrated Voltage Regulator Using 1:30 PMCoupled-Magnetic-Core Inductors on Silicon Interposer Delivering 10.8A/mm2
N. Sturcken1, E. O’Sullivan2, N. Wang2, P. Herget3, B. Webb2, L. Romankiw2, M. Petracca1,R. Davies1, R. Fontana3, G. Decad3, I. Kymissis1, A. Peterchev4, L. Carloni1, W. Gallagher2,K. Shepard1
1Columbia University, New York, NY 2IBM T. J. Watson, Yorktown Heights, NY3IBM Almaden Research Center, San Jose, CA 4Duke University, Durham, NC
23.2 A Modular 1mm3 Die-Stacked Sensing Platform 2:00 PMwith Optical Communication and Multi-Modal Energy Harvesting
Y. Lee, G. Kim, S. Bang, Y. Kim, I. Lee, P. Dutta, D. Sylvester, D. BlaauwUniversity of Michigan, Ann Arbor, MI
23.3 A DC-Isolated Gate Drive IC with Drive-by-Microwave 2:30 PMTechnology for Power Switching Devices
S. Nagai, N. Negoro, T. Fukuda, N. Otsuka, H. Sakai, T. Ueda, T. Tanaka, D. UedaPanasonic, Seika, Japan
23.4 Nonvolatile 3D-FPGA with Monolithically Stacked 2:45 PMRRAM-Based Configuration Memory
Y. Yang Liauw, Z. Zhang, W. Kim, A. El Gamal, S. WongStanford University, Stanford, CA
24.1 A Sub-2W 10GBASE-T Analog Front-End in 40nm CMOS process 3:15 PMT. Gupta1, F. Yang1, D. Wang1, A. Tabatabaei1, R. Singh1, H. Aslanzadeh1, A. Khalili1, S. Vats1, S. Arno1, S. Campeau2
1Applied Micro, Sunnyvale, CA2Applied Micro, Kanata, ON, Canada
24.2 A 16-Port FCC-Compliant 10GBASE-T Transmitter and Hybrid 3:45 PMwith 76dBc SFDR up to 400MHz Scalable to 48 Ports
F. Gerfers, R. Farjad, M. Brown, A. Tavakoli, D. Nguyen, H-T. Ng, R. ShiraniAquantia, Milpitas, CA
24.3 A 10Gb/s Burst-Mode Laser Diode Driver 4:00 PMfor Burst-by-Burst Power Saving
H. Koizumi, M. Togashi, M. Nogawa, Y. OhtomoNTT, Atsugi, Japan
24.4 A 10Gb/s Burst-Mode TIA with On-Chip Reset/Lock CM 4:15 PMSignaling Detection and Limiting Amplifier with a 75ns Settling Time
X. Yin1, J. Put1, J. Verbrugghe1, J. Gillis1, X-Z. Qiu1, J. Bauwelinck1, J. Vandewege1,H-G. Krimmel2, M. Achouche3
N. Shibata1, K. Kanda1, T. Hisada1, K. Isobe1, M. Sato1, Y. Shimizu1, T. Shimizu1, T. Sugimoto1, T. Kobayashi1, K. Inuzuka1, N. Kanagawa1, Y. Kajitani1, T. Ogawa1, J. Nakai1, K. Iwasa1, M. Kojima1, T. Suzuki1, Y. Suzuki1, S. Sakai1, T. Fujimura1, Y. Utsunomiya1, T. Hashimoto1, M. Miakashi1, N. Kobayashi1, M. Inagaki1, Y. Matsumoto1,S. Inoue1, Y. Suzuki1, D. He1, Y. Honda1, J. Musha1, M. Nakagawa1, M. Honma1, N. Abiko1, M. Koyanagi1, M. Yoshihara1, K. Ino1, M. Noguchi1, T. Kamei2, Y. Kato2, S. Zaitsu2, H. Nasu2, T. Ariki2, H. Chibvongodze2, M. Watanabe2, H. Ding2, N. Ookuma2, R. Yamashita2, G. Liang2, G. Hemink2, F. Moogat2, C. Trinh2, M. Higashitani2, T. Pham2, K. Kanazawa1
1Toshiba, Yokohama, Japan; 2Sandisk, Milpitas, CA
25.2 Over-10×-Extended-Lifetime 76%-Reduced-Error Solid-State 2:00 PMDrives (SSDs) with Error-Prediction LDPC Architecture and Error-Recovery Scheme
S. Tanakamaru, Y. Yanagihara, K. Takeuchi; University of Tokyo, Tokyo, Japan
Y. Lee, H. Yoo, I. Yoo, I-C. Park; KAIST, Daejeon, Korea
25.4 Bitline-Capacitance-Cancelation Sensing Scheme with 2:45 PM11ns Read Latency and Maximum Read Throughput of 2.9GB/s in 65nm Embedded Flash for Automotive
M. Jefremow1,2, T. Kern1, U. Backhausen1, C. Peters1, C. Parzinger1, C. Roll1, S. Kassenetter1, S. Thierold1, D. Schmitt-Landsiedel21Infineon, Neubiberg, Germany; 2Technical University Munich, Munich, Germany
D. Lee, I. Chang, S-Y. Yoon, J. Jang, D-S. Jang, W-G. Hahn, J-Y. Park, D-G. Kim, C. Yoon, B-S. Lim, B-J. Min, S-W. Yun, J-S. Lee, I-H. Park, K-R. Kim, J-Y. Yun, Y. Kim, Y-S. Cho, K-M. Kang, S-H. Joo, J-Y. Chun, J-N. Im, S. Kwon, S. Ham, A. Park, J-D. Yu, N-H. Lee, T-S. Lee, M. Kim, H. Kim, K-W. Song, B-G. Jeon, K. Choi, J-M. Han, K. Kyung, Y-H. Lim, Y-H. JunSamsung Electronics, Hwasung, Korea
A. Kawahara1, R. Azuma1, Y. Ikeda1, K. Kawai1, Y. Katoh1, K. Tanabe2, T. Nakamura2,Y. Sumimoto2, N. Yamada2, N. Nakai2, S. Sakamoto2, Y. Hayakawa1, K. Tsuji1, S. Yoneda1, A. Himeno1, K-I. Origasa2, K. Shimakawa1, T. Takagi1, T. Mikawa1, K. Aono1
1Panasonic, Moriguchi, Japan; 2Panasonic, Nagaokakyo, Japan
25.7 A 0.5V 4Mb Logic-Process Compatible Embedded 4:15 PMResistive RAM (ReRAM) in 65nm CMOS Using Low-Voltage Current-Mode Sensing Scheme with 45ns Random Read Time
25.8 128Gb 3b/Cell NAND Flash Memory in 19nm Technology 4:45 PMwith 18MB/s Write Rate and 400Mb/s Toggle Mode
Y. Li1, S. Lee1, K. Oowada1, H. Nguyen1, Q. Nguyen1, N. Mokhlesi1, C. Hsu1, J. Li1, V. Ramachandra1, T. Kamei1, M. Higashitani1, T. Pham1, M. Honma2, Y. Watanabe2, K. Ino2, B. Le1, B. Woo1, K. Htoo1, T-Y. Tseng1, L. Pham1, F. Tsai1, K-H. Kim1, Y-C. Chen1, M. She1, J. Yuh1, A. Chu1, C. Chen1, R. Puri1, H-S. Lin1, Y-F. Chen1, W. Mak1, J. Huynh1, J. Chan1, M. Watanabe1, D. Yang1, G. Shah1, P. Souriraj1, D. Tadepalli1, S. Tenugu1, R. Gao1, V. Popuri1, B. Azarbayjani1, R. Madpur1, J. Lan1, E. Yero1, F. Pan1, P. Hong1, J. Kang1, F. Moogat1, Y. Fong1, R. Cernea1, S. Huynh1, C. Trinh1, M. Mofidi1, R. Shrivastava1, K. Quader1
Session Chair: Ranjit Gharpurey, University of Texas at Austin, Austin, TXAssociate Chair: Woogeun Rhee, Tsinghua University, Beijing, China
26.1 A 1V 357Mb/s-Throughput TransferJetTM SoC with Embedded 1:30 PMTransceiver and Digital Baseband in 90nm CMOS
M. Tamura1, F. Kondo1, K. Watanabe1, Y. Aoki1, Y. Shinohe1, K. Uchino1, Y. Hashimoto1,F. Nishiyama1, H. Miyachi1, I. Nagase2, I. Uezono2, R. Hisamura2, I. Maekawa1
1Sony, Tokyo, Japan2Sony Semiconductor, Kagoshima, Japan
G. Papotto1, F. Carrara2, A. Finocchiaro2, G. Palmisano1
1University of Catania, Catania, Italy2STMicroelectronics, Catania, Italy
26.8 A 915MHz 120µW-RX/900µW-TX Envelope-Detection 5:00 PMTransceiver with 20dB In-Band Interference Tolerance
X. Huang1, A. Ba1,2, P. Harpe1,3, G. Dolmans1, H. De Groot1, J. Long2
1imec - Holst Centre, Eindhoven, The Netherlands2Delft University of Technology, Delft, The Netherlands3Eindhoven University of Technology, Eindhoven, The Netherlands
28.3 Conditional Push-Pull Pulsed Latches with 726fJ·ps 2:30 PMEnergy-Delay Product in 65nm CMOS
E. Consoli1, M. Alioto2,3, G. Palumbo1, J. Rabaey4
1University of Catania, Catania, Italy2University of Siena, Siena, Italy3University of Michigan, Ann Arbor, MI4University of California at Berkeley, Berkeley, CA
28.4 A 200mV 32b Subthreshold Processor with Adaptive 2:45 PMSupply Voltage Control
S. Luetkemeier1, T. Jungeblut2, M. Porrmann1, U. Rueckert2
1University of Paderborn, Paderborn, Germany2Bielefeld University, Bielefeld, Germany
Break 3:00 PM
28.5 13% Power Reduction in 16b Integer Unit in 40nm CMOS 3:15 PMby Adaptive Power Supply Voltage Control with Parity-Based Error Prediction and Detection (PEPD) and Fully Integrated Digital LDO
K. Hirairi1, O. Yasuyuki1, H. Fuketa2, T. Yasufuku2, M. Takamiya2, M. Nomura1, H. Shinohara1, T. Sakurai21Semiconductor Technology Academic Research Center, Tokyo, Japan2University of Tokyo, Tokyo, Japan
28.6 Bubble Razor: An Architecture-Independent Approach to 3:45 PMTiming-Error Detection and Correction
M. Fojtik1, D. Fick1, Y. Kim1, N. Pinckney1, D. Harris2, D. Blaauw1, D. Sylvester1
1University of Michigan, Ann Arbor, MI2Harvey Mudd College, Claremont, CA
28.7 A 25MHz 7μW/MHz Ultra-Low-Voltage Microcontroller SoC 4:15 PMin 65nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes
D. Bol1, J. De Vos1, C. Hocquet1, F. Botman1, F. Durvaux1, S. Boyd2, D. Flandre1, J-D. Legat1
1Université catholique de Louvain, Louvain-la-Neuve, Belgium2P.E. International, Berkeley, CA
28.8 A 530mV 10-Lane SIMD Processor with Variation 4:45 PMResiliency in 45nm SOI
R. Pawlowski1, E. Krimer2, J. Crop1, J. Postman1, N. Moezzi-Madani3, M. Erez2, P. Chiang1
1Oregon State University, Corvallis, OR2University of Texas, Austin, TX3Qualcomm, San Diego, CA
Instructors: Christian Enz, CSEM, Neuchatel, SwitzerlandWilly Sansen, K.U. Leuven, Leuven, BelgiumBoris Murmann, Stanford University, Stanford, CAPhilip Mok, Hong Kong University of Science and Technology,
Hong Kong
OverviewThe reduction of the power consumption of all electronic functions is a continuous endeavor.This endeavor requires judicious comparison of analog and digital realizations from the pointof view of performance per unit of power consumed. Analog signal processing offers the advantage that power consumption can be minimized at both very low and very high frequencies. This short course explores the limits in reduction of power consumption for important analog blocks.The first presentation defines the physical limits of supply voltages and power consumptionbased on present-day technologies and transistor models. The second presentation addressesthe limits of amplifiers and filters. For all circuit blocks, figures of merit are derived, followedby circuit techniques to improve them.In the third presentation, new opportunities are identified to reduce the power consumptionin all types of analog-to-digital converters, with emphasis on the improvement of the FOMwith technology. Finally, in the fourth presentation, power minimization techniques are discussed for power management blocks such as dc-dc converters.
The Short Course8 am-9.30 am: Christian Enz: Ultra-low Power/Ultra-low Voltage
Analog Circuit Design9.30 am-10 am: Break10 am-11.30 am: Willy Sansen: Power Limits for Amplifiers and Filters11.30 am-12.30 am: Lunch12.30 am-2 pm: Boris Murmann: Energy Limits in Current A/D
Converter Architectures 2 pm-2.30 pm: Break2.30 pm-4 pm: Philip Mok: Low-Power and Low-Voltage DC-DC
Converter Design
OUTLINE:
Ultra-Low-Power/Ultra-Low-Voltage Analog Circuit Design
The supply voltage of CMOS chips has been scaled down in recent years, today reaching thesub-1V region. Analog circuits unfortunately do not take advantage of this voltage scaling. Infact, almost all analog performance metrics are degraded at lower voltages. We first recallthe fundamental limits of the design of low-power analog circuits. We then look at the mainchallenges when designing analog circuits for ultra-low-voltage (ULV) operation. We take acloser look at the MOS transistor operation with a particular focus on weak inversion. Wethen review several basic building blocks capable of operating at ULV.
Instructor: Christian Enz is VP heading the Integrated and Wireless Systems Division of theSwiss Center for Electronics and Microtechnology (CSEM) in Neuchâtel, Switzerland. He isalso Professor at the Swiss Federal Institute of Technology, Lausanne (EPFL), where he islecturing and supervising students in the field of analog and RF IC design. He received thePhD from the EPFL in 1989. His technical interests and expertise are in the field of ultralow-power analog and RF IC design, wireless sensor networks and semiconductor device modeling. Together with E. Vittoz and F. Krummenacher, he is the developer of the EKV MOStransistor model.
SHORT COURSE Thursday February 23rd, 8:00 AM
50
Power Limits for Amplifiers and Filters
Increasing power consumption in amplifiers increases the speed and also reduces noise anddistortion. The most common operational amplifiers, gm blocks and wideband amplifiers arecompared using a power-based FOM. Also discussed are continuous-time filters, switched-capacitor filters and GmC filters. They are classified and compared based on a unified FOM.Again power is optimized in view of speed, noise and distortion.
Instructor: Willy Sansen received a PhD degree from U.C. Berkeley in 1972. Since 1980 hehas been full professor at the Catholic University of Leuven, in Belgium, where he has headedthe ESAT-MICAS laboratory on analog design up till 2008. He has been supervisor of sixty-four PhD theses and has authored and coauthored more than 650 publications and fifteenbooks among which the Powerpoint slide based book “Analog Design Essentials” (Springer2006). He was Program chair of the ISSCC-2002 conference and President of the IEEE Solid-State Circuits Society in 2008-2009. He is the recipient of the D.O.Pederson award of the IEEESolid-State Circuits in 2011. He is a Life Fellow of the IEEE.
Energy Limits in Current A/D Converter Architectures
Driven by ever-increasing application demands, the energy expended per A/D conversion hasbeen reduced substantially over the last decade. This presentation surveys the most recenttrends and investigates energy limits as they apply to A/D converter architectures commonlyemployed in fine-line CMOS technology (Flash, Pipeline, SAR and Oversampling Converters).Through this analysis, opportunities for further improvements are identified and discussedin detail, specifically emphasizing the impact of technology scaling.
Instructor: Boris Murmann is an Associate Professor in the Department of Electrical Engineering, Stanford, CA. He received the Ph.D. degree in electrical engineering from theUniversity of California at Berkeley in 2003. Dr. Murmann’s research interests are in the areaof mixed-signal integrated circuit design, with special emphasis on data converters and sensorinterfaces. He is a member of the International Solid-State-Circuits Conference (ISSCC) program committee, an associate editor of the IEEE Journal of Solid-State Circuits and a Distinguished Lecturer of the IEEE Solid-State Circuits Society.
Low-Power and Low-Voltage DC-DC Converter Design
With the recent advanced development of the VLSI system, power management circuits willbe operated with lower output power requirement and with lower supply voltage. Severalstrategies to improve the power efficiency of low-power DC-DC converter are described andtheir pros and cons are discussed. Different design techniques for low-voltage dc-dc converterdesign are also included.
Instructor: Philip Mok is a Professor at the Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology in Hong Kong. He receivedhis PhD in Electrical and Computer Engineering from the University of Toronto, Toronto,Canada, in 1995. His current research interests include power management integrated circuitsand low-voltage analog integrated circuits design.
SHORT COURSE Thursday February 23rd, 8:00 AM
51
F3: 10-40 Gb/s I/O Design for Data Communications
Organizer: Ken Chang, Xilinx, San Jose, CACo-Organizer: Tony Chan Carusone, University of Toronto, Toronto, Canada
Chair: Ali Sheikholeslami, University of Toronto, Toronto, Canada
Committee: Bob Payne, Texas Instruments, Dallas, TXMiki Moyal, Intel, Haifa, IsraelJohn Stonick, Synopsys, Hillsboro, ORHisakatsu Yamaguchi, Fujitsu, Kawasaki Japan
The importance of I/O data rates beyond 10Gb/s is growing rapidly. Supporting these datarates introduces new challenges beyond those faced at lower data rates. The objective of thisForum is to present both electrical and optical I/O approaches to meeting these challenges atthe architecture and circuit levels. The Forum commences with two talks offering an overviewof circuits and systems issues in CMOS technology. They are followed by two presentationsfocusing on the challenges of 20Gb/s+ over electrical backplanes and very lossy electricalchannels. The next talk compares conventional analog equalization versus digital (data-con-verter-based) approaches from a system perspective. The final two talks focus on opticalsolutions, highlighting the relative strengths and weaknesses of electrical and optical ap-proaches. The Forum concludes with a panel discussion providing an opportunity for parti-cipants to give feedback and ask questions. The Forum is aimed at circuit designers andengineers working on high-speed wireline transceivers.
Forum AgendaTime Topic
8:00 Breakfast8:20 Introduction: Ali Sheikholeslami, University of Toronto, Toronto, Canada
08:30 10-to-40Gb/s I/O Circuits and System Design: Techniques to Improve Power Efficiency
James Jaussi, Intel, Hillsboro, OR
09:20 Design of 40Gb/s Broadband Transceivers in CMOS TechnologyJri Lee, National Taiwan Univeristy, Taipei, Taiwan
10:10 Break
10:35 (What is so Hard About) SerDes Design Challenges for 20Gb/s+ Data Rates over Electrical Backplanes?
Andy Joy, Texas Instruments, Northampton, United Kingdom
11:25 10-20Gb/s+ Equalizer Design for Electrical Channel with 40dB+ LossYasuo Hidaka, Fujitsu Laboratories of America, Sunnyvale, CA
12:15 Lunch
1:20 Equalization for High-Speed SerDes Systems – a System-Level Comparison of Analog and Digital Techniques
Vivek Telang, Broadcom, Austin, TX
2:10 Optical vs. Electrical I/O: Reach, Bandwidth, Power Efficiency, Density and Cost
Alexander Rylyakov, IBM T.J. Watson Research Center, Yorktown Heights, NY
3:00 Break
3:20 A System-Level Look at Silicon PhotonicsRon Ho, Oracle, Redwood Shores, CA
4:10 Panel Discussion
5:00 Closing Remarks (Chair)
FORUM
52
F4: Computational Imaging
Organizers: Makoto Ikeda, University of Tokyo, Tokyo, JapanAlbert Theuwissen, Harvest Imaging, Bree, Belgium,
Delft University of Technology, Delft, The NetherlandsJohannes Solhusvik, Aptina Imaging, Oslo, Norway
Committee: Jan Bosiers, Teledyne DALSA, Eindhoven, The Netherlands
Computational imaging is becoming widely adopted in consumer products to reconstructhigh-quality pictures from raw pixel data provided by special optics and image sensors. Thisforum provides details of such systems. We commence with an overview of computationalphotograpy and imaging. This is followed by object recognition and tracking techniques in-cluding interesting point techniques and face-detection algorithms optimized for cameras.Camera array techniques, multiple shot techniques and coded aperture techniques for im-proved resolution and extended depth-of-field are presented. The popular compressed sensingtechnique is also covered with the aim to reduce data rate without severely impacting imagequality. Last, existing implementations on parallel-processing architectures are introduced.
Forum AgendaTime Topic
08:00 Breakfast
08:30 IntroductionMakoto Ikeda, University of Tokyo, Tokyo, Japan
08:35 Overview of Computational Photography and ImagingShinsaku Hiura, Hiroshima City University, Hiroshima, Japan
09:20 Interest Point and Local Descriptor Generation in SiliconGraham Kirsch, Aptina UK, Berkshire, United Kingdom
10:05 Break
10:30 Face Detection in Embedded SystemsPetronel Bigioi, DigitalOptics, San Jose, CA
11:15 Light Field Imaging with Regular Arrays of Inexpensive Cameras (RayCam)Kartik Venkataraman, Pelican Imaging, Mountain View, CA
12:00 Lunch
1:00 Super-Resolution by Multiple Shots: From Myths to MethodsLucas van Vliet, Delft University of Technology,
Delft, The Netherlands
1:45 Image and Depth from a Conventional Camera with a Coded ApertureBill Freeman, Massachusetts Institute of Technology,
Cambridge, MA
2:30 Break
2:50 Is Compressed Sensing Relevant to Image Sensors?Abbas El Gamal, Stanford University, Stanford, CA
3:35 Processing Device Prospectives for Computational Imaging ApplicationsYuki Kobayashi, Renesas Electronics, Kanagawa, Japan
4:20 Closing Remarks (Chair)
Thursday February 23rd, 8:00 AM
53
F5: Bioelectronics for Sustainable Healthcare
Organizers: Chris Van Hoof, imec, Leuven, BelgiumWim Dehaene, Katholieke Universiteit Leuven, Leuven, BelgiumWentai Liu, UC Santa Cruz, Santa Cruz, CA
Committee:Wim Dehaene, Katholieke Universiteit Leuven, Leuven, BelgiumTimothy Denison, Medtronic, Minneapolis, MNMinkyu Je, A*STAR, Singapore, SingaporeWentai Liu, UC Santa Cruz, Santa Cruz, CAChris Van Hoof, imec, Leuven, BelgiumHoi-Jun Yoo, KAIST, Daejeon, Korea
The forum gives a broad view on the role of Bioelectronics in the world of tomorrow. It startsfrom a holistic view on the importance of sustainable and affordable health care from a societaland economical perspective. Next the forum addresses key application challenges that needto be met to achieve those goals. The circuit and system requirements for these applicationsis derived. In the third part of the forum, the realization of the circuit building blocks (andtheir remaining challenges) is discussed. Circuit and component innovation is shown to becrucial for achieving advanced technological tools that will underpin sustainable health care.
Forum AgendaTime Topic
8:00 Breakfast
8:30 IntroductionChris Van Hoof, imec, Leuven, Belgium
8:40 Societal and Economical Healthcare ChallengesBill Heetderks, NIH-BIBIB, Bethesda, MD
9:40 Electronic System Challenges for HealthcareGene Frantz, Texas Instruments, Dallas, TX
10:40 Break
10:55 Retinal Prosthesis and Hybrid Neural InterfacesJames D Weiland, USC, Los Angeles, CA
11:40 Chip-Level Electronic Noses for a Sustainable SocietySywert Brongersma, Holst Centre, Eindhoven, The Netherlands
12:25 Lunch
1:15 Low-Cost MR-compatible NeuroprostheticsSung June Kim, Seoul National University, Seoul, Korea
2:00 THz Bio-Imaging SystemsFrank Chang, UCLA, Los Angeles, CA
2:45 Low Noise Design and Integration Challenges for Neurophysiology Probes Zhi Yang, Singapore National University, Singapore, Singapore
3:30 Low-Power Wireless and Implantable Sensor InterfacesGeorges Gielen, University of Leuven, Leuven, Belgium
4:15 Break
4:30 Conclusion
FORUM
54
F6: Power/Performance Optimization of Many-Core Processor SoCs
Organizers: Stephen Kosonocky, Advanced Micro Devices, Fort Collins, COVladimir Stojanovic, MIT, Cambridge, MA
As performance scaling per-core continues to slow-down, designers are faced with a myriadof challenges in efficiently using the transistors offered by modern processes. This Forumwill address next generation computing challenges in the context of highly parallel manycoreprocessors. The key design challenge in the many-core era is management and efficient useof resources across the layers of design hierarchy. In this context, the Forum will focus onkey challenges that lie ahead:
• Architecture balancing: homogeneous vs. heterogeneous processors• Embedded multicore challenges in mobile platforms• Power management and optimization • On-chip network and memory system design for ease of programming
and balancing of compute/communication power• Design tool challenges for many-core SOCs
Forum Agenda
Time Topic
08:00 Breakfast
08:30 IntroductionStephen Kosonocky, AMD, Fort Collin, CO
08:45 Integration Choices for Heterogeneous SoCsJim Kahle, IBM, Austin, TX
09:30 Embedded Multicore in Mobile PlatformsAlain Artieri, ST-Ericsson, Grenoble, France
10:15 Break
10:30 Heterogeneous Many-Core Processors and the Fusion System ArchitectureMichael Schulte, AMD, Austin, TX
11:15 Power Optimization Through Many-Core MultiprocessingJohn Goodacre, ARM, Cambridge, United Kingdom
12:00 Lunch
11:00 High-Performance Energy-Efficient NoC FabricsMark A. Anders, Intel, Hillsboro, OR
11:45 System-Level Power Management Methodology for Real-Time Applications: From Application to Silicon
Se-Joong Lee, Texas Instruments, Dallas, TX
2:30 Randomized Modeling of Performance and Power in Heterogeneous Multi-Core SOC
Michael Frank, MediaTek, San Jose, CA
3:15 The Layout Evaluation and Hierarchical Layout Method of MPSoCYuichi Nakamura, NEC, Kawasaki, Japan
4:00 Break
4:15 Panel Discussion – Moderator: Vladimir Stojanovic, MIT, Cambridge, MA
5:00 Conclusion
Thursday February 23rd, 8:00 AM
55
EXECUTIVE COMMITTEE
CONFERENCE CHAIR Anantha Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA
SECRETARY, FORUM CHAIR AND DATA TEAM CO-CHAIRTrudy Stetzler, Texas Instruments, Stafford, TX
DIRECTOR OF FINANCE AND BOOK DISPLAY COORDINATORBryant Griffin, Penfield, NY
PROGRAM CHAIRHideto Hidaka, Renesas Electronics, Itami, Japan
PROGRAM VICE CHAIRBram Nauta, University of Twente, Enschede, The Netherlands
STUDENT FORUM CHAIR AND UNIVERSITY RECEPTIONS Jan van der Spiegel, University of Pennsylvania, Philadelphia, PA
WEB MANAGER AND DATA TEAM CO-CHAIR Bill Bowhill, Intel, Hudson, MA
ITPC FAR EAST REGIONAL CHAIRHoi-Jun Yoo, KAIST, Daejeon, Korea
ITPC FAR EAST REGIONAL VICE CHAIR AND STUDENT FORUM VICE-CHAIRMakoto Ikeda, University of Tokyo, Tokyo, Japan
ITPC FAR EAST REGIONAL SECRETARYKazutami Arimoto, Renesas Electronics, Itami, Japan
ITPC EUROPEAN REGIONAL CHAIRAarno Pärssinen, Renaesas Mobile, Helsinki, Finland
ITPC EUROPEAN REGIONAL VICE CHAIREugenio Cantatore, Eindhoven University of Technology,
Eindhoven, The Netherlands
ITPC EUROPEAN REGIONAL SECRETARYAlison Burdett, Toumaz Technology, Abingdon, United Kingdom
EDUCATIONAL EVENTS LIAISON Ali Sheikholeslami, University of Toronto, Toronto, Canada
ADCOM REPRESENTATIVE Bryan Ackland, Stevens Institute of Technology, Old Bridge, NJ
DIRECTOR OF PUBLICATIONS AND PRESENTATIONSLaura Fujino, University of Toronto, Toronto, Canada
DIRECTOR OF AUDIOVISUAL SERVICESJohn Trnka, Rochester, MN
PRESS LIAISON AND AWARDS & RECOGNITION COMMITTEE (ARC) CHAIRKenneth C. Smith, University of Toronto, Toronto, Canada
DIRECTOR OF OPERATIONSMelissa Widerkehr, Widerkehr and Associates, Montgomery Village, MD
TECHNICAL EDITORSJason H. Anderson, University of Toronto, Toronto, CanadaVincent Gaudet, University of Waterloo, Waterloo, CanadaGlenn Gulak (Editor-at-Large), University of Toronto, Toronto, CanadaJames W. Haslett, University of Calgary, Calgary, CanadaShahriar Mirabbasi, University of British Columbia, Vancouver, CanadaKostas Pagiamtzis, Gennum, Burlington, CanadaKenneth C. Smith (Editor-at-Large), University of Toronto, Toronto, Canada
INTERNATIONAL TECHNICAL PROGRAM COMMITTEEPROGRAM CHAIR:
Hideto Hidaka, Renesas Electronics, Itami, Japan
PROGRAM VICE CHAIR:Bram Nauta, University of Twente, Enschede, The Netherlands
ANALOG SUBCOMMITTEEChair: Bill Redman-White, NXP Semiconductors, Southampton, United Kingdom
Ivan Bietti, ST Microelectronics, Grenoble, FranceTony Chan Carusone, University of Toronto, Toronto, CanadaGyu-Hyeong Cho, KAIST, Daejon, KoreaBaher Haroun, Texas Instruments, Dallas, TXJed Hurwitz, Broadcom, Edinburgh, United KingdomMinkyu Je, Institute of Microelectronics, A*STAR, SingaporeWing Hung Ki, HKUST, Clear Water Bay, Hong Kong,Peter Kinget, Columbia University, New York, NY*Kimmo Koli, ST-Ericsson Oy, Turku, FinlandJae-Youl Lee, Samsung Electronics, Yongin, KoreaTsung-Hsien Lin, National Taiwan University, Taipei, TaiwanChris Mangelsdorf, Analog Devices, Tokyo, JapanJafar Savoj, Xilinx, San Jose, CAMichiel Steyaert, KULeuven, Hevrelee, BelgiumAxel Thomsen, Silicon Laboratories, Austin, TXEd van Tuijl, University of Twente, Enschede, The Netherlands
DATA CONVERTERS SUBCOMMITTEEChair: Venu Gopinathan, Texas Instruments, Bangalore, India
Brian Brandt, Maxim Integrated Products, North Chelmsford, MA*Lucien Breems, NXP Semiconductors, Eindhoven, The NetherlandsKlaas Bult, Broadcom, Bunnik, The NetherlandsMarco Corsi, Texas Instruments, Dallas, TXDieter Draxelmayr, Infineon Techologies, Villach, AustriaMichael Flynn, University of Michigan, Ann Arbor, MIGabriele Manganaro, Analog Devices, Wilmington, MAYiannos Manoli, University of Freiburg, IMTEK, Freiburg, GermanyTakahiro Miki, Renesas Electronics, Itami, JapanGerhard Mitterregger, Intel Mobile Communications Austria, St. Magdalen, AustriaUn-Ku Moon, Oregon State University, Corvallis, ORBoris Murmann, Stanford University, Stanford, CAKatsu Nakamura, Analog Devices, Wilmington, MAShanthi Pavan, Indian Institute Of Technology, Chennai, IndiaMichael Perrott, Masdar Institute of Science and Technology,
Abu Dhabi, United Arab Emirates
ENERGY-EFFICIENT DIGITAL SUBCOMMITTEEChair: Tzi-Dar Chiueh, National Chip Implementation Center, Hsinchu, TaiwanKazutami Arimoto, Renesas Electronics, Hyogo, Japan*Ming-Yang Chao, Mediatek, Hsinchu, TaiwanWim Dehaene, KU Leuven, Leuven, BelgiumVasantha Erraguntla, Intel Technology India, Bangalore, IndiaStephen Kosonocky, Advanced Micro Devices, Fort Collins, COShannon Morton, Nvidia, Bristol, United KingdomByeong-Gyu Nam, Chungnam National University, Daejeon, KoreaMichael Phan, Qualcomm, Raleigh, NCMichael Polley, Texas Instruments, Dallas, TXMasaya Sumita, Panasonic, Moriguchi, JapanKees van Berkel, ST-Ericsson, Eindhoven, The Netherlands
HIGH-PERFORMANCE DIGITAL SUBCOMMITTEEChair: Stefan Rusu, Intel, Santa Clara, CA
IMAGERS, MEMS, MEDICAL AND DISPLAYS SUBCOMMITTEEChair: Roland Thewes, TU Berlin, Berlin, Germany
JungChak Ahn, Samsung Electronics, Yongin, KoreaJan Bosiers, Teledyne DALSA Professional Imaging, Eindhoven, The NetherlandsTimothy Denison, Medtronic, Minneapolis, MNMaysam Ghovanloo, Georgia Institure of Technology, Atlanta, GA*Christoph Hagleitner, IBM Research, Ruschlikon, SwitzerlandMakoto Ikeda, University of Tokyo, Tokyo, JapanRobert Johansson, Aptina Imaging, Oslo, NorwaySam Kavusi, Bosch Research and Technology Center, Palo Alto, CAShoji Kawahito, Shizuoka University, Hamamatsu, JapanWentai Liu, UC Santa Cruz, Santa Cruz, CAKofi Makinwa, Technical University of Delft, Delft, The NetherlandsYoung-Sun Na, LG Electronics, Seoul, KoreaJun Ohta, Nara Institute of Science & Technology, Nara, JapanYusuke Oike, Sony, Kanagawa, JapanMaurits Ortmanns, University of Ulm, Ulm, GermanyAaron Partridge, SiTime, Sunnyvale, CADavid Stoppa, Fondazione Bruno Kessler, Trento, Italy
MEMORY SUBCOMMITTEEChair: Kevin Zhang, Intel, Hillsboro, OR
Colin Bill, Global Foundries, Sunnyvale, CALeland Chang, IBM T. J. Watson Research Center, Yorktown Heights, NYJoo Sun Choi, Samsung, Hwasung, KoreaSungdae Choi, Hynix Semiconductor, Icheon, KoreaMichael Clinton, Texas Instruments, Dallas, TXJin-Man Han , Samsung Electronics, Hwasung, Korea*Satoru Hanzawa, Hitachi Central Research Laboratory, Tokyo, JapanHeinz Hoenigschmid, Elpida Memory, Munich, GermanyNicky C.C. Lu, Etron Technology, Hsinchu, TaiwanCormac O’Connell, TSMC, Ottawa, CanadaYasuhiro Takai, Elpida Memory, Sagamihara, JapanDaisaburo Takashima, Toshiba, Yokohama, JapanKen Takeuchi, University of Tokyo, Tokyo, JapanDaniele Vimercati, Micron Technology, Agrate, ItalyTadaaki Yamauchi, Renesas Electronics, Itami, Japan
RF SUBCOMMITTEEChair: Andreia Cathelin, STMicroelectronics, Crolles Cedex, France
Ehsan Afshari, Cornell University, Ithaca, NYPietro Andreani, Lund University, Lund, SwedenHooman Darabi, Broadcom, Irvine, CABrian Floyd, North Carolina State University, Raleigh, NC*Joseph Golat, Motorola, Algonquin, ILSongcheol Hong, KAIST, Daejeon, KoreaMike Keaveney, Analog Devices, Limerick, IrelandHarald Pretl, Intel Mobile Communications, Linz, AustriaGabriel Rebeiz, University of California, San Diego, La Jolla, CACarlo Samori, Politecnico di Milano, Milano, ItalyBogdan Staszewski, TU Delft, Delft, The NetherlandsPiet Wambacq, imec, Leuven, BelgiumTaizo Yamawaki, Renesas Mobile, Takasaki, JapanMasoud Zargari, Qualcomm-Atheros, Irvine, CAJing-Hong Conan Zhan, MediaTek, HsinChu, TaiwanMichael Zybura, RF Micro Devices, Scotts Valley, CA
TECHNICAL DIRECTIONS SUBCOMMITTEEChair: Siva Narendra, Tyfone, Portland, OR
Pascal Ancey, STMicroelectronics, Crolles, FranceAhmad Bahai, National Semiconductor, Santa Clara, CA*Azeez Bhavnagarwala, GLOBALFOUNDRIES, Hopewell Junction, NYShekhar Borkar, Intel, Hillsboro, ORAlison Burdett, Toumaz Technology, Abingdon, United KingdomEugenio Cantatore, Eindhoven University of Technology, Eindhoven, The NetherlandsEric Colinet, CEA-LETI, Grenoble, FranceFu-Lung Hsueh, TSMC, Hsinchu, TaiwanUming Ko, Texas Instruments, Houston, TXTadahiro Kuroda, Keio University, Yokohama, Kanagawa, JapanMasaitsu Nakajima, Panasonic, Moriguchi, JapanDavid Ruffieux, CSEM, Neuchatel, SwitzerlandSatoshi Shigematsu, NTT Electronics, Yokohama, JapanChris Van Hoof, IMEC, Leuven, BelgiumHoi-Jun Yoo, KAIST, Daejeon, Korea
COMMITTEES
58
*ADS/IDS Committee
WIRELESS SUBCOMMITTEEChair: David Su, Atheros Communications, San Jose, CA
Didier Belot, ST Microelectronics, Crolles, FranceGangadhar Burra, Texas Instruments, Dallas, TXGeorge Chien, MediaTek, San Jose, CAJan Crols, AnSem, Heverlee, BelgiumRanjit Gharpurey, University of Texas at Austin, Austin, TXHossein Hashemi, University of Southern California, Los Angeles, CAMyung-Woon Hwang, FCI, Sungnam, KoreaAlbert Jerng, Ralink, Jhubei, TaiwanEric Klumperink, University of Twente, Enschede, The NetherlandsShouhei Kousai, Toshiba, Kawasaki, JapanDomine Leenaerts, NXP Semiconductors, Eindhoven, The NetherlandsSven Mattisson, Ericsson AB, Lund, Sweden*Kenichi Okada, Tokyo Institute of Technology, Tokyo, JapanYorgos Palaskas , Intel, Hillsboro, ORAarno Parssinen, Renaesas Mobile, Helsinki, FinlandWoogeun Rhee, Tsinghua University, Beijing, ChinaIason Vassiliou, Broadcom, Alimos, Greece
WIRELINE SUBCOMMITTEEChair: Daniel Friedman, IBM Thomas J. Watson Research Center, Yorktown Heights, NY
Ajith Amerasekera, Texas Instruments, Dallas, TXKen Chang, Xilinx, San Jose, CASeongHwan Cho, KAIST, Daejon, KoreaNicola Da Dalt, Infineon, AustriaIchiro Fujimori, Broadcom, Irvine, CAChewnpu Jou, TSMC, Hsinchu, TaiwanJack Kenney, Analog Devices, Somerset, NJMiki Moyal, Intel Israel, Haifa, IsraelMasafumi Nogawa, NTT Microsystem Integration Laboratories, Atsugi, JapanBob Payne, Texas Instruments, Dallas, TXTatsuya Saito, Hitachi, Kokubunji, Tokyo, JapanAli Sheikholeslami, University of Toronto, Toronto, CanadaJae-Yoon Sim, POSTECH, Pohang, KoreaJohn T. Stonick, Synopsys, Hillsboro, OR*Koichi Yamaguchi, Renesas Electronics, Kawasaki, JapanHisakatsu Yamaguchi, Fujitsu Laboratories, Kawasaki, Japan
EUROPEAN REGIONAL COMMITTEEITPC EUROPEAN REGIONAL CHAIR
Aarno Pärssinen, Renaesas Mobile, Helsinki, Finland
ITPC EUROPEAN REGIONAL VICE CHAIREugenio Cantatore, Eindhoven University of Technology,
Eindhoven, The NetherlandsITPC EUROPEAN REGIONAL SECRETARY
Alison Burdett, Toumaz Technology, Abingdon, United KingdomMembers: Pascal Ancey, STMicroelectronics, Crolles, France
Pietro Andreani, Lund University, Lund, SwedenDidier Belot, STMicroelectronics, Crolles, FranceIvan Bietti, STMicroelectronics, Grenoble, FranceJan Bosiers, Teledyne DALSA Professional Imaging, Eindhoven, The NetherlandsLucien Breems, NXP Semiconductors, Eindhoven, The NetherlandsKlaas Bult, Broadcom, Bunnik, The NetherlandsAlison Burdett, Toumaz Technology, Abingdon, United KingdomAndreia Cathelin, STMicroelectronics, Crolles Cedex, FranceEric Colinet, CEA-LETI, Grenoble, FranceJan Crols, AnSem, Heverlee, BelgiumNicola Da Dalt, Infineon, AustriaWim Dehaene, KULeuven, Leuven, BelgiumDieter Draxelmayr, Infineon Techologies, Villach, AustriaChristoph Hagleitner, IBM Research, Ruschlikon, SwitzerlandHeinz Hoenigschmid, Elpida Memory, Munich, GermanyJed Hurwitz, Broadcom, Edinburgh, ScotlandRobert Johansson, Aptina Imaging, Oslo, NorwayMike Keaveney, Analog Devices, Limerick, IrelandEric Klumperink, University of Twente, Enschede, The NetherlandsKimmo Koli, ST-Ericsson Oy, Turku, FinlandDomine Leenaerts, NXP Semiconductors, Eindhoven, The NetherlandsKofi Makinwa, Technical University of Delft, Delft, The NetherlandsGerhard Mitterregger, Intel Mobile Communications Austria, St. Magdalen, AustriaShannon Morton, Nvidia, Bristol, United Kingdom
COMMITTEES
59
*ADS/IDS Committee
European Members (continued):Miki Moyal, Intel Iserael, Haifa, IsraelTobias Noll, RWTH Aachen University, Aachen, GermanyMaurits Ortmanns, University of Ulm, Ulm, GermanyHarald Pretl, Intel Mobile Communications, Linz, AustriaBill Redman-White, NXP Semiconductors, Southampton, United KingdomDavid Ruffieux, CSEM, Neuchatel, SwitzerlandCarlo Samori, Politecnico di Milano, Milano, ItalyBogdan Staszewski, Technical University of Delft, Delft, The NetherlandsDavid Stoppa, Fondazione Bruno Kessler, Trento, ItalyRoland Thewes, TU Berlin, Berlin, GermanyKees van Berkel, ST-Ericsson, Eindhoven, The NetherlandsChris Van Hoof, imec, Leuven, BelgiumEd van Tuijl, University of Twente, Enschede, The NetherlandsIason Vassiliou, Broadcom, Alimos, GreeceDaniele Vimercati, Micron Technology, Agrate, ItalyPiet Wambacq, imec, Leuven, Belgium
FAR EAST REGIONAL COMMITTEEITPC FAR EAST REGIONAL CHAIR
Hoi-Jun Yoo, KAIST, Daejeon, Korea
ITPC FAR EAST REGIONAL VICE CHAIR AND STUDENT FORUM VICE-CHAIRMakoto Ikeda, University of Tokyo, Tokyo, Japan
ITPC FAR EAST REGIONAL SECRETARYKazutami Arimoto, Renesas Electronics, Itami, Japan
Members: JungChak Ahn, Samsung Electronics, Yongin, KoreaMing-Yang Chao, MediaTek, Hsinchu, TaiwanTzi-Dar Chiueh, National Chip Implementation Center, Hsinchu, TaiwanGyu-Hyoeong Cho, KAIST, Daejeon, KoreaSeongHwan Cho, KAIST, Daejon, KoreaJoo Sun Choi, Samsung, Hwasung, KoreaSungdae Choi, Hynix Semiconductor, Icheon, KoreaVasantha Erraguntla, Intel Technology, Bangalore, IndiaSatoru Hanzawa, Hitachi Central Research Laboratory, Tokyo, JapanHiroo Hayashi, Toshiba, Kawasaki, JapanSongcheol Hong, KAIST, Daejeon, KoreaFu-Lung Hsueh, TSMC, Hsinchu, TaiwanMyung-Woon Hwang, FCI, Sungnam, Kyunggi, KoreaAtsuki Inoue, Fujitsu, Kawasaki, JapanMinkyu Je, Institute of Microelectronics, A*STAR, Singapore, SingaporeAlbert Jerng, Ralink, Jhubei, TaiwanChewnpu Jou, TSMC, Hsinchu, TaiwanShoji Kawahito, Shizuoka University, Hamamatsu, JapanWing Hung Ki, HKUST, Hong Kong, ChinaShouhei Kousai, Toshiba, Kawasaki, JapanTadahiro Kuroda, Keio University, Yokohama, Kanagawa, JapanJae-Youl Lee, Samsung Electronics, Yongin, KoreaTsung-Hsien Lin , National Taiwan University, Taipei, TaiwanNicky C.C. Lu, Etron Technology, Hsinchu, TaiwanChris Mangelsdorf, Analog Devices K.K, Tokyo, JapanTakahiro Miki, Renesas Electronics, Itami, JapanYoung-Sun Na, LG Electronics, Seoul, KoreaMasaitsu Nakajima, Panasonic, Osaka, JapanByeong-Gyu Nam, Samsung Electronics, Yongin, KoreaMasafumi Nogawa, NTT Microsystem Integration Laboratories, Atsugi, JapanJun Ohta, Nara Institute of Science & Technology, Nara, JapanYusuke Oike, Sony, Kanagawa, JapanKenichi Okada, Tokyo Institute of Technology, Tokyo, JapanShanthi Pavan, Indian Institute Of Technology, Chennai, IndiaWoogeun Rhee, Tsinghua University, Beijing, ChinaTatsuya Saito, Hitachi, Tokyo, JapanSatoshi Shigematsu, NTT Electronics, Yokohama, JapanJae-Yoon Sim, POSTECH, Pohang, KoreaMasaya Sumita, Panasonic, Moriguchi, JapanYasuhiro Takai, Elpida Memory, Sagamihara, JapanDaisaburo Takashima, Toshiba, Yokohama, JapanKen Takeuchi, University of Tokyo, Tokyo, JapanKoichi Yamaguchi, NEC, Sagamihara, JapanTadaaki Yamauchi, Renesas Electronics, Itami, JapanTaizo Yamawaki, Renesas Electronics, Gunma, JapanSe Hyun Yang, Samsung, Yongin, KoreaJing-Hong Conan Zhan, MediaTek, HsinChu, Taiwan
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HOW TO REGISTER FOR ISSCCOnline: This is the fastest, most convenient way to register and will give you immediate emailconfirmation of your events. To register online (which requires a credit card), go to the ISSCCwebsite at www.isscc.org and select the link to the registration website.
FAX or mail: Use the “2012 IEEE ISSCC Registration Form” which can be downloaded fromthe registration website. All payments must be made in U.S. Dollars, by credit card or check.Checks must be made payable to “ISSCC 2012”. It will take several days before you receiveemail confirmation when you register using the form. Registration forms received withoutfull payment will not be processed until payment is received at YesEvents. Please read thedescriptions and instructions on the back of the form carefully.
Onsite: The Onsite Registration and Advance Registration Pickup Desks at ISSCC 2012 willbe located in the Yerba Buena Ballroom Foyer at the San Francisco Marriott Marquis. All participants, except as noted below, should register or pick up their registration materials atthese desks as soon as possible. Pre-registered Presenting Authors and pre-registeredmembers of the ISSCC Program and Executive Committees must go to the Nob Hill Room,Ballroom level, to collect their conference materials.
REGISTRATION DESK HOURS:
Saturday, February 18 4:00 pm to 7:00 pmSunday, February 19 6:30 am to 8:30 pm Monday, February 20 6:30 am to 3:00 pmTuesday, February 21 8:00 am to 3:00 pmWednesday, February 22 8:00 am to 3:00 pmThursday, February 23 7:00 am to 2:00 pm
Students must present their Student ID at the Registration Desk to receive the student rates.Those registering at the IEEE Member rate must provide their IEEE Membership number.
Deadlines: The deadline for registering at the Early Registration rates is 11:59 pm PacificTime Friday January 13, 2012. After January 13th, and on or before 11:59 pm Pacific TimeMonday January 30, 2012, registrations will be processed at the Late Registration rates.After January 30th, you must register onsite at the Onsite rates. You are urged to registerearly to obtain the lowest rates and ensure your participation in all aspects of ISSCC 2012.
Cancellations/Adjustments/Substitutions: Prior to 11:59 pm Pacific Time Monday January30, 2012, conference registration can be cancelled. Fees paid will be refunded (less a processing fee of $75). Registration category or credit card used can also be changed (for aprocessing fee of $35). Send an email to the registration contractor [email protected] to cancel or make other adjustments. No refunds will be madeafter 11:59 pm Pacific Time January 30, 2012. Paid registrants who do not attend the conference will be sent all relevant conference materials. Transfer of registration to someoneelse is allowed with WRITTEN permission from the original registrant.
MEMBERSHIP SAVES YOU ON ISSCC REGISTRATIONTake advantage of reduced ISSCC registration fees by using your IEEE membership number.If you’re an IEEE member and have forgotten your member number, simply phone IEEE at1(800) 678-4333 and ask. IEEE membership staff will take about two minutes to look upyour number for you. If you come to register onsite without your membership card, you canphone IEEE then, too. Or you can request a membership number look-up by email. Use theonline form at: www.ieee.org/about/help/member_support.html. If you’re not an IEEE member,consider joining before you register to save on your fees. Join online at www.ieee.org/join atany time and you’ll receive your member number by email. If you join at the conference, youcan also select a free Society membership. This offer is not available to existing IEEE members.
All IEEE members are invited to drop into the Member Lounge in the Willow Room behindthe IEEE Exhibit this year. Meet and greet other IEEE members and IEEE staff, learn moreabout products/services, IEEE grade elevations, or just relax.
Upgrade your IEEE membership to Solid-State Circuits Society membership for $28. SSCSmembership provides tutorials and short courses free online at sscs.ieee.org/tutorials-on-line. Students are eligible for conference travel grants with SSCS membership and an application. Add Society membership at sscs.ieee.org/membership or renew or join duringISSCC at the onsite IEEE Exhibit.
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ITEMS INCLUDED IN REGISTRATIONTechnical Sessions: Registration includes admission to all technical and evening sessionsstarting Sunday evening and continuing throughout Monday, Tuesday and Wednesday.ISSCC does not offer partial conference registrations.Technical Book Display: A number of technical publishers will have collections of professionalbooks and textbooks for sale during the Conference. The Book Display will be open on Mondayfrom Noon to 8:00 pm; on Tuesday from 10:00 am to 8:00 pm; and on Wednesday from 10:00am to 3:00 pm. Demo Sessions: Hardware demonstrations will support selected papers from industry andacademia during the Social Hours.Author Interviews: Author Interviews will be held Monday, Tuesday and Wednesdayevenings. Authors from each day’s papers will be available to discuss their work.Social Hour: Social Hour refreshments will be available starting at 5:15 pm on Monday andTuesday in both the Book Display and Author Interview areas.University Events: Several universities are planning social events during the Conference.Check the University Events display at the conference for the list of universities, locationsand times of these events.ISSCC logo umbrella: A folding umbrella will be provided to all conference registrants.Publications: Conference registration includes:-The Digest of Technical Papers in both hard copy and on CD (available onsite beginning onSunday at 4:00 pm, and during registration hours on Monday through Wednesday).-The ISSCC 2012 Conference DVD that includes the Digest and Visuals Supplement (to bemailed in April). Student registration does not include the ISSCC 2011 Conference DVD,however it is available for purchase at a reduced fee for students.
OPTIONAL EVENTSEducational Events: Many educational events are available at ISSCC 2012 for an additionalfee. There are nine 90-minute Tutorials and two all-day Forums on Sunday. There are fouradditional all-day Forums on Thursday as well as an all-day Short Course. All events includea course handout in color. The all-day events also include breakfast, lunch and break refreshments. See the schedule for details of the topics and times.Women’s Networking Event: ISSCC will be sponsoring a networking event for women insolid-state circuits on Monday at 12:15 pm. This luncheon is an opportunity to get to knowother women in the profession and discuss a range of topics including leadership, work-lifebalance, and professional development. By registering and paying a nominal fee for this event,you will receive a ticket, a chance to build new friendships, and an opportunity to expandyour professional network. Please indicate on your ISSCC registration form if you plan to attend this special event, open to women only.
OPTIONAL PUBLICATIONSISSCC 2012 Publications: The following ISSCC 2012 publications can be purchased in advance or onsite:Additional copies of the Digest of Technical Papers in book or CD format.Additional copies of the ISSCC 2012 Conference DVD (mailed in April).ISSCC 2012 Conference DVD at the special student price (mailed in April).2012 Tutorials DVD: All of the 90 minute Tutorials (mailed in May).2012 Short Course DVD: “Low Power Analog Signal Processing” (mailed in May). Short Course and Tutorial DVDs contain audio and written English transcripts synchronizedwith the presentation visuals. In addition, the Short Course DVDs contain a pdf file of the pre-sentations suitable for printing, and pdf files of key reference material.Earlier ISSCC Publications: Selected publications from earlier conferences can be purchased.There are several ways to purchase this material:-Items listed on the registration form can be purchased with registration and picked up atthe conference or mailed to you when available.-Visit the ISSCC Publications Desk. This desk is located in the registration area and has thesame hours as conference registration. With payment by cash, check or credit card, you canpick up (or order for future delivery) materials at this desk. Tutorial and Short Course DVDsfrom prior conferences are available. See the order form for titles and prices.-Visit the ISSCC website at www.isscc.org and click on the link “SHOP ISSCC” where youcan order online or download an order form to mail or fax. For a small shipping fee, this material will be sent to you immediately (or when available) and you will not have to wait untilyou attend the conference to get it.
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HOW TO MAKE HOTEL RESERVATIONS
TO ALL ATTENDEES WHO NEED A HOTEL ROOM: We are offering this year a $100 Marriottrebate coupon! If you register for ISSCC 2012 and spend at least three nights at the SanFrancisco Marriott Marquis, a credit of $100 will be applied to your hotel bill. Enjoy theconvenience of staying at the Conference hotel AND save money too! See the hotel reservations site for details.
Online: ISSCC participants are urged to make their hotel reservations at the San FranciscoMarriott Marquis online. Go to the conference website and click on the Hotel Reservation link.Conference room rates are $215 for a single/double, $235 for a triple and $255 for a quad(per night plus tax). In addition, ISSCC attendees booked in the ISSCC group receive in-roomInternet access for free. All online reservations require the use of a credit card. Online reservations are confirmed immediately. You should print the page containing your confirmation number and reservation details and bring it with you when you travel to ISSCC. Telephone: Call 800-266-9432 (US) or 506-474-2009 and ask for “Reservations.” When making your reservation, identify the group as ISSCC 2012 to get the group rate.Hotel Deadline: Reservations must be received at the San Francisco Marriott Marquis nolater than January 30, 2012 to obtain the special ISSCC rates. A limited number of rooms areavailable at these rates. Once this limit is reached or after January 30th, the group rateswill no longer be available and reservations will be filled at the best available rate.Changes: Before the hotel deadline, your reservation can be changed by calling the telephonenumbers above. After the deadline, call the Marriott Marquis at 888-575-8934 (ask for “Reservations”). Have your hotel confirmation number ready.
REFERENCE INFORMATIONTAKING PICTURES, VIDEOS OR AUDIO RECORDINGS DURING
Hotel Transportation: Visit the ISSCC website “Attendees” page for helpful travel links andto download a document with directions and pictures of how to get from the San FranciscoAirport (SFO) to the Marriott Marquis. You can get a map and driving directions from thehotel website at www.marriott.com/hotels/travel/sfodt-san-francisco-marriott-marquis/
Next ISSCC Dates and Location: ISSCC 2013 will be held on February 17-21, 2013 at theSan Francisco Marriott Marquis Hotel.
