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NI AWR Design Environment AWR Learn. Network. Collaborate awrcorp.com/adf AWR DESIGN FORUM Istanbul - 26 February
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Page 1: Istanbul - 26 February - · PDF filemicrowave monolithic integrated circuit ... de-embedded data and model parameters for inductors ... The fundamentals of spatial diversity and spatial

NI AWR DesignEnvironment

AWR

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AWRDESIGNFORUM

Istanbul - 26 February

Page 2: Istanbul - 26 February - · PDF filemicrowave monolithic integrated circuit ... de-embedded data and model parameters for inductors ... The fundamentals of spatial diversity and spatial

©2016 National Instruments. All rights reserved. A National Instruments Company, Analog Offi ce, AWR, Microwave Offi ce, AXIEM, National Instruments, NI, and ni.com are trademarks of National Instruments. Other product and company names listed are trademarks or trade names of their respective companies.

Time Topic

09:00 – 09:30 Welcome, Registration, and Coffee

09:30 – 10:30 NI AWR Design Environment Overview: New Technologies of

V12 Release and Complete Bits to Beams Radar Simulation

10:30 – 11:15 Integrating Antennas With Linear and Nonlinear Circuits

11:15 – 11:30 Coffee Break

11:30 – 12:15 Phased Arrays and Communications Systems Analysis

With Visual System Simulator

12:15 – 13:00 Using NI AWR Design Environment for Miniaturizing RF Circuits

With LTCC/Laminate Technologies and for BAW/SAW Filter Design

13:00 – 14:00 Lunch

14:00 – 14:30 Tubitak, Mustafa Demirci: Design and Modeling of 10 GHz

Monolithic Inductors for YITAL 0.25um SiGeC BiCMOS Technology

14:30 – 15:00 Design and Simulation of MIMO Systems

15:00 – 15:15 Coffee Break

15:15 – 16:15 RFIC Design Flow With Analog Offi ce

16:15 – 16:45 National Instruments Presentation: TBA

16:45 – 17:15 Q&A, Conclusion, and Lucky Draw

Media Partner:Registrationhttp://bit.ly/1aOwfZe

Event Partners:Aktif Neser Elektronik

Page 3: Istanbul - 26 February - · PDF filemicrowave monolithic integrated circuit ... de-embedded data and model parameters for inductors ... The fundamentals of spatial diversity and spatial

Presentation Abstracts

NI AWR Design Environment Overview: New Technologies ofV12 Release and Complete Bits to Beams Radar Simulation

This presentation begins with an overview of NI AWR Design Environment™ for printed circuit board (PCB),

microwave monolithic integrated circuit (MMIC), low temperature co-fi red ceramic (LTCC), and RFIC designs and

a review of the powerful, innovative technologies contained within the recent V12 release. It will also highlight

how NI AWR Design Environment can be used to simulate and optimize the performance, as well as the cost, of

a complete ISM band radar system based on commercial off the shelf components (COTS). Simulation

examples using NI AWR software will include system, circuit, and antenna analysis.

Integrating Antennas With Linear and Nonlinear Circuits

Analyst™ 3D FEM-based EM solver is integrated into Microwave Offi ce circuit design software along with the

3D planar analysis tool AXIEM, allowing engineers to couple antennas with linear and nonlinear components.

This presentation will begin with an introduction to Analyst, the unique parametrized cells (PCells) approach for

components such as connectors, waveguides, chip packages, and more.

The introduction will be followed by an overview of in-situ antenna measurements, one of the new enhance-

ments in NI AWR Design Environment V12. This unique capability enables engineers to simulate driving circuits

with nonlinear amplifi ers as well as feed networks with antennas in a single simulation.

Phased Arrays and Communications Systems Analysis With Visual System Simulator

This presentation provides a basic overview of the new Visual System Simulator™ (VSS) features in V12, illus-

trating system-level simulation using various real world examples. A transceiver example showing the new VSS

bi-directional simulation capability will be presented, which highlights several new enhancements for complex

system simulations of radars and T/R modules.

Examples during this presentation will include enhanced phased-array simulation capabilities for hundreds and

thousands of elements and new and unique VSS system simulation models, including support for LTE downlink

test models per TS36.141 specifi cations.

ni.com/awr

IstanbulSilence Istanbul HotelKüçükbakkalköy Mah. Dudullu Yolu Cad.No:29 Atasehir, 34758 Istanbul

Venue

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AWRDESIGNFORUM

Page 4: Istanbul - 26 February - · PDF filemicrowave monolithic integrated circuit ... de-embedded data and model parameters for inductors ... The fundamentals of spatial diversity and spatial

ni.com/awr

Presentation Abstracts

Using NI AWR Design Environment for Miniaturizing RF Circuits with LTCC/Laminate Technologies and for BAW/SAW Filter Design

This presentation will overview the LTCC design process within NI AWR Design Environment V12. LTCC technology

is a multi-layer ceramic process that can be used to fabricate low cost, high performance RF and microwave

components. It is an extremely versatile technology that can be used to realize a wide range of components, from

simple passive fi lter structures and packages to complex subsystem assemblies containing discrete SMT

components, bare die, and printed passives. Topics such as creation of a custom LTCC PDK for passive components

and use of planar and 3D EM for modelling of LTCC components and more will be presented. This talk also includes

a design example of packaged SAW chip, including all electromagnetic details of the test board, as well as SAW

package and SAW layout contributing to the distortion of the ideal fi lter performance, enabling proper redesign of

the fi lter resonators to meet the design goals.

Tubitak, Mustafa Demirci: Design and Modeling of 10 GHz Monolithic Inductors for YITAL 0.25um SiGeC BiCMOS Technology

This presentation demonstrates the design, fabrication, and measurement of passive on-chip 10 GHz monolithic

inductors using the back-end metal process of the 0.25 um silicon germanium carbon (SiGeC) bipolar junction

transistor complementary metal oxide semiconductor (BiCMOS) technology being developed in the YITAL

Semiconductor Technologies Researh Laboratory in Turkey. The presentation highlights the use of NI AWR

software, specifi cally AXIEM 3D planar electromagnetic (EM) simulator and Microwave Offi ce circuit design

software. AXIEM was used for the design phase of the inductors and to obtain the S-parameters for

de-embedding structures. After the measurements, de-embedded data and model parameters for inductors

were generated using Microwave Offi ce.

Design and Simulation of MIMO Systems

The compelling reason why modern day communications systems need to utilize a multiple input multiple output

(MIMO) system as opposed to the traditional single input single output (SISO) confi guration will be explained

and the basic concepts of MIMO will be discussed in detail. The fundamentals of spatial diversity and spatial

multiplexing will also be addressed. Different fl avors of MIMO such as signal input multiple output (SIMO) and

multiple input single output (MISO) will be discussed and two receiver structures for SIMO will be illustrated. The

remainder of the presentation will concentrate on the details of a true MIMO 2x2 system. The Alamouti code, a

space time block code, will be discussed. The assumption used for the simulation purposes of a true 2x2 MIMO

will be clearly explained. Finally, simulations of a 2x2 MIMO system will be shown in Visual System Simulator

system simulation software.

RFIC Design Flow With Analog Offi ce

The complexity of today’s new technologies renders traditional design methods inadequate in terms of accuracy,

effi ciency and cost. Analog offi ce ensures complete design closure between IC, package, module, and PCB

design phases. This presentation will highlight the complete RFIC design fl ow. With the help of circuit design

examples, it will cover all the design steps involved in the RFIC design process: schematic simulation, layout,

parasitic and EM extraction, and process corner simulations, as well as well as DRC and LVS to ensure the

manufacturability of the chip layout.

Learn. Network. Collaborate

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AWRDESIGNFORUM


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