ISUAL Sprite Imager Interface and Status Review Stewart Harris.

ISUALSprite Imager

Interface and Status Review

Stewart Harris

NCKU UCB Tohoku Sprite Imager S. Harris

IFR 5 Mar 2001 2

Outline

• Imager Overview• Interface Details• Design and Fabrication Status


IFR 5 Mar 2001 3

Imager Objectives

• Provide high temporal and spatial resolution imaging of Sprites and other emissions related to lightning storms

• Provide imaging of aurora and airglow


IFR 5 Mar 2001 4

Imager Optical Path


IFR 5 Mar 2001 5

Optical Specifications

300 400 500 600 700 800 9000

20

40

60

80

100

Filt

er T

rans

mitt

ance

(%

)

1

ICCD Filter Curves

Wavelength (nm)

23 45

300 400 500 600 700 800 9000

3

6

9

12

15

Det

ecto

r Q

E (

%)

Lens transmission

S25 QE

• Filters– 1: 660 - 900 nm

• notch at 756 - 790

– 2: 762 nm

– 3: 427.8 nm

– 4: 630 nm

– 5: 557.7 nm

– 6: 400 - 900 nm• IR/thermal block


IFR 5 Mar 2001 6

Optical Specifications, con’t.

• Lens– Focal length: 61.8 mm– Field of View: ±10º (h) (20º full angle)

– Focal ratio: f/1.56

– Image size: 21.4 mm horizontal

– Spectral band: 420 - 780 nm– Spot Diameter: on-axis: 16 m

(80% encircled energy) 7º: 22 m10º: 30 m

(Note: Input pixel size: 41.8 m)


IFR 5 Mar 2001 7

Detector specifications

• Image Intensifier– Type: 25 mm Gen II

– Manufacturer: DEP

– Photocathode: Super S25, 6 mm quartz window

– MCP: Single, 100 ns gating

– Phosphor: P46, fiber optic window2 µs decay time constant

• Fiber Optic Taper– Input diameter 25.0 mm

– Output diameter 14.4 mm

– Ratio 1.74 : 1


IFR 5 Mar 2001 8

Detector specifications, con’t.

• CCD– Type: 1024 x 1024, frame transfer

– Manufacturer: Dalsa, IA-D4

– Antiblooming: Vertical anti-blooming (VAB)

– Primary mode: 512 x128 (binned 2x2 and masked)

– Pixel size (unbinned): 12 µm x 12 µm

– Pixel size (binned): 24 µm x 24 µm

– # of Outputs: 2

– Pixel readout rate: 8 MHz


IFR 5 Mar 2001 9

CCD Block Diagram

IA-D4 Image Sensor

Image Area

Storage Area

Output


IFR 5 Mar 2001 10

CCD Active Area Masking

• Imaging Earth Limb– Narrow, 4:1 Aspect Ratio

– CCD Active Area

– Mask applied to f/o taper

– Size: 1024 x 256 (unbinned)

– Size: 512 x 128 (binned)

– FOV: 20° x 5º

Top view of Dalsa CCD with f/o window


IFR 5 Mar 2001 11

Imager Mechanical Layout


IFR 5 Mar 2001 12

Imager Connector Locator

J1Imager

Electrical Board

J4Phosphor

High Voltage

J3MCP High Voltage

J2Front End

Electronics


IFR 5 Mar 2001 13

Imager Electrical Board Functions

• Connections– Thermistors

• TEC hot side

• Lens (front and rear)

• Filter Wheel

• Filter Motor

• Daylight Sensor

• Survival (spacecraft)

– Heater Circuits• Lens (front and rear)

• Filter Wheel

• Survival (spacecraft)

– Thermoelectric Cooler (TEC)• Power controlled from AEP

– Stim Source

• Active Electronics– Photocathode Power Supply

• On/off control

• Gate control from FEC

– DayLight Sensor Buffer• Analog output (left and right)

– Filter Wheel Motor Driver• Stepper motor (2 phases)

• Position indicators (2 bits)


IFR 5 Mar 2001 14

J1 - Imager Electrical InterfaceReference Designator: J1Location: Imager Electrical Board Interface

Connector Type: SDD44F4000GMating Connector: SDD44M1000G

44 31

30 16

SDD44F4 -- Face View

Pin Signal Spec Dir Pin Signal Spec Dir Pin Signal Spec Dir1 CATHODE PS+12V SW DC* IN 16 FILTER HEAT RTN DC 31 CHASSIS GND DC2 TEC TEMP THERM** OUT 17 FILTER TEMP THERM OUT 323 THERMISTOR COM DC 18 DAY SENS +12V SW DC IN 334 TEC V- DC IN 19 RT-DAY SENS OUT ANALOG OUT 345 TEC V+ SW DC IN 20 LT-DAY SENS OUT ANALOG OUT 356 SURVIV HEAT RTN DC 21 DAY SENS RTN DC 367 SURVIV TEMP THERM OUT 22 DAY SENS TEMP THERM OUT 378 SURVIV HEAT +28V SW DC IN 23 MOTOR +12V SW DC IN 389 FR-LENS HEAT +12VSW DC IN 24 PHASE A CONTROL LOGIC IN 3910 LENS HEAT RTN DC 25 MOTOR -12V SW DC IN 4011 FR-LENS TEMP THERM OUT 26 PHASE B CONTROL LOGIC IN 4112 R-LENS HEAT +12V SW DC IN 27 MOTOR TEMP THERM OUT 4213 LENS HEAT RTN DC 28 WHEEL POS B0 LOGIC OUT 4314 R-LENS TEMP THERM OUT 29 WHEEL POS B1 LOGIC OUT 4415 FILTER HEAT +12V SW DC IN 30 WHEEL MON COM DC

* SW DC: Switched DC Power Input** THERM: Thermistor output.


IFR 5 Mar 2001 15

Image Intensifier Interface

Imager Electrical Board

J1 - 44 pin

Photocathode Power Supply

Image Intensifier - 25 mm

MCP-Out-1kV

HV Supply

Phosphor (Anode -6kV) HV Supply

GATEFEC Connector

J4 - 9 pin J3 - 9 pin

MCP-In GND


IFR 5 Mar 2001 16

J3 - MCP HVPS InterfaceReference Designator: J3Location: Imager, MCP (stbd) HVPS

Connector Type: SND9F5000GMating Connector: SND9M1000G

Pin Signal Spec Dir Pin Signal Spec Dir1 +12V SW DC* IN 62 VMONITOR ANALOG OUT 7 GND DC3 VCONTROL ANALOG IN 84 IMONITOR ANALOG OUT 9 TEMP THERMISTOR OUT5 TRTN DC

* SW DC: Switched DC Power Input

SND9F5 -- Face View


IFR 5 Mar 2001 17

J4 - Phosphor HVPS InterfaceReference Designator: J4Location: Imager, Phosphor (port) HVPS

Connector Type: SND9F5000GMating Connector: SND9M1000G

Pin Signal Spec Dir Pin Signal Spec Dir1 +12V SW DC* IN 62 VMONITOR ANALOG OUT 7 GND DC3 VCONTROL ANALOG IN 84 IMONITOR ANALOG OUT 9 TEMP THERMISTOR OUT5 TRTN DC

* SW DC: Switched DC Power Input

SND9F5 -- Face View


IFR 5 Mar 2001 18

Front End Electronics Block Diagram

Digital I/O

Timing Generator

Based on FPGA

Develops Bias & Clock Voltages

Linear Regulators

Voltage Monitor

Clock Drivers: Analog SPDT Switches

R/C waveform shaping

CCD

Preamps

Correlated Double Sample

A/D Converters

J2


IFR 5 Mar 2001 19

Front End Electronics Interface

• Data[0..11]– 12 bits per pixel

• PixelClock (PIXCLK)

– pixel data strobe

• FrameValid (FRMV)

– indicates duration of frame

• LineValid (LINV)

– indicates duration of line

– used only during test

• Busy (BUSY)

– signals start of EXP

• Acquire (ACQ)

– signals start of exposure in Aurora mode

– signals Event in Sprite mode

• CommandData (CDI)

– serial data interface for upload of camera parameters

• VoltageMonitor (MON)

– switched analog output

• Power– dc voltages

Images are transferred to the AEP in data frames,each frame is 128 lines x 512 pixels


IFR 5 Mar 2001 20

J2 - FEC Electronics InterfaceReference Designator: J2Location: Imager, rear panel FEC

Connector Type: SDD62F4000GMating Connector: SDD62M1000G

Pin Signal Spec Dir Pin Signal Spec Dir Pin Signal Spec Dir1 COM DC IN 22 COM DC IN 43 +12VP SW DC IN2 +5VP SW DC* IN 23 +5VP SW DC IN 44 +12VP SW DC IN3 FRMV+ RS422 OUT 24 FRMV- RS422 OUT 454 LINV+ RS422 OUT 25 LINV- RS422 OUT 465 PIXCLK+ RS422 OUT 26 PIXCLK- RS422 OUT 476 ACQ+ RS422 IN 27 ACQ- RS422 IN 48 BUSY- RS422 OUT7 D0+ RS422 OUT 28 D0- RS422 OUT 49 BUSY+ RS422 OUT8 D1+ RS422 OUT 29 D1- RS422 OUT 50 DGND DC OUT9 D2+ RS422 OUT 30 D2- RS422 OUT 51 CCLK- RS422 IN10 D3+ RS422 OUT 31 D3- RS422 OUT 52 CCLK+ RS422 IN11 D4+ RS422 OUT 32 D4- RS422 OUT 53 DGND DC IN12 D5+ RS422 OUT 33 D5- RS422 OUT 54 CDAT- RS422 IN13 D6+ RS422 OUT 34 D6- RS422 OUT 55 CDAT+ RS422 IN14 D7+ RS422 OUT 35 D7- RS422 OUT 56 DGND DC IN15 D8+ RS422 OUT 36 D8- RS422 OUT 57 CSTB- RS422 IN16 D9+ RS422 OUT 37 D9- RS422 OUT 58 CSTB+ RS422 IN17 D10+ RS422 OUT 38 D10- RS422 OUT 59 MONL DC OUT18 D11+ RS422 OUT 39 D11- RS422 OUT 60 MONH ANALOG** OUT19 40 61 CCDTEMP THERMISTOR OUT20 -12VP SW DC IN 41 -12VP SW DC IN 6221 COM DC IN 42 COM DC IN

* SW DC: Switched DC Power Input** Analog: Monitor output (MONH) is switched output, -5 to +5 VDC


IFR 5 Mar 2001 21

Data Transfer Timing

Line Timing

Pixel Timing

Tframe = 9.6 ms

Tline = 75 s

Tpixel = 125 ns

N > 512

FRMV

LINV

PIXCLK

DATA[0..11]

LINE 1 LINE 2 LINE 128

T frame

lineT

LINV

PIXCLK

DATA[0..11] PIXEL 1 PIXEL 2 PIXEL N-1 PIXEL N

pixelT


IFR 5 Mar 2001 22

Image Readout Order

CCD array is illustrated showing the order in which pixels are transferred from Imager to AEP

1

2

127

128

Line

1. Each cell represents one pixel

2. Since the CCD is read from two outputs, the image is split in the middle

1 3 509 511

513 515 1021 1023

24510

1024

512

65536

1022 514516

65534 65028 6502665535655336502765025

64513 64515 65021 65023 65024 65022 64516 64514


IFR 5 Mar 2001 23

Aurora Mode Imaging

Take exposure

Shift image entire vertical register

Read out image

The time to shift and readout one image: ~15 ms

Exposure duration can be as long as ~ 1 second

N - 1

N - 1

N - 1


IFR 5 Mar 2001 24

Frame Timing - Aurora Mode

* EXP and VSHIFT are only indicating the relative timing of the exposure period and CCD vertical shift period

Notes:

1. Images are taken while ACQ held high.

2. Exposure duration specified by parameter EXP 1 ms TExp 1 sec

3. Frame repetition period specified by parameter REPRATE(TExp + TFrame + TVshift ) TReprate 5 sec

4. Frame readout period is fixed, TFrame = 9.6 ms

5. Vertical shift duration is fixed, TVshift ~ 5 ms (Aurora Mode)

Reprate

VSHIFT*

EXP*

BUSY

T

ACQ

FRMV

Exp T

FrameT

VshiftT


IFR 5 Mar 2001 25

Sprite Continuous Mode Clocking

N

N - 4

N - 3

N - 2

N - 1

N - 5

N

N - 4

N - 3

N - 2

N - 1

N

N - 4

N - 3

N - 2

N - 1

N + 1

N

N - 3

N - 2

N - 1

N + 1

N

N - 3

N - 2

N - 1

N + 1

N + 2

Image Area

Storage Area

Expose New Image

AND

Shift & Read image from Storage Area

Shift Image & Storage Areas

Transferanother image into Storage Area

Repeat Cycle

Note: Storage area is shifted twice as often

Tframe


IFR 5 Mar 2001 26

Frame Timing - Sprite Continuous

Notes:

1. Imaging begins when FSW sets mode to Sprite Continuous

2. ACQ signals the Sprite Event occurrence

3. Exposure duration specified by parameter EXP 1 ms TExp 100 ms

4. Frame repetition period specified by parameter REPRATE( max(TExp , TFrame) + TVshift ) TReprate 100 ms


6. Vertical shift duration is fixed, TVshift = 1.3 ms (Continuous Mode)

7. No attempt is made to synchronize EXP with GDelay

FRMV

BUSY

EXP*

VSHIFT*

ACQ

ReprateTExpT

FrameT GdelayT

1 2 3 4 5 6 7

21 7 8

12 13

T Vshift


IFR 5 Mar 2001 27

Sprite Burst Mode ClockingN

N - 1 N

N - 1

N + 1

N

N - 1

N + 1

N + 2

N

N - 1

N + 1

N + 2

N + 3N - 1

N

N - 1

N + 1

N + 2

N + 3

N

N - 1

N + 1

N + 2

N + 3

N

N + 1

N + 2

N + 3

N + 1

N + 2

N + 3

N + 2

N + 3

N + 3

Tframe

N • Tframe

Begin acquisition of N images at leading edge of Event Trigger

Image readout time ~ (N+1) • Treadout

Treadout

Acquisition Phase

Readout Phase


IFR 5 Mar 2001 28

Frame Timing - Sprite Burst Mode

Notes:

1. Continuous fast exposures begin when FSW sets mode to Sprite Burst

2. When ACQ occurs, NPost exposures are taken, then 8 images are readout

3. Exposure duration specified by parameter EXP 1 ms TExp 100 ms

4. Frame repetition period specified by parameter REPRATE(TExp + TVshift ) Treprate 10 ms


6. Vertical shift duration is fixed, TVshift < 750 s (Burst Mode)

VSHIFT*

EXP*

BUSY

FRMV

ACQ

1 2 3 4 5 6 7 8

1 2 7 8

Gdelay T T Frame

T Reprate

Exp T


IFR 5 Mar 2001 29

Principal Camera Parameters

• Gated operation enable• Photocathode gate open/close• Set Mode (Aurora, Sprite Continuous, Sprite Burst)• Set number of Post Trigger Images, NPOST

– Only used in Burst Mode (TBD)

• Set Exposure (EXP) duration• Set repetition (REPRATE) period• Set photocathode Gate Delay (GDELAY)• Note:

– Dark image acquire accomplished by disabling gated operation,force gate closed, set mode and acquire dark image.


IFR 5 Mar 2001 30

Camera Parameters (Complete List)

Imager CDI Commands

Range of Values

Gated operation enable yes / noGate Open/Close open / closeSet Mode (Aurora, Sprite Continuous, Sprite Burst) 1, 2, or 3Set exposure duration time (EXP) 1, 2, 3 … 1000 msAdjust V12Hi voltage 0, 1, 2, 3Adjust V3Hi voltage 0, 1, 2, 3Set Gate open delay (GDELAY) 0, 100, 200 … 10000 sSet Vertical Binning on/off on / offSelect monitor voltage 0, 1, 2 … FSet repetition period (REPRATE) 0, 1, 2 … 1000 msCR1 readout clock pattern 0x000 … 0xFFFCR2 readout clock pattern 0x000 … 0xFFFCR3 readout clock pattern 0x000 … 0xFFFRST readout clock pattern 0x000 … 0xFFFADC Clock pattern 0x000 … 0xFFFSUMG readout clock pattern 0x000 … 0xFFFNumber clock periods per serial readout cycle 0, 1, 2 … A, B, CSet vertical shift period (VRATE) setting 1, 2, 3 … FNumber of Post trigger images (NPOST) {burst only} 0, 1, 2 … 7


IFR 5 Mar 2001 31

Imager Design Status

• Breadboard fabrication and testing complete• Detailed design in progress

– FEC Electronics Design• Schematics: 6 of 7 completed

• PCB Layout: 5 of 7 completed

– Imager Electrical Board Design• In progress

– Imager Mechanical Design• In progress


IFR 5 Mar 2001 32

FEC Breadboard

A breadboard version of the FEC electronics was built to test the design of clock drivers, preamps, correlated double sample (CDS) circuitry and 12-bit A/D conversion.


IFR 5 Mar 2001 33

Breadboard Camera Measurements

• Measured system gain 29 e-/ADU

• Measured readout noise < 50 e- rms

• CCD full well ~ 120,000 e-

• Dynamic range > 2400:1

• Operating Parameters Master clock: 22.5MHz

Pixel clock: 7.5 MHz

Line clock: 340 kHz


IFR 5 Mar 2001 34

Breadboard Camera Image


IFR 5 Mar 2001 35

Imager Fabrication Status

• Assembly of ETU Imager to start 15 May– All PC boards need to be etched by this date

• FEC Board etch has already started

– All Mechanical parts to be fabricated by this date

– Electrical / Electronic (EE) Parts status• see next page

– Optics Parts status• see next page


IFR 5 Mar 2001 36

EE Parts and Optics Status

EE Parts and Optics Ordered Delivered Ordered DeliveredMicrocircuits

CCD ü ü ü üA/D Converter ü ü ü 5/15/01Oscillator ü ü ü 5/30/01All others ü ü ü ü

Interconnection DevicesCCD pin contacts ü ü ü üHSP030M2G (pin contacts) ü 3/20/01 ü 3/20/01All others ü ü ü ü

Discrete SemiconductorsAll devices ü ü ü ü

Passive DevicesInductors/Magnetics

Tape wound core (xfmr) ü ü P PSpiradel Delay Lines ü ü ü 5/1/01All others ü ü ü ü

Capacitors ü ü ü 4/9/01Resistors ü ü ü 4/9/01

Optical ComponentsWindow, fused silica P P P PFilters (set of 6), 70 mm ü P ü PLens, 61.8 mm ü ü ü üImage Intensifier ü ü ü üFiber Optic Taper, 25 mm ü 3/2/01 ü 3/2/01Mask Application on Taper P P P PFiber Optic Window, 5 mm ü ü ü ü

Revised : 3/1/01 ü : Completed P : Pending information

Engineering Test Unit Flight Unit


IFR 5 Mar 2001 37

The End


IFR 5 Mar 2001 39

PCB Assembly Drawing

FEC Analog Processor PC Board: Assembly Dwg. 8747-A4AReturn

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ISUAL Sprite Imager Interface and Status Review Stewart Harris.

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