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ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language...

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ITEC 352 Lecture 11 ISA - CPU
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Page 1: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ITEC 352

Lecture 11ISA - CPU

Page 2: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

Review

• Questions?• HW 2 due on Friday• ISA

– Machine language– Buses– Memory

Page 3: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

Outline

• P1 is posted• CPU

Page 4: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

Architecture

• Contains: Data Section and Control Unit

Data Section: Registers and ALU (they do the processing)

Control Unit: controls the processing.`

Page 5: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

CPU

• Registers– One type of memory.

• Each register can usually store a word (there are some that store a byte).– They are few in number (usually range from 16 onwards to something

higher).– Hence, they require fewer bits to represent their addresses.

• E.g., if we had 16 registers, we would only need 4 bits to address them (contrast this with 32 bit memory).

– Hence, it is very fast memory.• ALU: Arithmetic and Logic Unit: This implements a variety of

binary and unary operations. Examples: ADD, MULTIPLY, AND, NOT, OR etc…

Page 6: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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ISA definition

• Every control unit is pre-programmed with a set of basic instructions. – E.g.,

• IA-32 (Intel 32 bit processor) instruction set: – http://siyobik.info/main/reference

– ARM processors (used in DROID and other mobile devices) instruction set: – http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001m/QRC0001_UAL.pdf

• SUN SPARC instruction set (32 bit) (version 7)• http://www.cs.utexas.edu/users/novak/sparcv7.pdf

• These basic instructions are called Instruction sets and the architecture supporting the instruction set is refereed as Instruction Set Architecture (ISA).

– E.g., SUN SPARC Version 7 32 bit ISA• ARM 11 ISA

• NEXT: A second in the life of a program (from program to a process).

Page 7: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

Program to Process: The process of compilation, linking and loading

(overview)Program in

high level language(e.g., C/C++/Java/ADA)

Libraries(e.g., stdlib)

Assembly code (Java is a little different)

Assembly code

Combined machinecode

Machine Code Machine CodeWaiting (and happy)

to be executed

COMPILATION

ASSEMBLY

LINKING

LOADING

A second (or much less) in the life of a high-level program

Page 8: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

Compiler/OS

Program inhigh level language

(e.g., C/C++/Java/ADA)

Libraries(e.g., stdlib)

Assembly code (Java is a little different)

Assembly code

Combined machinecode

Machine Code Machine CodeWaiting (and happy)

to be executedBy the CPU

COMPILATION

ASSEMBLY

LINKING

LOADINGOperating System

COMPILER

Page 9: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Portability

• Java programs are compiled into “Java bytecode”– Java bytecode is analogous to an ISA.

• Depending on the specific CPU (Intel or ARM etc.), – Java’s bytecode is mapped to specific

ISA.

Page 10: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Program to Process

A specific ISA can only execute the instructions it supports.

• E.g., to execute a Java program:– It has to be finally translated into the specific

ISA.

Page 11: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

Compilation

• Consider the following harmless statement in a high level language: A = B + 4 To compile this program in a high level language (say Java), it

must first reduce the statement to various symbols in the language.

Symbols in the example statement:

A = B + 4

Identifiers Operators (delimiters) constant

This phase in compilation is called Lexical Analysis.

Page 12: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Lexical Analysis (2)

• How does compiler store information about the symbols in a statement ? • Answer: Symbol table. • Symbol table contains several records. Each record in the table usually has

the following information:– Name of the symbol if it is an identifier (Stored as a String) or a key word like

“constant” if the symbol happens to be a contant value. • E.., A, B

– Type of the identifier or constant. E.g., (integer , …) • This value cannot be filled up during the lexical analysis. We will see how this

value is derived later. – Scope of the identifier (if the identifier is a variable – what is its scope).

Remember scope from a previous slide.

Page 13: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Lexical Analysis (3)

• Example – For the statement: A = B + 4 The compiler builds the symbol table:

Name: A UNKNOWN UNKNOWN

Name: B UNKNOWN UNKNOWN

CONST:4 UNKNOWN UNKNOWN

Name Type Scope

Page 14: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

ISA (2)

Static Analysis

• Lexical analysis is done in parallel with syntactic analysis. Here, the compiler checks to see if the syntax of the statement is correct.– For instance, in Java, the statement A = B + 4 is incorrect,

because at the end of the statement Java expects a “semicolon”.

– We will not go into details of how it check the syntax. Lets just assume it does.

• As part of these analysis, a brief step is the building of a syntax tree.

Page 15: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Syntax tree

• A syntax tree captures the syntax of a statement. The nodes of the tree are operators (or delimiters). The leaves are the symbols.

+=

Symbol table entry of B Symbol table entry of 4

Symbol table entry of A

Page 16: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Semantic Analysis

• After determining the syntax is correct, the compiler does a semantic analysis. – Usually, in many programming languages this requires that the compiler make

a second pass across the program.– THIS ALLOWS A PROGRAM TO USE VARIABLES OR FUNCTIONS DEFINED

LATER. This is called FORWARD REFERENCING• In this phase, the compiler determines and check the types of variables

and functions. E.g., In A = B + 4, it determines the type of A and B (perhaps int A and int B) and then

checks to see if the statement is correct when A and B are ints). E.g., if B is a String, the above statement will be incorrect – a compilation error is thrown here.

– Also in this phase the compiler adds the remaining entries of the symbol table

Page 17: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Semantic Analysis (2)

• After the type checking phase during semantic analysis

Name: A int scope of A

Name: B int scope of B

CONST :4 int

Name Type Scope

Page 18: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Code Generation

• In this phase, the compiler generates the assembly code. – Usually, the compiler first converts the program (the

syntax tree) into an intermediate form of pseudo code that closely parallels assembly.

– It then maps the pseudo code into assembly.– This is because, assembly is specific to an architecture –

hence this step is not portable across different machines. Converting to pseudo code however is portable.

• Hence, compiler writers can simply port their compilers to different OSes by changing this one last step.

Page 19: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Code generation

• The statement A = B + 4 is now generated into specific ISA:

ld [B], %r1add %r1, 4, %r2st %r2, %r0, [A]

Page 20: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Compilation: end of our discussion

• So far we looked at the process of compilation. – For more information, you should take a course on

Compilers/Translators (offered sometimes in Spring by Dr. Okie) (or) read a very popular textbook in Compilers called the “Dragon Book”

Page 21: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Summary

• Compiler: – Programs are compiled into machine code

• Operating system: – executes a program (program in execution is called a

process). – Execution starts when a user passes the program as an

argument to a “method/function call” called exec implemented by the OS.

• Next how does the control unit interact with the OS?– How does it execute the machine code that the OS

wants it to execute?

Page 22: ITEC 352 Lecture 11 ISA - CPU. ISA (2) Review Questions? HW 2 due on Friday ISA –Machine language –Buses –Memory.

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Next.

• Once machine code is generated, linked and loaded, it is executed by the CPU.

• Next: The all important: Fetch – execute cycle.– Defines how instructions are executed.– Every commercial architecture out there

(from Intel to ARM) follows this cycle.


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