J. Coughlan et al. 1st October 2003 LECC 2003 Amsterdam The CMS Tracker Front-End Driver 9 th Workshop on Electronics for LHC Experiments Amsterdam J.A.Coughlan , S.A. Baird, I. Church, C.P.Day, E.J.Freeman, W.J.F.Gannon, R.N.J. Halsall, M. Pearson, G. Rogers, J. Salisbury, S.Taghavirad, I.R.Tomalin CCLRC Rutherford Appleton Laboratory E. Corrin, C.Foudas, J. Fulcher, G. Hall, G. Iles, M. Noy, O. Zorba Imperial College I. Reid Brunel University Presented by John Coughlan [email protected]
Transcript
J. Coughlan et al. 1st October 2003LECC 2003 Amsterdam
The CMS Tracker Front-End Driver
9th Workshop on Electronics for LHC Experiments Amsterdam
J.A.Coughlan, S.A. Baird, I. Church, C.P.Day, E.J.Freeman, W.J.F.Gannon,R.N.J. Halsall, M. Pearson, G. Rogers, J. Salisbury, S.Taghavirad, I.R.Tomalin
CCLRC Rutherford Appleton Laboratory
E. Corrin, C.Foudas, J. Fulcher, G. Hall, G. Iles, M. Noy, O. ZorbaImperial College
Chip-Scope Pro Logic Analyser capture10 bit-raw data on 12 channels in FE FPGA
sine input (1 MHz) via Cross-Point Switch test card to 12 channels
first 100 (of 4k) samples @ 40 MHz
ADC count
NB Chip-Scope also invaluable as Firmware Debugger!
Testing analogue circuits, connections etc
J. Coughlan et al. 1st October 2003LECC 2003 Amsterdam
CMS Tracker FED First prototype 6U VME Opto-Tester
VME interface logic
Analogue section
Sequence control logic
Sequence storage
DACAmplification+cmAnalogue opto-tx
Acknowledgements for following results to Acknowledgements for following results to Matthew NoyMatthew Noy , Imperial College , Imperial College
Drives up to 3 Fibres
J. Coughlan et al. 1st October 2003LECC 2003 Amsterdam
CMS Tracker FED Early Analogue Characterisation effects
RMS noise of ~ 1.1 counts ≈ 350e- (including ORx)
ADC? effect under investigation
Ch. 0 23with ORx
Ch. 24 95without ORx
Important that FED meets analogue specifications toodetailed characterisation only possible with complete modules and sophisticated tester (built - also needs evaluation and careful control)
All preliminary results are positive details under study … e.g. ….
Timing scan of 25 nsec pulse
J. Coughlan et al. 1st October 2003LECC 2003 Amsterdam
CMS Tracker FED Other Test Results
Require fine & coarse clock skewingindependently on all 96 FED channels
32 fine steps of ~ 800 psec
Implemented by Virtex-IIDigital Clock Managers
Independent TrimDAC offsets at ADC inputson all 96 FED channels
ADC Linearity plot
J. Coughlan et al. 1st October 2003LECC 2003 Amsterdam
CMS Tracker FED FED Large Scale Opto-Tester
• Relatively sophisticated tester needed to evaluate FEDs fullyneed to compare analogue input with digital outputs
large volume of well defined data must be scrutinised
analogue performance should not degrade systemnoise - characterise complete FED, not just single channels
input data should be very stable - challenging given laser T sensitivity
• Tester system comprises 4 modules, each driving 24 optical channels.
Each module has 3 unique analogue channels, each driven by 12 bit, 40MHz DACs.
Cross-point switches allow the 24 outputs to select any of these 3 channels or an external one.
The FED Tester can act as a Trigger Control System if needed (e.g provide Clk, L1As, BC0, etc)
System control is achieved with 2 Virtex II, 1M gate FPGAs
J. Coughlan et al. 1st October 2003LECC 2003 Amsterdam
CMS Tracker FED FED Large Scale Opto-Tester
DACsFibre reels
8-way MU optical connectors
Clks provided via QPLLs
Analogue Optical Hybrids
Cross-point switches
VME interface
System control FPGA
Awaiting AOHs to complete first 24 channel module(G. Iles, J. Leaver + C. Foudas, O. Zorba)Refer to talk at these proceedings
J. Coughlan et al. 1st October 2003LECC 2003 Amsterdam
CMS Tracker FED First FED Readout of 9U Opto-Tester Data
12
10
8
6
4
2
0
Pai
r of
AP
Vs
350340330320310300290
Clock Count
Now using Final FirmwareFinal Firmwarein all FPGAsFully formatted DAQ eventsDAQ eventsvia VME readout
