DSP OVERVIEWDSP OVERVIEW

• DSPs are like “traditional” embedded DSPs are like “traditional” embedded microprocessorsmicroprocessors

• DSPs are designed to meet sophisticated DSPs are designed to meet sophisticated “signal processing algorithms”“signal processing algorithms”

• DSPs are used in drives, audio & video DSPs are used in drives, audio & video applications, image applications, bio applications, image applications, bio medical, industrial automations etc.,medical, industrial automations etc.,

ADVANTAGES OF DSP……ADVANTAGES OF DSP……

• Easy to change applicationsEasy to change applications

• Better control & accuracyBetter control & accuracy

• Easy to execute complex algorithms like svpwm, Easy to execute complex algorithms like svpwm, vector control , dtc etc.,vector control , dtc etc.,

• Compact in size (ic)Compact in size (ic)

• Cost effective (ic) for particular applications. Cost effective (ic) for particular applications.

DSP LEADING MANUFACTURERSDSP LEADING MANUFACTURERS

• Texas instrumentsTexas instruments

• Analog devicesAnalog devices

• Motorola Motorola

TEXAS INSTRUMENTS DSP TEXAS INSTRUMENTS DSP FAMILYFAMILY• TMS320C2000TMS320C2000

C24x, C28xC24x, C28x• TMS320C5000TMS320C5000

C54x,C55xC54x,C55x• TMS320C6000TMS320C6000

C62x,C64x,C67xC62x,C64x,C67x

TMS320 DEVICE NOMENCLATURETMS320 DEVICE NOMENCLATURE

DSP BASED MOTOR CONTROLDSP BASED MOTOR CONTROL

• TMS320C2000 series offers various processors for TMS320C2000 series offers various processors for motor control applications motor control applications

• Based on the requirements user can choose the Based on the requirements user can choose the following processorsfollowing processors

TMS320C240TMS320C240

TMS320LF2407TMS320LF2407

TMS320LF2812TMS320LF2812

LF2407 KEY FEATURESLF2407 KEY FEATURES

• 3.3v operating volts3.3v operating volts

• 16 bit fixed point processor with 144 pins16 bit fixed point processor with 144 pins

• 40MHz operating frequency40MHz operating frequency

• 32KWord FLASH memory, 2.5 K Word RAM32KWord FLASH memory, 2.5 K Word RAM

• 40 general-purpose I/O (GPIO) lines40 general-purpose I/O (GPIO) lines

• Event managerEvent manager

•10 bit, 16 channel ADC with 500ns as 10 bit, 16 channel ADC with 500ns as conversion timeconversion time

•Serial communication interface (SCI)Serial communication interface (SCI)

•Serial peripheral interface (SPI)Serial peripheral interface (SPI)

•Watchdog timerWatchdog timer

•In-built space vector hardwareIn-built space vector hardware

TMS320LF2407 ARCHITECTURETMS320LF2407 ARCHITECTURE

CENTRAL PROCESSING UNITCENTRAL PROCESSING UNIT

• AA 32-bit central arithmetic logic unit (CALU)32-bit central arithmetic logic unit (CALU)

• A 32-bit accumulatorA 32-bit accumulator

• Data-scaling shifters Data-scaling shifters

• A 16-bit X 16-bit multiplierA 16-bit X 16-bit multiplier

• A 32-bit product registerA 32-bit product register

• 8 auxiliary registers and an auxiliary register arithmetic unit 8 auxiliary registers and an auxiliary register arithmetic unit

MEMORYMEMORY

• 544 words * 16 bits of on-chip data/program dual-544 words * 16 bits of on-chip data/program dual-access RAMaccess RAM

• 32K words * 16 bits of on-chip program 32K words * 16 bits of on-chip program Flash EEPROMFlash EEPROM

• 2K words * 16 bits of single-access RAM2K words * 16 bits of single-access RAM

• External memory interface moduleExternal memory interface module

PLL CLOCK MODULEPLL CLOCK MODULE

PLL Clock Module provides all of the clocks required for the PLL Clock Module provides all of the clocks required for the entire device.entire device.

• CPUCLKCPUCLK – – This is the highest frequency clock provided by the This is the highest frequency clock provided by the module and is used by the CPU, all memories and any module and is used by the CPU, all memories and any peripherals tied directly to the CPUs buses, including an peripherals tied directly to the CPUs buses, including an external memory interface if used. external memory interface if used.

• SYSCLKSYSCLK – – This clock is a half or a quarter the rate of CPUCLK. This clock is a half or a quarter the rate of CPUCLK. It is used to clock all the peripherals on the TI peripheral bus.It is used to clock all the peripherals on the TI peripheral bus.

• WDCLKWDCLK – – This is the low power clock used by the watchdog This is the low power clock used by the watchdog timer/real- time interrupt module. timer/real- time interrupt module.

WATCHDOG TIMER MODULEWATCHDOG TIMER MODULE

• Internal 8 bit re-settable up counting timer, that Internal 8 bit re-settable up counting timer, that reset the system if software fails to operate reset the system if software fails to operate properly.properly.

• If the software goes into an improper loop, or if If the software goes into an improper loop, or if the CPU becomes temporarily disrupted, the WD the CPU becomes temporarily disrupted, the WD timer overflows to assert a system reset.timer overflows to assert a system reset.

• The watchdog increases the reliability of the The watchdog increases the reliability of the CPU, thus ensuring system integrity.CPU, thus ensuring system integrity.

SERIAL COMMUNICATION INTERFACE SERIAL COMMUNICATION INTERFACE MODULEMODULE

• The programmable SCI module supports digital The programmable SCI module supports digital communications between the CPU and other communications between the CPU and other asynchronous peripherals.asynchronous peripherals.

• To ensure data integrity, the SCI checks data that To ensure data integrity, the SCI checks data that has been received for break detection, parity, has been received for break detection, parity, overrun, and framing errors.overrun, and framing errors.

• The speed of the bit rate (baud) is programmable to The speed of the bit rate (baud) is programmable to over 64K different speeds through a 16-bit baud-over 64K different speeds through a 16-bit baud-select register.select register.

SERIAL PERIPHERAL INTERFACE MODULESERIAL PERIPHERAL INTERFACE MODULE

• The SPI is a high-speed synchronous serial input/ The SPI is a high-speed synchronous serial input/ output (I/O) port that allows a serial bit stream of output (I/O) port that allows a serial bit stream of programmed length (one to eight bits) to be shifted into programmed length (one to eight bits) to be shifted into and out of the device at a programmed bit-transfer rate.and out of the device at a programmed bit-transfer rate.

• The SPI is normally used for communications between The SPI is normally used for communications between the DSP controller and external peripherals or another the DSP controller and external peripherals or another controller.controller.

• SPI applications include external I/O or peripheral SPI applications include external I/O or peripheral expansion via devices such as shift registers, display expansion via devices such as shift registers, display drivers, and analog-to-digital converters (ADCs).drivers, and analog-to-digital converters (ADCs).

DIGITAL I/O MODULEDIGITAL I/O MODULE

• The digital I/O ports module provides a The digital I/O ports module provides a flexible method for controlling both flexible method for controlling both dedicated I/O and shared pin functionsdedicated I/O and shared pin functions

• The LF2407 has a total of 40 shared I/O linesThe LF2407 has a total of 40 shared I/O lines

• I/O ports can be used as i/o lines or as pwm I/O ports can be used as i/o lines or as pwm lineslines

EVENT MANAGER (EV) MODULEEVENT MANAGER (EV) MODULE• The EV module provides functions and features that are required for motor The EV module provides functions and features that are required for motor

control applicationscontrol applications

• LF2407 has two event managers EVA & EVBLF2407 has two event managers EVA & EVB

• Features:Features:

2 general-purpose (GP) timers2 general-purpose (GP) timers

3 compare units3 compare units

3 capture units3 capture units

quadrature encoder pulse(QEP) circuitquadrature encoder pulse(QEP) circuit

space vector pwm circuitsspace vector pwm circuits

dead band generation unitsdead band generation units

output logic circuitsoutput logic circuits

EV BLOCK DIAGRAMEV BLOCK DIAGRAM

PWM OUTPUTPWM OUTPUT

EVENT MANAGER REGISTERSEVENT MANAGER REGISTERS• EVENT MANAGER TIMER REGISTERSEVENT MANAGER TIMER REGISTERS

• GPTCONAGPTCONA -- General purpose timer control register General purpose timer control register • T1CNTT1CNT -- Timer1 counter registerTimer1 counter register• T1CMPRT1CMPR -- Timer1 compare registerTimer1 compare register• T1PRT1PR -- Timer1 period registerTimer1 period register• T1CONT1CON -- Timer1 control registerTimer1 control register

• EVENT MANAGER COMPARE CONTROL REGISTERSEVENT MANAGER COMPARE CONTROL REGISTERS

• COMCONACOMCONA -- Compare control registerCompare control register• ACTRAACTRA -- Action control registerAction control register• DBTCONADBTCONA -- Dead-band control registerDead-band control register• CPMR1CPMR1 -- Compare register1Compare register1• CMPR2CMPR2 -- Compare register2Compare register2• CMPR3CMPR3 -- Compare register3Compare register3

SPACE VECTOR PWM MODULESPACE VECTOR PWM MODULE

• The EV module has built-in hardware to The EV module has built-in hardware to generate svpwmgenerate svpwm

• Software is used to generate svpwm Software is used to generate svpwm outputsoutputs

CAPTURE & QEP UNITSCAPTURE & QEP UNITS• The capture & QEP units can be used to The capture & QEP units can be used to

interface with an optical encoder to get interface with an optical encoder to get speed information from the rotating speed information from the rotating machinemachine

• Capture unit is used to sense the actual Capture unit is used to sense the actual speed of the machinespeed of the machine

• QEP is used to find the direction of rotation QEP is used to find the direction of rotation of the machineof the machine

ANALOG TO DIGITAL ANALOG TO DIGITAL CONVERTERCONVERTERFeatures:Features:

• 10-bit ADC core with built-in S/H circuit10-bit ADC core with built-in S/H circuit

• Fast conversion time of 500nsFast conversion time of 500ns

• 16 multiplexed analog input16 multiplexed analog input

• Two independent 8 state sequencer can beTwo independent 8 state sequencer can be operated in dual-sequencer or cascaded modeoperated in dual-sequencer or cascaded mode

• 16 result registers to store the digital values16 result registers to store the digital values

ADC BLOCK DIAGRAMADC BLOCK DIAGRAM

ADC CONTROL REGISTERSADC CONTROL REGISTERS

• ADCTRL1ADCTRL1 - Adc control register1- Adc control register1

• ADCTRL2ADCTRL2 - Adc control register2- Adc control register2

• MAXCONVMAXCONV- Maximum conversion reg- Maximum conversion reg

• CHSELSEQnCHSELSEQn - Channel select registers- Channel select registers

• RESULTnRESULTn - Adc result registers- Adc result registers

PROGRAM MEMORY ADDRESS FOR TRAINER PROGRAM MEMORY ADDRESS FOR TRAINER KITKIT

Starting

address

Ending

addressDescription

Memory

Type

0000 BFFFASSEMBLER, DISASSEMBLER, SERIAL MONITOR PROGRAM AREA

EEPROM

C000 FFFFUSER PROGRAM MEMORY AREA

RAM

LF2407 DATA MEMORYLF2407 DATA MEMORYTotal memory = 0000h – FFFFh (64KW)Total memory = 0000h – FFFFh (64KW)

Total no. pages = 200hTotal no. pages = 200h

Every page contains 80h locationsEvery page contains 80h locations

Page 0 = 0h * 80h = 0000 to 007FPage 0 = 0h * 80h = 0000 to 007F

Page 1 = 1h * 80h = 0080 to 00FFPage 1 = 1h * 80h = 0080 to 00FF

.. .. .. .. .. .. ..

.. .. .. .. .. .. ..

.. .. .. .. .. .. .. Page 100 = 100h * 80h = 8000 to 807FPage 100 = 100h * 80h = 8000 to 807F

Page 1FF = 1FFh * 80h = FF80 to FFFFPage 1FF = 1FFh * 80h = FF80 to FFFF

DATA MEMORY ADDRESS FOR TRAINER DATA MEMORY ADDRESS FOR TRAINER KITKIT

Starting

address

Ending

addressDescription

Memory

Type

0000 7FFF

8000 FFFF RAM

ON-CHIP RAM

USER DATA MEMORY AREA

RAM

ASSEMBLEY LANGUAGE PROGRAMSADDITION

.TEXT

.MMREGSSTART:

LDP #100HLACC 0HADD 1HSACL 2H

H: B H

Input:8000 – 33338001 – 2222

Output:8002 - 5555

.TEXT

.MMREGSSTART:

LDP #100HLACC #3333HADD #2222HSACL 0H

H: B H

Output:8000 – 5555

SIMPLE PROGRAM FOR PWM GENERATIONSIMPLE PROGRAM FOR PWM GENERATION .include 2407regs.h.include 2407regs.h.text.textStart:Start:

LDPLDP #232#232SPLKSPLK #2000,T1PR#2000,T1PRSPLKSPLK #1000,T1CMPR#1000,T1CMPRSPLKSPLK #1000,T2CMPR#1000,T2CMPRSPLKSPLK #1000,T3CMPR#1000,T3CMPRSPLKSPLK #0999H,ACTRA#0999H,ACTRASPLKSPLK #8200H,COMCONA#8200H,COMCONASPLKSPLK #0000,T1CNT#0000,T1CNTSPLKSPLK #0000,T2CNT#0000,T2CNTSPLKSPLK #0000,T3CNT#0000,T3CNTSPLKSPLK #0802H,T1CON#0802H,T1CONSPLKSPLK #0842H,T1CON#0842H,T1CON

ENDEND BB ENDEND