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joal 2005 HT:1 Em3 Custom Designed Integrated Circuits
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Course Introduction Kundanpassade kretsar
Custom Designed Integrated CircuitsLecturer/Examinator:Alf Johansson Senior Lecturer, Embedded Systems
[email protected] 0705-43 98 44 / 15 74 78
All documents are stored in the PingPong activity:
Custom Designed Integrated Circuits 5p –HT05
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Course introductionKurslitteratur på svenska:VHDL för konstruktion.Lennart Lindh, Stefan Sjöholm. Studentlitteratur (ISBN 9144024711)
Litterature in English:VHDL for designers. Stefan Sjoholm/Lennart LindhPrentice Hall (ISBN 0134734149)
Reference book: Designers Guide To VhdlAshenden, PeterElsevier, UK, 2000 (ISBN 1558606742).
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Course Introduction
ScheduleLectures/exercises(2p): Tuesdays 15– 17
Wednesdays 8 - 10
Labs/Projects(1+2p): Wednesdays 13 – 17
ExaminationWritten exam + labs + project.
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1. Course introduction. Custom Designed Integrated Circuits.Week Lecture Ref Exercise Lab
1/W35 Introduction to ASIC.Concurrent VHDL
1/W35 Concurrent VHDL Chap1-3
Chap 3: 3, 4, 5, 10, 13, 14
Lab 1, Concurrent VHDL
2/W36 Sequential VHDL Chap 4 Chap 4: all Lab 2, Sequential VHDL
3/W37 Library, structural VHDL. State machines FSM
Chap 5, 6, 9 Chap 5: 4,7,8,9Chap 6: 1,2,6Chap 9: 1,2,4,5,9
Lab 3State machines
4/W38 Test benches Chap 8,10,11,12 Chap 8: 1,3,4,5 Lab 4Test benches
5/W39 Coding style. Design hints. Project example.Introduction to project..
Chap 13,14 Project
6/W40 VHDL-AMS, Design tools ASIC technology Test
Chap 15,16 Project
7/W41 Behavioural synthesis. SoC Chap 17 Project
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Customer Integrated Circuits
ASIC
Gate Array Std Cell Full Custom
Field programmable
FPGA PLD
CPLD PLD
FPGA = Field Programmable Gate Array. >1 milj gates!
PLD = Programmable Logic DeviceCPLD = Complex PLD. <10k gates
ASIC = Application Specific Integrated CircuitGate Array = Prefabricated wafer with logic+added
interconnections (metal layers). Vol > 10kStandard Cell = Library with components (e.g. gates,
multiplexors, flip-flops). Precompiled on transistor level. Vol >100k
Full Custom = Transistor level design. Used for analogue circuits.
SOC = System On Chip (processors, memories, logic)
SOC SOC
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Motivation for HDL (Hardware Description Language)
• Standardised HDL enables use of IPs, Intellectual Properties.
• More and more complex circuits require efficient design and verification methods.
• Technology independent. We have a rapid change in technology.• Design on a higher abstraction level and automatic
”codegeneration” (synthesis).
• Using a HDL for design is as natural as using C or ADA instead of assembler.
• Design and verification/test in one environment (language).
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VHDLVHSIC Hardware Description Language
(VHSIC=Very High Speed Integrated Circuit)
• Initiated by DoD (Department of Defense) early 1980s
• Specified by Intermetrics (they also specified ADA)
• Standard IEEE 1076-1987 (VHDL-87, VHDL-93, VHDL-2000, VHDL-2002)
• Standard language for specification and modelling
• Subset of language for synthesis
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Why use VHDL ?
• Technology independent => Technologies change during the life time of electronic products. Use automatic tools to implement new technologies.
• Modifiability => Easy to read, hierarchical and structured.
• Hierarchical => Structural VHDL (block diagrams).
• Abstraction levels => Behaviour, RTL and gate level.
• Supports concurrent and sequential language constructions (C only sequential).
• Reuse of designs and part of designs => components.
• Can be verified in a (technology independent) simulator.
• De facto standard for design (synthesis) => Synopsys.
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Development flow
Development phase
Result Documentation
Analysis Specification What has to be done?
Design VHDL code How?
Technology mapping
Netlist How?
Prototyping Prototype What is the result?
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History
Verification with ”black box” prototype
1
Signal generator Prototype Oscilloscope
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History
Verification with a schematics in the computer
2
Input signal file ”signal gener.”
Computer model. Netlist prototype.
Output signal file ”logic analyser”
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History
Synthesis to gates and flip-flops
3
Prototype model
SynthesisVHDL
Input signal file ”signal gener.”
Output signal file ”logic analyser”
Netlist
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History
Verification with a testbench (A and B) in the computer
4
VHDL component ”signal gener.”
VHDL component ”logic analyser”
Computer VHDL ”prototype”A B
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Synthesis• Synthesis = Translate VHDL to logic
• Logic synthesis = Translate Boolean functions to gates
•RTL synthesis (Register Transfer Level) = Logic synthesis + sequential constructs to gates and flip flops. All clocking defined by designer.
• Behavioral synthesis = reuse of components (e.g. a common multiplier). Clocking defined by synthesis tools.
process(sel,a,b)begin if sel=’1’ then c<=b; else c<=a; end if;end process;
&
1
&
1
a
b
selc
ca
b
sel
0
1
Synthesis Technology mapping
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VHDL abstraction levels
Higher abstraction levels conceal details.
SystemFunctional level
Behavioural level
Computer model
information
RTL level
clk
res
&
&&
Logic level
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Design domains and abstraction levels in Y ChartsBehavioral domain
Structural domain
Physical domain
Algorithms
RTL
Boolean
Transistor functions
Transistor layout
Transistors
BehavioralProcessors, mem
Registers, ALUs
Gates, Flip-Flops
Cells, modules
Chips, ASICs
Boards, MCM
Functional design
Physical design of chips
More details when we move towards center
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Design Process Representation in Y- ChartBehavioral domain
Structural domain
Physical domain
Algorithms
RTL (VHDL)
Boolean
Transistor functions
Transistor layout
Transistors
Behavioral (VHDL)Processors, mem
Registers, ALUs
Gates, Flip-Flops, muxes, adders
Cells, modules
Chips, ASICs
Boards, MCM
Synthesis
Implementation(technology mapping)
Gates, FF
netlist
e.g. bit file
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Comp1
VHDL abstraction levels and hierarchies
• Behavioural level: Reuse of instantiated components. No architecture is required. Research area. Few tools on market.
• RTL (Register Transfer Level): Logic + sequential circuits like registers andstate machines. At RTL all registers are defined in VHDL code.
• Logic level: Boolean algebra or gate network.
• Compare abstraction levels with programming languages: UML – C – assembler –machine code
Abstraction levels:
• Complexity not reduced but easier to understand.
Design hierarchies:Comp21 Comp22
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VHDL• VHDL components: Central concept in VHDL. The components can be
stored in libraries. A component can be a simple gate or a complex system like a microprocessor. The internal behavior can be concealed from the designer (black box) and only the component interface is shown.
• Entity: The entity declaration defines the interface between an entity and the environment. The entity name is the same as the component name.
• Architecture: An architecture defines the body of a component entity and specifies the behavior between inputs and outputs. An architecture is tied to one entity and one entity can have several architectures.
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entity and_gate is
end;
port (a,b: in std_logic, c: out std_logic);
-- ****************************************-- My first VHDL program-- Kundanpassade kretsar HT 2001-- ****************************************
The entity describes the boarder of a
component
Component name: and_gate
port describes the input and output signals of a
component.a and b are input signals
c is an output signalstd_logic describes
signal type
Two hyphens -- indicate start of a comment for the rest of a
line
architecture rtl of and_gate isbegin
end rtl;
c <= a and b;
architecture describes what shall be done Signal c is assigned the boolean
and of a and b
library ieee;use std_logic_1164.all;use std_logic_unsigned.all;
library for signal types
rtl is an arbitrary name of an architecture
Let’s make a very simple VHDL
program
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VHDL Syntax
Syntax (VHDL-93)
entity <identifier_name> isport ([signal] <identifier>:[mode]<type_indicator>; [signal] <identifier>:[mode]<type_indicator>; …… [signal] <identifier>:[mode]<type_indicator>);end [entity] <identifier_name>;
<mode> = in, out, inout, bufferin: input signal to componentout: output signal from componentinout: bidirectional signalbuffer: output signal that can be read (out signal can’t be read!!!)
Exampleentity ex is
port (a,b: in std_logic; c: out std_logic);
end ex;
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-- Exampleentity ex isport (a,b: in std_logic; c: out std_logic);end ex;
VHDL Syntax
Syntax (VHDL-93)
architecture <architecture_name> of <entity_identifier> is[<architecture_declarative_part>]begin <architecture_statement_part>end [architecture] <architecture_name>;
architecture rtl of ex isbegin c <= not (a and b);end rtl;
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Logical operators
not inverted a<=not b;and a<=b and c;nand a<=b nand c a<=not(b and c);or a<=b or c;nor a<=not(b or c);xor a<=not((b and c) or (not b and not c));xnor a<=(b and c) or (not b and not c); (VHDL –93)
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The three faces of VHDLVHDL has three different parts:
• Concurrent VHDL (Parallell VHDL)
• Sequential VHDL (Sekventiell VHDL)
• Structural VHDL (Strukturell VHDL)
Some constructs are only allowed in the concurrent part other constructs only in the sequential part. The syntax may differ in the different parts ( in order to show the differences).
The timing is different in concurrent and sequential VHDL
Concurrent
with xx select q<=a when ”00”, b when ”11, ’0’ when others;
Sequential
case xx is when ”00” => q<=a; when ”11” => q<=b; when others => q<=’0’;end case;
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Concurrent VHDL
Signal assignmentThink of signals as physical connections
Syntax (VHDL –93)
Signal assignment:<target_identifier>’<=’ <selected_expression>’;’
Syntax (VHDL –93)
Signal assignment with delay:<target_identifier>’<=’ <selected_expression> ’after’ 10 ’ns’ ’;’
The nature of hardware is parallel. A HDL must have features to describe the parallel behavior of hardware. In VHDL this is called ”concurrent VHDL”.
NB ”after” can’t be synthesised and is dismissed by synthesiser.
Examples: a<=’0’; a<=b after 10 ns; a<=b and c; a<=’0’, ’1’ after 20 ns, b after 30 ns;
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Concurrent VHDL. Delays• Inertial delay (tröghets): Default in VHDL. Spikes are not propagated (if ’after’ is used).
Often used in electronic component delays.
• Transport delay: Pulses are always propagated. Used for delay lines.
• Reject delay: Is used when spike filtering is not the same as the circuit delay (VHDL-93).
• Inertial delay is ignorded by synthesis tools. Transport delay will give errors (often).
10 20 30 40 50 60 70 [ns]
a b
a
b1 <= a inertial after 10 ns;b2 <= a transport after 10 ns;b3 <= a reject 4 ns inertial after 10 ns;
b1
b2
b3
10 20 30 40 50 60 70 80 [ns]
a
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Concurrent VHDL. Assignment order• Concurrency: Hardware is parallel in nature. VHDL has constructions for
concurrency (e.g C has not but SystemC has).
• Concurrent constructions in VHDL are executed concurrently and the order in which the code is written is irrelevant.
• Concurrent commands in VHDL are event-controlled.
architecture rtl of ex1 isbegin c <= b; b <= a;end rtl;
architecture rtl of ex2 isbegin b <= a; c <= b;end rtl;
cba
cba
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Concurrent VHDL. Delta time• Delta time is used for queuing up sequential events. Delta times are executed while the
simulation clock is stopped. When combinational logic has 0 ns delay the simulator counts up one delta time for each assignment. The delta time will count up until all signals are stable.
• What happens with the assignment: q <= not q; ??
10 20 30 40 50 60 70 [ns]
A
B
C D&A
B
D<= not C;C<=A and B;
10 20 30 40 50 60 70 [ns]
D
C
30 ns+2 delta 57 ns+2 delta
30 ns+1 delta 57 ns+1 delta
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Concurrent VHDL. When statement
Syntax
When statement:<target>’<=’ <expression> [after <expression>] when <condition> else <expression> [after <expression>];
Several when else lines can be used!
-- Examplearchitecture rtl of ex isbegin q<= a when data=”00” else b when data=”11” else c;end rtl;
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Concurrent VHDL. When statement
-- Example-- Useful when statement
architecture rtl of three_state isbegin dbus0<= data0 when enable=’1’ else ’Z’;end rtl;
enable
data dbus
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Concurrent VHDL. With statement
Syntax
With statement:with <expression> select <target>’<=’ <expression> when <choose>; <expression> when <choose>;
All possible <choices> must be enumerated!
Remaining choices can be collected in when others!
-- Examplearchitecture rtl of ex isbegin with data select q<=a when ”00”, b when ”11”, c when others;end rtl;
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Concurrent VHDL. Object, class and typeClass Object Typesignal a: std_logic;
Class• constant• variable• signal ”a wire”, time dependent
constant a: std_logic_vector(3 downto 0):= ”1111”;signal b: std_logic_vector(7 downto 0);variable c: std_logic;
TypeDatatypes to be used in this course:
• integer NB: Length is implementation dependent!Use range! signal my_int: integer range 0 to 255;
• std_ulogic• std_logic (resolved type of std_ulogic).
Signal driver and resolve function (read the book!!).
Std_ulogic/std_logic:
’U’ – uninitialized (start value=left)
’X’ – forcing unknown
’0’ – forcing 0
’1’ – forcing 1
’Z’ – high impedence
’W’ – weak unknown
’L’ – weak 0
’H’ – weak 1
’-’ – don’t care
Every signal assignment in concurrent VHDL will create a driver. Two or more assignments of the same signal require resolved types.
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Concurrent VHDL• Type declarations of std_logic_vector:
type std_logic_vector is array (natural range<>) of std_logic;
• Declaration.signal a_vect: std_logic_vector(7 downto 0); -- normal way to write with MSB to the leftsignal a_vect: std_logic_vector(0 to 7); -- LSB to the left
signal a_vect: std_logic_vector(7 downto 0);
a_vect<= ”10101010”; -- Note double quotation marks!
a_vect<= b_vect;
Slice of arraysignal a_vect: std_logic_vector(7 downto 0);signal b_vect: std_logic_vector(5 downto 0); -- length differs
a_vect(0)<= ’1’;
a_vect(0)<= b_vect(1);
a_vect(7 downto 1)<=a_vect(6 downto 0); --Left shift one step!
a_vect<=(1=>’0’, 4=>’0’, others =>’1’);
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Concurrent VHDL. Vector assignmentConcatinationsignal a_vect: std_logic_vector(7 downto 0);signal b_vect: std_logic_vector(5 downto 0); -- length differs
a_vect<=”00” & b_vect; -- add two msb
Aggregatesignal a_vect: std_logic_vector(7 downto 0);
a_vect<=(others=>’0’); -- a_vect>=”00000000”a_vect<=(1=>’0’, 4=>’0’, others =>’1’);
Bit string literals
a_vect<=B”11110000”; -- B”1111_0000” more readablea_vect<=X”FFA0”;
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Concurrent VHDL. OperatorsRelational operators= equal/= not equal< less than> greater than<= less than or equal>= greater than or equal
Can be used on integers and std_logic_vectors
= and /= can be used on all defined data types
Arithmetic operators+ addition- subtraction* multiplication/ divisionabs absolute valuerem remaindermod modulus** exponantiation
These operators are predefined for integer and time.
If std_logic_vector shall be used the operators must be defined in a package e.g. std_logic_unsigned.
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all
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Concurrent VHDL. Internal signal. Init values
Left-hand values
The default init value is the left-hand value in the value list.
e.g. for std_logic the init value is ’U’.
Init in entity or architecture (Not for synthesis)
entity ex isport(a: in std_logic:=’0’;
b: out std_logic);end;
architecture behv of ex issignal i1: std_logic:=’1’;signal i2,i3: std_logic:=’H’;signal i4: std_logic_vector(3 downto 0):=”0000”;
begin
……..end;
Internal signals
No in, out etc!
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Concurrent VHDL. Block statement
architecture behav of ex issignal a
beginaddr_decode: block
signal cs_b: std_logic;signal addr: std_logic_vector(3 downto 0);
begin……..
end block;end behav;
• The block statement can be used to make the text more readable.• The scope of signals that are declared in a block is the block.• Signals from a block can be loaded into the simulator as one unit.• The block statement is a concurrent statement.
Block declarations
scope
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Introduction to labexercises
VHDL source
Compiler/Simulator Synthesis
Place & Route
Load circuit
Xilinx CPLD/FPGA
Mentor Leonardo
Mentor HDesigner
Mentor Modelsim
Xilinx Foundation
Netlist (.edif)
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FPGAs in the future?• Miljons of gates. 10 miljon gates circuits soon available.
• Lower cost. Now 0,1 öre/gate.
• Soft IP (microcontrollers, DSPs, etc ) IP=Intellectual Properties.
• FPGAs with hard IP cores. E.g. microcontrollers and FPGA in one circuit (SOPC) .
• SOPC, System On Programmable Chip.
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Moore’s law
108
106
Moore’s law: The capacity ( e.g. # of gates) of integratedchips doubles every 18-20 months.
toolscircuits
gap
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VHDL Examples Ex 1.
Design a XOR-gate with AND and OR functions (entity xorgate) that has 2 inputs and one output. Use std_logic as signal type.
a
bQ
a b Q
0 0 0
1 0 1
0 1 1
1 1 0
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VHDL Examples Ex 2.
Design a multiplexor (entity MUX8) that has 8 inputs, 3 selection lines and 1 output. The output is three_state type. Use std_logic as signal type.
a0-a7 8
s0-s2 3
Q
s3-s0 Q (E=’1’) Q (E=’0’)
000 a0 Z
001 a1 Z
010 a2 Z
011 a3 Z
100 a4 Z
101 a5 Z
110 a6 Z
111 a7 Z
E
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VHDL Examples Ex 3.
Design an inverter (entity openc) that has an output as in the figure below. Use std_logic as signal type.
Q
a Q
0 1
1 0
a
Vdd
Vss