June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.

June 11, 2014 CLBv2, Vidyo

Peter JansweijerNikhefAmsterdamElectronics- Technology

1

KM3NeT CLBv2



PAR ERROR:◦ ERROR:Place:1398 - A clock IOB / BUFGCTRL clock component pair have

been found that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock IOB component <RESET> is placed at site <D11>. The corresponding BUFGCTRL component <ix18505z53357> is placed at site <BUFGCTRL_X0Y25>. The clock IO can use the fast path between the IOB and the Clock Buffer if the IOB is placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; >

PAR Error:

2



Cause: RESET is connected to a “N” type Single Region Clock Capable (SRCC) pin.

As the design grows, one needs to use the top & bottom part of the FPGA. Only “P” side pins can drive global clock nets.

We already had this issue for CLK20_VCXO◦ see slide 14:◦ http

://indico.cern.ch/event/286898/contribution/4/material/slides/0.pptx

Solution: Swap FPGA pins for NRESET and RESET (note: NRESET connects to “P”)

PAR Error:

3

http://indico.cern.ch/event/286898/contribution/4/material/slides/0.pptx





Vincent ran into memory limitations◦ always the same story with these memory hungry

software engineers… Increased from 88 Kbytes to 128 Kbytes

◦ BMM files for XST and Precision changed but nobody should have noticed this…

LM32_2nd Memory:

4



With higher TDC rates in rare conditions…

Missing either 1, 2 or 3, 16-bit words randomly

Checksum: “unchecked, not all data available”

UDP Length error:

5



Who is to blame?◦ TDC + StateMachine (unlikely)

It just forwards payload that will be counted by IPMUX

◦ IPMUX (unlikely) The correct length word (counted by IPMUX) is in the header

so IPMUX must have seen all data words…

◦ The interface between IPMUX and WR (maybe)◦ WR endpoint (maybe)

UDP Length error:



Test to hunt for the UDP Length error:

7

Added UDP Length checker. Verification signalling (to Oscilloscope):• Length Okay• Length Error

Test packet generator:16 x okay

0 x error



Test to hunt for the UDP Length error:

8

Only okay’s

0 triggers on errorConclusion:Up to the WRPC input all is okay!Focus on WRPC (endpoint)



Further points checked:

9

Input ep_tx_frames (= WR MAC) Input 1000basex-PCS Input PHY

All okay!? I must be doing something wrong…◦ Sorry… Got the wrong file updated.◦ => work in progress.



While hunting down the UDP Length error issue:

I had a simulation stall. IPMUX connects to the non empty input fifo

of the TDC channel and starts reading packet payload. It keeps connected (there is no other way) until it completes the payload transfer (i.e. EOD). When for some reason no EOD is generated (or it takes a while, i.e. one time slice) then it keeps waiting, effectively blocking other inputs.

Example case study:◦ Long time slice with no data IPMUX is connected to

TDC for the time slice duration◦ During this time AES data should be buffered

IPMUX arbitration

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Three parameters to optimize the dataflow:1. Proper setting for the packet size.

2. Buffer sizes (either the TDC/AES fifos or the IPMUX input fifo) can help optimize the dataflow.

3. The arbitration scheme. Now all channels are served equally so one has to wait for the other.

For the time being I see no problems but we should be aware of this behaviour!

IPMUX arbitration

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Tommaso proposed to have no TDC-UDP data packets if there is no TDC data in the Time Slice.

Do we want that behaviour?◦ If we don’t send data each Time Slice (even if it is

empty) then the DAQ cannot distinguish between data that is still in the pipeline or apparently the time slice was empty. => a timeout is needed.

◦ Sending an Time Slice packet that contains no TDC data at least tells the DAQ that it can continue with data processing. No timeout.

Empty Time Slice to DAQ?

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½ DOM electronics + readoutEMCClimateRate testGolden image

◦ Golden image reprogrammable itself? => Test!◦ SFP wave length shift

Test: unplug CLB Tx fiber and see if we can switch a LED on/off (i.e. without upstream communication)

PRR

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Pause frame implementation◦ Gave some feedback to Emilio @ TIPP2014◦ Feedback 7-Sols to WR community?

Calibration. Yes/no WR in the DOMs◦ WR very handy for Dark Room Calibartion!◦ Also handy for Dark Room Calibartion: Make PPS

signal available with an assembled DOM (RF? Via Nano-Beacon?)

Other topics that keep me busy

14

DU-Base

WR-Calibrato

r

Measure strings “constant” delays(to be considered as delta Rx for each of the DOMs)



Backup slides

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Zoom into WRPC:

16

Added UDP Length checker. Verification signalling (to Oscilloscope):• Length Okay• Length Error

Again:Only okay’s

0 triggers on error



Zoom into WRPC endpoint:

17

okay

Again:Only okay’s

0 triggers on error

Ep_t

x_f

ram

er

snktxpcs_fabphy_tx

Wr_

gtx

_ph

y_k

inte

x7

okaye

p_t

x_p

cs_1

6bit

ep_1000basex_pcs

serdes_tx pcs_fab

errors

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June 11, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1.

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