June, 2010 High Speed IO Buffer Modeling for Networking … · 2016. 3. 21. · High Speed IO...

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

FTF-NET-F0708

High Speed IO Buffer Modeling for Networking Processors

June, 2010

Jon BurnettHardware Enablement Team – Signal Integrity

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 22

Objectives

►Examine IO buffer and interconnect modeling issues for networking processors

►Review high speed bus modeling considerations• DDR• SerDes

►Review IO buffer modeling details

►Examine interaction between IO buffers and interconnects

• Note how they relate to hardware specifications• Note how they produce information useful

in timing and noise budgets


►Review interconnect – Typically PCB

►DDR Bus

►SerDes Bus

►LVCMOS Bus

►IO buffer modeling considerations• DDR: driver strength, ODT• SerDes: De-emphasis, equalization, IBIS-AMI

Agenda


Predicting Effect of the Interconnect

How to calculate the system effects when interfacing with our devices?

How is the digital design implemented in the physical world (typically printed circuit board)?

Drivers interact with interconnect►Driver impedance►Driver edge rate►De-emphasis/equalization

Receivers interact with interconnect and effect driver►Capacitive load ►Receiver clamping ►Termination►Equalization

4


Board Layout Example: DDR Memory

CPU

DDR

How to predict behavior of the CPU driving the DDR2/3 DIMMs?

► Driver: CPU • Drive strength

► Interconnect:• Package• PCB traces• DIMM sockets• DIMM routing

► Receiver: Memory• ODT


Board Layout Example: SerDes

Will the PCBinterconnectdegrade data eyefrom CPU toconnector?

►Driver: CPU • Equalization

► Interconnect:• Package• PCB traces/vias• Connector• Crosstalk

►Receiver: Terminated

PEX Slot

CPU


IO Buffer Simulation

►Extract from waveforms: • Eye width• Cross-point voltage• Edge rate• Propagation delay• Skew between signals• Crosstalk• ISI effects


Simplified IO Buffer Model

►Linear IO buffer model• Simplify IO buffer to “equivalent” resistive value

►Resistive driver impedance value application• Can be used in traditional transmission line lattice diagram analysis

Initial Voltage Step: Vstep = Vswing * Zo/(Zo + RD)

Reflection Coefficient:ρ= (Zrec – Zo)/(Zrec + Zo)

Driver

Receiver

Driver Receiver


Hardware Specs: IO Buffer Drive Strength

►Some hardware specs include IO buffer drive strength targets►A separate model description is needed for each “driver type” listed

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLinkand VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc. 11

SerDes Modeling

11


PCI Express® – Signaling

►Differential signaling• Reduced swing• Lower crosstalk• Improved EMI• Zdiff = 100 ohms +/- 20%, Z0 = 60 ohms +/- 15% recommended

►AC coupled differential pairs• Isolates DC voltage component from Tx device to Rx device

Allows different reference planes at each device on a link• 75nF – 200nF, placed near device transmitter outputs

►Terminations on-die to 100 ohms differential

Presenter

Presentation Notes

Diff pair signal benefits Minimize reflections Lower single ended impedance tends to improve performance (per simulation data) OK, so why would you want to AC-couple a signal? (1) To change the DC bias level when interconnecting logic families with different switching thresholds, or (2) To provide a removable interface that may be shorted to ground without damaging the output drivers, or (3) When combined with differential signaling and transformer coupling, to connect boxes without requiring any DC connection between the two product chassis. Why does the blocking cap have to be located at or near the TX side? �With a connector and plug-in card, there needs to be some convention as to which card contains the AC coupling cap. PCI SIG picked near the transmitter to avoid confusion. So if there is a plug-in card, the AC caps are located on the plug-in card for the plug-in card's TX to motherboard RX path. What happens if the blocking cap value is outside of the recommended range (too high a value)?�Depends on how out-of-spec it is. If it gets too large, then the receiver detect circuitry will sense that there is no device at the other end of the link and the link will never train. Too low value will have the same effect for the same reason.


PCI Express – Key Electrical Parameters

►Loss• Insertion loss• Return loss

►Jitter• Random jitter (Rj)• Deterministic jitter (Dj)

Rx SpecMin Eye

Tx SpecMin Eye

InterconnectLoss < 13.2 dBJitter < 0.35 UI

800 mV

0.75 UI

0.4 UI

175 mV

•1 UI = 400 ps•Tx eye shown without de-emphasis

Presenter

Presentation Notes

Introduce KEY parameters in a SERDES Interconnect Introduce TX specs Interconnect specs RX specs Concept of “Mask” These are mimimum values RETRUN LOSS – due to energy reflected due to impedance mismatch also vias and connectors etc Insertion Loss – dielectric material etc Random Jitter- Heating effects, power supply Deterministic Jitter- crosstalk, emi, ISI


SerDes – Intersymbol Interference (ISI) & De-emphasis

Total loss of eye here

Rx signal without de-emphasis

Eye is now open

Rx signal with de-

emphasis

Tx signal withde-emphasis

► ISI: Signal transitions start at different voltage levels depending on their previous signal state

►De-emphasis: Attenuation of the voltage level at the transmitter of all consecutive bits of the same signal state except the first

Presenter

Presentation Notes

Notice change in slope of transition from TX to RX Note: De-Emphasis occurs only in non-T-bits Think of it as a “pre-leveling” of the signal to get ready for an acceptable transition in the coming bit to make the eye diagram as open as possible


SERDES Interconnect Sources of Loss

►The primary interconnect for NMG SERDES busses are printed circuit boards (PCBs).

► Insertion Loss (S11, S21):• The PCB dielectric materials and traces have losses that increase with

the frequency of the signal. As the SERDES bus speeds increase, the PCB losses become a larger factor in signal degradation.

►Return Loss (S11, S22):• Signal losses are also caused by mismatches in impedance.

Impedance mismatches occur in packages, PCB traces, vias, connectors, and sockets.

α o f / twtw = trace width(worse with narrow traces)

Frequency Dependent Skin Effect Loss

α = 2.3 (f ) tan(θ) er

tan(θ) = loss tangent, (better with low loss tangent)

Frequency Dependent Dielectric Loss


SerDes – Ways to Mitigate Loss and Jitter

►Trace width• Use wider traces

(+) Improves skin effect loss(+) No increase in material cost(-) Uses more routing area(-) Increases PCB thickness to maintain impedance targetsEx: ½ oz. copper stripline, Zdiff = 100 ohms

– 5 mil width / 6 mil air gap yields 1 db loss per 10.8 inches– 8 mil width / 14 mil air gap yields 1 db loss per 15.0 inches

►Vias• Use blind/buried vias• Use via-in-pad

(+) Smaller via geometry lower parasitics• Backdrill vias with stubs eliminates signal reflections at via stub


SerDes – Ways to Mitigate Loss and Jitter

taupe colored areas are cutouts in GND plane

►PCB materials• Use “high-speed” FR4

(+) Lower er lowers dielectric loss(+) Lower loss tangent lowers dielectric loss

Loss tangent can be cut in half with modified FR4 materials

(-) can cost 2x to 5x of standard FR4

• Use “smooth” copper(+) Lower dielectric loss(-) Caution! Peel strength is reduced

►AC coupling caps near Tx for PCI Express, near Rx for SRIO• Use smaller body style (0402 recommended for most designs)

(+) 0201 pads reduce parasitic capacitance by 70% over 0402 pads(-) 0201 assembly and rework more challenging

• Cutout reference planes (GND) underneath capacitor pads


PCI Express – Simulation Example

Type stripline

ConnectorAC Caps

0.1 uF 0201

stripline

System Card Add-in CardRiser Card

stripline

PCI Express midbus probe

Length 0.7” 6.1” 0.8” 6.7”0.6” 0.6”3.1”

Tx

0.1” via

stubs

T width Zdiff

4mil100 ohms

6mil100 ohms

stripline0.2”

4mil100 ohms

6mil100 ohms

ustrip5.2”

8mil100 ohms

ustrip8mil

100 ohms

ustrip8mil

100 ohms

Thru via (no stub)Thru via (0.1 stub)Backdrilled via (no stub)

SMTConnector

Rx

Total Length = 24 in. !! Will stubs at Rx be ok?

Presenter

Presentation Notes

24" is what we could achieve for PCIe 1.0; 20" is key parameter for PCIe2.0.


PCI Express – Simulation Example

0.4 UI

175mV

Rx SpecMin Eye


PCI Express – Rx Data Eye

Rx data eye: 24 inch path through two connectors


Next Generation PCI Express 2.0

►PCI Express 2.0• Double the data rate of PCIe 1.x – 5 GT/s

• AC parameters and measurements redefinedJitter budget

Insertion loss

• Backwards compatible with PCIe 1.x

• “Short reach” <= 20” achievable with 1.x routing guidelines and materials

• “Long reach” >20” difficultRequires one or more of the following:

– Improved PCB materials (not FR4)

– Backdrilling of via stubs

– Improved (higher speed) connectors

Presenter

Presentation Notes

PCIe2 goal was to double the throughput while maintaining the same physical interconnect (PCB materials and topologies, connectors). The compromise comes in the total length able to run, and more detailed breakout of jitter budget and loss requirements. Total jitter allowed is the same percentage of the UI– which means the actual amount allowed for Gen2 is cut in half! Loss allowed is increased for Gen2 due to additional losses in the media at the higher data rate. PCIe2 specs are designed to minimize the amount of guardbanding that Gen1 employed. “Upon power-up, all 5.0 GT/s devices must initially operate in the 2.5 GT/s mode, and the system must negotiate to the higher bit rate, making sure that both Transmitter and Receiver are 5.0 GT/s compatible, before switching to the 5.0 GT/s data rate.” [PCIe2 Base Spec, Section 4.3.1] 2.5 GT/s is Not a Subset of 5.0 GT/s !!!!! Both 2.5 and 5.0 specs must be met for Gen2. Loss in long channels tend to be dominated by insertion loss and crosstalk, while short channels tend to be dominated by impedance discontinuities.


PCI Express 1.1 vs. 2.0

PCIe (Gen1) PCIe2 (Gen2)

Data rate 2.5 GT/s 5.0 GT/s

Unit interval 400 ps ± 300ppm 200 ps ± 300ppm

Tx min voltage 800 mV p-p 800 mV p-p

Rx min voltage 175 mV p-p 120 mV p-p

Jitter: Tj @ receiver 0.6 UI (240 ps) 0.6 UI (120ps)

REFCLK jitter 150 ps (cyc-cyc)108 ps Jphase,p-p @ BER=10-12

150 ps (cyc-cyc)3.1 ps rms Jrnd

Presenter

Presentation Notes

These are the major key differences only. Refer to Gen1-Gen2_parameter_compare.pps for more complete list of spec differences between Gen1 and Gen2 PCI Express. Jitter specs are redefined (subdivided into four explicit areas: Transmitter, Receiver, channel, and REFCLK) to minimize guardbanding that existed in Gen1.


SERDES IO Buffer Modeling Related to Loss

► IO Buffer modeling is critical to predicting behavior of the SERDES channel.

• Modeling return loss: The IO buffer model and the detailed interconnect model will predict the reflections and effects of return loss.

• Modeling insertion loss: The IO buffer model will provide an appropriate edge rate into the interconnect model. The interconnect model will react to the frequency components in the edge rate to predict the effect of the frequency dependent losses of the interconnect.

RX SpecMin Eye

TX SpecMin Eye

InterconnectLoss < 13.2 dBJitter < 0.35 UI

800 mV

0.75 UI0.4 UI

175 mV

PCI Express Loss Budget


SerDes IO Buffer Modeling Example

►Review eye diagrams for jitter, eye opening, compliance mask


SerDes Tx IBIS: Use of Driver Schedule (Main, Boost)

[Driver Schedule]| Model_name Rise_on_dly Rise_off_dly Fall_on_dly Fall_off_dlytx_d66011_v11_main 0.0ns NA 0.0ns NAtx_d66011_v11_boost NA 0.400ns NA 0.400ns


SerDes Tx IBIS: De-emphasis at Eye and Transient V vs. T Plot


SerDes Tx IBIS: Tx and Rx Nodes with TL Load


SerDes Tx IBIS: At Receiver through Transmission Line


IO Buffer Modeling Using New Techniques: IBIS-AMI

► De-emphasis at the Tx can be modeled in SPICE and “standard” IBIS, but equalization at the Rx cannot be modeled effectively in SPICE and IBIS. The Rx equalization is not an analog, SPICE-based extraction based on IO buffer characteristics.

► A new means is needed to model the Rx equalization. The leading candidate for this task is the IBIS-AMI format.

► IBIS-AMI:• AMI: Algorithmic Modeling Interface

► AMI uses compiled DLL files to contain algorithmic modeling details• Uses internal models in languages such as Matlab, Verilog • Hides details in compiled DLL (confidentiality maintained)• Users can not see the model or review the data, as in standard IBIS

Documentation and test cases needed to enable use of models

► AMI models are useful for statistical based channel simulations.• Works with the impulse response of the channel

29


TXPackage

Interconnect (socket, vias,

PCB, AC Caps)

RXPackage

TX RX

Probe Here

SERDES Equalization – TX based


SerDes 1.25 Gbps –Tx No De-emphasis, Rx No Equalization

448 mV

712 ps (800 ps bit period)


SerDes 2.5 Gbps –Tx No De-emphasis and 3.5 dB De-emphasis, Rx No Equalization

278 mV


369 mV


2.5 Gbps, Tx no de-emphasis 2.5 Gbps, Tx 3.5dB de-emphasis


SerDes 5 Gbps –Tx 3.5 dB and 6 dB De-emphasis, Rx No Equalization

116 mV


153 mV


5 Gbps, Tx 3.5 dB de-emphasis 5 Gbps, Tx 6dB de-emphasis


SERDES Equalization – TX & RX based

TXPackage

Interconnect (socket, vias,

PCB, AC Caps)

RXPackage

TX RX

Left Eye,Probe Here: Before RX EQ

Right Eye,Probe Here:After RX EQ


SerDes 8 Gbps –Tx 6 dB De-emphasis, Rx No Equalization

35

Rx at internal node (post Rx EQ circuit)

Rx pre EQ circuit




36

SerDes 8 Gbps –Tx 6dB De-emphasis, Rx FFE Equalization

181 mV

Rx pre EQ circuit


SerDes 8 Gbps –Tx 6dB De-emphasis, Rx DFE Equalization

97 mV



Rx pre EQ circuit


DDR Bus Modeling

38


DDR Bus Overview

► DDR traits (track evolution of DDR1, DDR2, DDR3)

►Consider DDR bus domains• Clock, address, command• Data strobe, data• Clock, data strobe

► Simulation details related to DDR bus domains


DDR SDRAM Highlights and Comparison

Feature/Category DDR1 DDR2 DDR3

Package TSOP BGA only BGA only

Densities 128 Mb -1 Gb 256 Mb – 4 Gb 512 Mb -8 Gb

Voltage 2.5V Core2.5V I/O

1.8V Core1.8V I/O

1.5V Core1.5V I/O

I/O Signaling SSTL_2 SSTL_18 SSTL_15

Internal Memory Banks 4 4 to 8 8

Data Rate 200-400 Mbps 400–800 Mbps 800–1600 Mbps

Termination No ODT: Motherboard termination to

VTT for all signals

ODT: On-die termination for data group. VTT

termination for address, command, and control

ODT: On-die termination for data group. VTT

termination for address, command, and control

Data Strobes Single Ended Differential or single Differential

Presenter

Presentation Notes

Package: Note moving from TSOP to BGA Lower Parastics: verify ____________ Better PG pattern: verify ____________ Voltage: Can see lower supply voltage and lower supply voltage Rates: 800-1600 Mbps - Some IBIS models show 2133 Vtt Termination DDR1: Series term, Vtt term (DQ), MA DDR2: ODT on DQ, MA: - DDR3: ODT on DQ, MA/MCK Vtt on DIMM Greater Densities: Up to 8 Gb on DDR3: verify ______________ Banks: Up to 8: Verify __________________ Data Strobes: Differential on DDR3 Prior: Lower Voltage swing; Higher Performance; Additional ODT settings


Key DDR3 Memory Improvements and Additions

►Lower signaling standard

► Improved device pinout

►Fly-by architecture

►Write leveling

►Driver calibration

41

Presenter

Presentation Notes

Lower Swing: 1.5V DDR3 Power Reduction 30% Pinout: Power Distribution Fly-By: Used on Unidirectional, heavily loaded signals Write leveling new for DDR3 not supported by DDR2 memories Dynamic ODT for Writes to Memory - Better ODT control to improve eyes as data is written to slot 1 vs slot 2 Driver Cal: - Keep driver impedance values close to target values SDRAM device Reset DIMM address mirroring


DDR3 Signaling – Example SSTL-1.5

0.850V

0.765V0.750V0.735V

0.925V

VDDQ (1.5V nominal)

VSSQ

Transmitter

Receiver

VREF + AC NoiseVREF + DC Error

VREF - DC ErrorVREF - AC Noise

0.650V

0.575V

VOL (MAX)

VOH(MIN)

VIL

VIH

VIHAC

AC

VILDC

DC

Presenter

Presentation Notes

Look at Voltage Levels: Gvdd: 2.5, 1.8, 1.5 Vref (1/2 GVdd): 1.25, 0.9, 0.75 Vin: DDR1 DDR2 DDR3 Vinac: - DDR1 - DDR2 - DDR3 - DDR3 1333 The AC values are chosen as the levels at which the SSTL receiver (DDR during writes or the PQIII during reads) must meet its timing requirements (..for setup and holds) . The DC values are chosen are chosen such that the final logic state is defined. In general, the DRAM will start to switch to the new logic level when the input signal transitions through the target DC level and it will latch when the input signal crosses through the final AC input level. Once the logic level has been latched, it will remain latched until the input signal transitions back through the DC level. This enables the interface to accommodate a certain amount of ringing which is a culprit on large address/data buses. If we look at the signaling standard… its very similar to previous SSTL standards used on DDR1 and DDR2 …. Except its been scaled down… …. As before…. SSTL1.5 it defines a reference voltage… called VREF. This voltage is leveraged by the SSTL receiver as the center of the voltage swing. For DDR3 chips, VREF is established at 0.75V… which is half of the VDDQ rail powering the chips. In addition, the standard defines both ac and dc input signal levels…. enabling the design of high gain, differential receivers. DDR3 voltage levels for higher speeds


Improved Pinout for DDR3 Memory

►Improved power delivery• More power and ground balls

►Improved signal quality• Better power and ground

distribution• And better signal referencing

►Fully populated ball grid• Stronger reliability

►Improved pin placement• Less pin skew• Tighter timing leaving chip

Presenter

Presentation Notes

More Power/Ground pins red circle - Better PG Distribution, reduce loop inductances? Tighter byte lane grouping blue box Any Power Dist Papers?


DDR3 Clock, Address, Command: Fly-by Routing Topology

►Introduction of “fly-by” architecture • Address, command, control & clocks• Improved signal integrity, enabling higher speeds• On-module termination

Controller

VTTFly by routing of clk, command and ctrl

Controller

Matched tree routing of clk command and ctrl

DDR2 DIMM

DDR3 DIMM

Presenter

Presentation Notes

Unbuffered DIMMs


Fly-by Skew Across All Receivers

This illustrates the skew created by DDR3 fly-by routing

Presenter

Presentation Notes

Up to 1.5 ns skew At 800MT/s At DRAM Device Per byte lane x8 devices


DDR Data Bus

► Data bus: Double data rate signaling

►Tight timing budget – count the 10s of pico-seconds

►Look at timing budget items• Inter-symbol interference• Receiver loading• Trace length matching• Crosstalk


Examine Crosstalk Effects on Data Eye (Tight Spacing)


Examine Crosstalk Effects on Data Eye (Wider Spacing)


Crosstalk Effects on Data Eye (Compare Spacing)


Crosstalk Effects on Data Eye (Driver Strength) – 1


Crosstalk Effects on Data Eye (Driver Strength) – 2


Interconnect Issue:Stubs and Topology Considerations

53


IO Buffer Modeling Example

►Examine effect of edge on stubs in the topology


A Few Words on IO Buffer Modeling

57


IBIS: Ties to IO Buffer Data in Hardware Specs

[Model] pci_25ohm

Model_type I/O

|

Vinl = 0.80V

Vinh = 2.00V

Vmeas = 1.65V

Rref = 50

Vref = 1.65V

|

C_comp 2.500pF 2.300pF 2.700pF

|

| TYP MIN MAX

[Temperature Range] 25.0 105.0 0.0

[Voltage Range] 3.300V 3.135V 3.465V

Hardware Spec:Driver ImpedanceBuffer Type

Vin Specs

Test Load

Simulated/Measured

Min & Max Temp

Min & Max Voltage


Overshoot Specs Referenced to GVDD, LVDD, OVDD

[Model Spec]| subparameter typ min maxS_overshoot_high 3.300 3.1185 3.8115 | Use 5%S_overshoot_low -300m -300m -300m | Use Gnd – 0.3VD_overshoot_high 3.960 3.564 4.356 | Use 20%D_overshoot_low -700m -700m -700m | Use Gnd – 0.7VD_overshoot_time 0.800n 0.800n 0.800n | Use 125 MHz


Information to Include in Topology Description

► Driver and receivers: • Model• PVT setting (min,typ,max)• Which signal or pin on device

► PCB load:• Trace segments: Length and impedance• Termination (if any, or note if termination is an option)• Vias for higher speed

► Note probing locations (die or pin or via)► Note frequency of operation

60


IBIS Development and Checking Procedure

►IBIS checker status• IBIS checked using 3.2, 4.x, 5.0 checkers• Visual IBIS inspection• Warnings reviewed

►Simulation comparison• IBIS-based simulations vs. internal SPICE

►Measured IBIS• Pilot program to use tester-based IBIS data • Allows IBIS to track actual silicon and process updates


IBIS Planning Spreadsheet


MPC8548 IBIS Planning Spreadsheet (I)


Measured vs. Simulated Pulldown Data

►Blue is measured, gray is simulated

64

Simulated vs Measured Pulldown Data

-40

-30

-20

-10

0

10

20

30

40

50

-1 1 2 3 4

Volts

mA

Series1 Series2


Comments on IBIS

► IO buffer modeling is a valuable process to predict behavior of the interconnect in high speed buses

► IO buffer modeling using IBIS provides fast, accurate simulations

► IBIS is a “neutral” format that is used across multiple simulators

►As IBIS simulators evolve and link to timing utilities, more hardware spec-based data is needed. In the past, getting the electrical data right was sufficient. Now, more parameters are requested and required by system signal integrity and timing simulators.

► IBIS quality processes are aiding in giving a baseline measure to review and document IBIS data


Summary

►SerDes Simulation

►New Process – IBIS AMI

►DDR Simulation

►IO Buffer Modeling


References

►PCI Sig

►Serial RapidIO

►JEDEC DDR

►Freescale DDR app notes

►Micron DDR app notes

►IBIS info, including AMI info

TMFreescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, C-Ware, mobileGT, PowerQUICC, StarCore, and Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMARTMOS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2010 Freescale Semiconductor, Inc.

Backup Slides


►Insertion Loss• Signal amplitude attenuation in the forward signal direction

(from Tx to Rx)

• Contributors to loss

KEY consistent L0/C0 along the path

Package

PCB traces and vias

AC coupling caps (parasitics)

Connectors

PCB dielectric variations (FR4 fabric weave)

Data pattern (intersymbol interference)

SerDes – Loss

Z0 =C0

L0

Ideal (lossless) transmission line

Presenter

Presentation Notes

Physical features -- causes of loss


PCI Express® – Signaling

►Differential signaling• Lower crosstalk• Improved EMI• Zdiff = 100 ohms +/- 20%, Z0 = 60 ohms +/- 15% recommended

►AC coupled differential pairs• Isolates DC voltage component from Tx device to Rx device

Allows different reference planes at each device on a link• 75nF – 200nF, placed near device transmitter outputs

►Terminations on-die to 100 ohms differential►8b/10b data encoding (required)

• No more than five bits in a row are transmitted at the same state – limits “dead time” and allows AC coupling scheme

Presenter

Presentation Notes

Diff pair signal benefits Minimize reflections Lower single ended impedance tends to improve performance (per simulation data) OK, so why would you want to AC-couple a signal? (1) To change the DC bias level when interconnecting logic families with different switching thresholds, or (2) To provide a removable interface that may be shorted to ground without damaging the output drivers, or (3) When combined with differential signaling and transformer coupling, to connect boxes without requiring any DC connection between the two product chassis. Why does the blocking cap have to be located at or near the TX side? �With a connector and plug-in card, there needs to be some convention as to which card contains the AC coupling cap. PCI SIG picked near the transmitter to avoid confusion. So if there is a plug-in card, the AC caps are located on the plug-in card for the plug-in card's TX to motherboard RX path. What happens if the blocking cap value is outside of the recommended range (too high a value)?�Depends on how out-of-spec it is. If it gets too large, then the receiver detect circuitry will sense that there is no device at the other end of the link and the link will never train. Too low value will have the same effect for the same reason.


►Insertion loss• Conservative estimates (standard FR4)

PCB traces 0.25 ― 0.35 db/inch at 1.25 GHzStandard FR4 vias (T-depth < 150 mils) vias 0.25 db eachBackplane vias (T > 150 mils) 0.5 db eachConnectors (CEM spec only allows 1db loss up to 1.25 GHz

• Two types of loss to considerSkin effect loss

– Resistive loss due to the tendency of current to flow near the surface of a conductor at high frequencies

Dielectric loss– Loss due to heating effects in the surrounding dielectric materials

Loss Total = Loss Skin Effect + LossDielectic

SerDes – Loss

Presenter

Presentation Notes

Start out using these conservative estimates for loss Always add the two together to get Total loss. what's the assumed via diameter and depth? Depth is shown-- segments vias into backplane vs non-backplane systems. Width was never assumed, but the conservative losses hold for just about any size via


SerDes – Loss

α = 2.3 (f ) tan(θ) er

α o f / tw

LossTotal = LossSkin Effect + LossDielectric

tw = trace width

tan(θ) = loss tangenter = dielectric constant

►Skin effect loss• Grows in proportion to the

square root of frequency• Grows in proportion to

decreasing trace width

►Dielectric loss• Grows in proportion to the

frequency• Grows in proportion to loss

tangent of material• Grows in proportion to the

square root of dielectric constant

Presenter

Presentation Notes

KEY At PCI Express 1.25 GHz, Dielectric loss is starting to become the dominant of the two.


SerDes – Loss

ConnectorAC Caps

System Card Add-in Card

Tx Rx

►Return loss• Reflected signal amplitude in the reverse direction (in path

from Rx to Tx)• Matching Impedance along the path minimizes return loss


►PCB trace routing• Maintain symmetry of diff pair routing

Placing AC capacitors side-by-side symmetrically will help this

• Side-by-side breakout from package pins

• Serpentine or loop-end route where non-symmetrical breakouts patterns cannot be avoided

• Stitching vias (to GND) at all diff pair via sites

SerDes PCB Design Recommendations (cont.)

TM

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