JV10-CS

5

4

3

2

1

JV10-CS Block DiagramClock Generator ICS9LRS3197AKLFTD

Project code:91.4GS01.001 PCB P/N :48.4GS01.0SA REVISION :09918-1

SYSTEM DC/DCRT8223INPUTSDCBATOUT

OUTPUTS5V_S5 3D3V_S5 42

3

DDRIII Slot 0 21 800/1066/1333 DDRIII Slot 1 22 800/1066/1333

DDRIII Channel A

SFF

Intel CPUINPUTS

SYSTEM DC/DCRT8209EOUTPUTS1D5V_S3 43 4,5,..,10,11 DCBATOUT

D

DDRIII Channel B

FDIx8

DMIx4 CRT LCD WXGA+ HDMI24

SYSTEM DC/DCRT8209BINPUTSDCBATOUT

OUTPUTS1D05V_S0 44

Mini-Card WLAN & 3G33

RGB CRTPCIE+USB 2.0

INTEL

PCHGiga LAN AR8151PCIE31

LVDS 2CH

23

SYSTEM DC/DCRT9026INPUTS OUTPUTSDDR_VREF_S3 43C

14 USB 2.0/1.1 ports ETHERNET (10/100/1000Mb) High Definition Audio 6 SATA ports 8 PCIE ports ACPI 1.1 LPC I/F AZALIA34

C

RJ45 CONN32

Digital Display

25 5V_S5

WEBCAM

23

CPU DC/DCTPS51611INPUTSDCBATOUT

35

MIC IN INT MIC

23

HD AUDIO CODEC ALC271X

BLUETOOTH 38USB 2.0

OUTPUTSVCC_CORE41

PCI/PCI BRIDGE

USB x 329,38

INTERSIL CHARGERISL88731AINPUTSDCBATOUT

35

LINE OUT

Card Reader RTS513830

SD/MMC MS/MS Pro/xD31

OUTPUTS BT+45B

B

SATA

SATA HDD28

12,13,...,19,20

2CH SPEAKER35

SPI

Flash ROM 4MB 37

PCB STACKUPTOP Power

LPC Bus

LPC debug

37

S S

KBCSPI

GND36

NPCE781B

BOTTOM

JV10 CSA A

Flash ROM 36 128KB26

Thermal Sensor G795 26

Wistron CorporationTouch PAD 38 Int. KB21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

CPU FAN4 3 2

Block DiagramSize A3 Document Number Rev

JV10-CSSheet1

-11 of 50

Date: Friday, January 22, 20105

5

4

3

2

1

PCH StrappingNameSPKR

Processor StrappingSchematics NotesPin NameCFG[4]

Strap DescriptionEmbedded DisplayPort Presence PCI-Express Static Lane Reversal PCI-Express Configuration Select Reserved Temporarily used for early Clarksfield samples.

Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k - 10-k weak pull-up resistor. Weak internal pull-down. Do not pull high. Default Mode: Internal pull-up. Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak pull-down resistor). High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Default (SPI): Left both GNT0# and GNT1# floating. No pull up required. Boot from PCI: Connect GNT1# to ground with 1-k pull-down resistor. Leave GNT0# Floating. Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k pull-down resistor. Default - Internal pull-up. Low (0)= Configures DMI for ESI compatible operation (for servers only. Not for mobile/desktops). Default: Do not pull low. Disable ME in Manufacturing Mode: Connect to ground with 1-k pull-down resistor.

Configuration (Default value for each bit is 1 unless specified otherwise)1: Disabled - No Physical Display Port attached to Embedded DisplayPort. 0: Enabled - An external Display Port device is connected to the Embedded Display Port. 1: Normal Operation. 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1: Single PCI-Express Graphics 0: Bifurcation enabled Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor Note: Only temporary for early CFD samples (rPGA/BGA) [For details please refer to the MoW and sighting report]. For a common motherboard design (for AUB and the pull-down resistor should be used. Does impact AUB functionality. WW33 CFD), not

Default Value1D

D

INIT3_3V# GNT3#/ GPIO55 INTVRMEN GNT0#, GNT1#

CFG[3] CFG[0]

1

1

CFG[7]

0

GNT2#/ GPIO53 GPIO33C

C

SPI_MOSI NV_ALE

Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable iTPM: Left floating, no pull-down required. Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable Danbury: Connect to ground with 4.7-k weak pull-down resistor. Weak internal pull-up. Do not pull low. Low (0): Flash Descriptor Security will be overridden. High (1) : Flash Descriptor Security will be in effect. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-up. Do not pull low. Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.

NC_CLE HAD_DOCK_EN# /GPIO[33] HDA_SDO HDA_SYNC GPIO15 GPIO8 GPIO27

Power SequenceU32 U40 U13

PM_SLP_S4#

1D5V_S3

ALL_PWRGD

1D05V_S0

VTT_PWRGD

KBC

IMVP_VR_EN

RT8209E

RT9025

NPCE781B

B

PCIE RoutingLANE1 LANE2 LAN MiniCard1

USB TablePair 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Device USB3 USB2 NC MINICARD1 WECAM NC NC NC NC USB1(HS) NC Blue Tooth MINIC2 Cardreader IMVP_VR_EN

U77

PCH1C

CPU1

CPU Core PWM

CORE_PWRGD

PCH

H_PWRGD

CPU

TPS51161

IBEXPEAK

AUBURNDALE

PLT_RST#

ALL DEVICEJV10 CSA

A

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title

Table of ContentSize A3 Document Number Rev

JV10-CSSheet1

-12 of 50

Date: Friday, January 22, 20105 4 3 2

5

4

3

2

1

RFL1~4 EC MGB1005G601EBP 1D5V_S0 68.00373.001D

R96 Do Not Stuff

1

DY

2

Normal

Pin 15,18----3.3V/1.05V Pin 15,18---1.5V/1.05V Pin 1,17,24---1.5V/1.05VD

3D3V_S0

RFL1 MGB1005G601FBP-GP 2 1

-13D3V_CK505 C241 SCD1U16V2ZY-2GP C231 SC1U10V2ZY-GP RFL2 MGB1005G601FBP-GP 2 1 1D05V_S0 R323 Do Not Stuff 1 R104 Do Not Stuff 1 DY

Low Power Normal Low Power

Pin 1,17,24---3.3V/1.05V

1

-12

2

1

2

DY2

1D5V_S0

-1RFL3 Do Not Stuff 1 3D3V_S0

SAm JV501D05V JV703D3V

3D3V_CK505_IO

3D3V_S0

1

2 1 1 1C239 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C227 SC10U6D3V3MX-GP SC10U6D3V3MX-GP

3D3V_CK505_1 C492 Do Not Stuff

C224 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP

1

C230

CLK Normal

14.31818M HZCL=20pF0.2pFGEN_XTAL_IN X2 X-14D31818M-50GP C245 SC12P50V2JN-3GP 2 1

SC1U10V2ZY-GP SC1U10V2ZY-GP

2

24

17

29

15

1

VDD_27MHZ

VDDSRC_IO

VDDREF_3_3

C

1

CLK Low Power

VDDDOT96MHZ_3_3

VDDCPU_3_3

VDDSRC_3_3

VDDCPU_IO

18

-1

RFL4 MGB1005G601FBP-GP 1 2 1D5V_S0

DY2

2

2

5

2

C

82.30005.A51 2nd = 82.30005.C5127MHZ_NONSS 27MHZ_SS 6 7 16 25 30 28 27 31 32CPU_STOP# CLK_EN FSC GEN_XTAL_IN GEN_XTAL_OUT PCH_SMBDATA 13,21,22 PCH_SMBCLK 13,21,22 GEN_XTAL_OUT

96 MHz 100 MHz

PCH DMI

13 13 13 13 13 13

DREFCLK# DREFCLK CLK_DMI# CLK_DMI CLK_SATA# CLK_SATA

4 3 14 13 11 10 22 23 19 20

DOT96C_LPR DOT96T_LPR SRCC1_LPR SRCT1_LPR SATAC_LPR SATAT_LPR CPUC0_LPR CPUT0_LPR CPUC1_LPR CPUT1_LPR

2

2

1

100 MHz SATA 133-MHz CPU

CPU_STOP# CLKPWRGD/PD#_3_3 REF_3L/FSLC_3_3 X1 X2 GNDDOT96MHZ SDATA_3_3 SCLK_3_3 GNDSATA

R123 1

C244 SC12P50V2JN-3GP

2 1RFC1

CLK_ICH14 13

14.318 MHz3D3V_S0

33R2J-2-GP

13 CLK_CPU_BCLK# 13 CLK_CPU_BCLK

3G2

SC12P50V2JN-3GP SC12P50V2JN-3GP

GND27MHZ

GNDSRC

GNDCPU

GNDREF

4 3RN31 SRN10KJ-5-GPB

B

1D05V_S0 U20 ICS9LRS3197AKLFT-GP-U R120 Do Not Stuff

GND

2

8

33

26

21

12

9

2

CPU_STOP#

1 2

CLK_EN

D

DY1

71.93197.003 2nd = 71.08595.B03 CLK Lower Power ICS:71.93197.B03,SILEGO:71.08595.00341 VR_CLKEN# Q18 2N7002-11-GP

FSC

G S

2

R118 2K2R2J-2-GP

FSC SPEED

0 133MHz (Default)

1 100MHzJV10 CS

1

A


A

Clock GeneratorSize Custom Document Number Rev Date: Friday, January 22, 20105 4 3 2

JV10-CS

-13 of 501

Sheet

5

4

3

2

1

CPU1A

1 OF 10 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 B12 A13 D12 B11 G40 G38 H34 P34 G28 H25 H24 D29 B26 D26 B23 D22 A20 D19 A17 B14 F40 J38 G34 M34 J28 G25 K24 B28 A27 B25 A24 B21 B19 B18 B16 D15 N40 L38 M32 D40 A38 G32 B33 B35 L30 A31 B32 L28 N26 M24 G21 J20 L40 N38 N32 B39 B37 H32 A34 D36 J30 B30 D33 N28 M25 N24 F21 L20 PEG_IRCOMP_R EXP_RBIAS 1 1

R232 2 49D9R2F-GP R229 2 750R2F-GP

14 14 14 14D

DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3

F7 J8 K8 J4 F9 J6 K9 J2 H17 K15 J13 F10 G17 M15 G13 J11

DMI_RX#0 DMI_RX#1 DMI_RX#2 DMI_RX#3 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_TX#0 DMI_TX#1 DMI_TX#2 DMI_TX#3 DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3

14 14 14 14 14 14 14 14 14 14 14 14

D

DMI DMI

C

14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14

FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1

L2 N7 M4 P1 N10 R7 U7 W8 K1 N5 N2 R2 N9 R8 U6 W10 AC7 AC9 AB5 AA1 AB2

FDI_TX#0 FDI_TX#1 FDI_TX#2 FDI_TX#3 FDI_TX#4 FDI_TX#5 FDI_TX#6 FDI_TX#7 FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1

C

B

PCI EXPRESS -- GRAPHICS

Intel(R) FDI Intel(R) FDI

14 14 14

B

JV10 CS

A

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A4

A

CPU SFF 1 of 8(DMI/FDI/PEG)Document Number

AUBURNDALE-1-GP-U3-NF5 4 3

JV10-CSSheet 41

Rev

-1of 50


5

4

3

2

1

1D

R254 2 20R2F-GP

CPU1B H_COMP3

2 OF 10

AD71 AC70 AD69 AE66 M71

COMP3 COMP2 COMP1 COMP0 PROC_DETECT CATERR# BCLK BCLK#

1 1 1

Clocks

H_COMP2 2 R255 20R2F-GP H_COMP1 2 R253 49D9R2F-GP H_COMP0 2 R73 49D9R2F-GP

AK7 AK8 K71 J70 L21 J21 Y2 W4

BCLK_CPU_P 17 BCLK_CPU_N 17

Misc Misc

D

BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#

CLK_EXP_P_R 13 CLK_EXP_N_R 13

SB

1D05V_S0

H_CATERR# H_CATERR# 2 R257 49D9R2F-GP PROCHOT# 2 R256 68R2-GP

N61

If supports integrated graphics but without Embedded DisplayPort(eDP), these pins can also be connected to GND directly. Refer JV50 CPDDR3_DRAMRST# 21,22 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 1D05V_S0 RN26 SRN10KJ-5-GP 4 3 PM_EXTTS#0_R 21 PM_EXTTS#1_R 22C

Thermal Thermal

1 1

17

H_PECI

N19

SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

BJ12 BV33 BP39 BV40 AV66 AV64

PECI

PROCHOT#

1 2

N67

DDR3 Misc

PROCHOT#

PM_EXT_TS#0 PM_EXT_TS#1

C

17,39 PM_THRMTRIP-A#

N17

THERMTRIP#

SM_RCOMP_0

1 R245 1 R246 1 R247

2 100R2F-L1-GP-U 2 24D9R2F-L-GP 2 130R2F-1-GP

PRDY# PREQ# N701D5V_S3 RN61 SRN1KJ-10-GP-U 14 PM_DRAM_PWRGD 14 H_PM_SYNC

U71 U69 T67 N65 P69 T69 T71 P71 T70 W71 J69 J67 J62 K65 K62 J64 K69 M69

SM_RCOMP_1 SM_RCOMP_2 XDP_TRST# XDP_TDO XDP_TDI_TDO_M XDP_DBRESET# RN64 SRN56J-4-GP 1 4 2 3 1D05V_S0

RESET_OBS#

M17

PM_SYNC

TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7

Power Management Power Management

1 2 3 4

8 7 6 5

17,49

H_PWRGD

AM7 Y67 AM5

VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK VTTPWRGOOD TAPPWRGOOD RSTIN#

JTAG & MBP

From PCH44 H_VTTPWRGD RN60 SRN1K5J-1-GP 8 7 6 5

1

TP24 Do Not Stuff

B

B

H15 Y70

1 2 3 416,31,33,36,37,39,49 PLT_RST#

PLT_RST#_R

G3

AUBURNDALE-1-GP-U3-NF

JV10 CS

A

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom

A

CPU SFF 2 of 8(CLK/Thermal) Document Number JV10-CS Sheet1

Rev

-15 of 50


5

4

3

2

1

CPU1D CPU1C 3 OF 10

4 OF 10

22 M_B_DQ[63..0] 21 M_A_DQ[63..0]D

C

B

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AT8 AT6 BB5 BB9 AV7 AV6 BE6 BE8 BF11 BE11 BK5 BH13 BF9 BF6 BK7 BN8 BN11 BN9 BG17 BK15 BK9 BG15 BH17 BK17 BN20 BN17 BK25 BH25 BJ20 BH21 BG24 BG25 BJ40 BM43 BF47 BF48 BN40 BH43 BN44 BN47 BN48 BN51 BH53 BJ55 BH48 BJ48 BM53 BN55 BF55 BN57 BN65 BJ61 BF57 BJ57 BK64 BK61 BJ63 BF64 BB64 BB66 BJ66 BF65 AY64 BC70

SA_CK0 SA_CK#0 SA_CKE0 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

BM34 BP35 BF20

M_CLK_DDR0 21 M_CLK_DDR#0 21 M_CKE0 21

SA_CK1 SA_CK#1 SA_CKE1

BK36 BH36 BK24

M_CLK_DDR1 21 M_CLK_DDR#1 21 M_CKE1 21

SA_CS#0 SA_CS#1

BH40 BJ47

M_CS#0 21 M_CS#1 21

SA_ODT0 SA_ODT1

BF43 BL47

M_ODT0 21 M_ODT1 21

SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7

BB10 BJ10 BM15 BN24 BG44 BG53 BN62 BH59

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DM[7..0] 21

DDR SYSTEM MEMORY - B

SA_DQS#0 SA_DQS#1 SA_DQS#2 SA_DQS#3 SA_DQS#4 SA_DQS#5 SA_DQS#6 SA_DQS#7

AY5 BJ7 BN13 BL21 BH44 BK51 BP58 BE62

M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_DQS#[7..0] 21

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

AY7 BJ5 BL13 BN21 BK44 BH51 BM60 BE64

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

M_A_DQS[7..0] 21

21 21 21

M_A_BS0 M_A_BS1 M_A_BS2

BT38 BH38 BF21

SA_BS0 SA_BS1 SA_BS2

21 21 21

M_A_CAS# M_A_RAS# M_A_WE#

BK43 BL38 BF38

SA_CAS# SA_RAS# SA_WE#

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

BT36 BP33 BV36 BG34 BG32 BN32 BK32 BJ30 BN30 BF28 BH34 BH30 BJ28 BF40 BN28 BN25

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_A[15..0] 21

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

BA2 AW2 BD1 BE4 AY1 BC2 BF2 BH2 BG4 BG1 BR6 BR8 BJ4 BK2 BU9 BV10 BR10 BT12 BT15 BV15 BV12 BP12 BV17 BU16 BP15 BU19 BV22 BT22 BP19 BV19 BV20 BT20 BT48 BV48 BV50 BP49 BT47 BV52 BV54 BT54 BP53 BU53 BT59 BT57 BP56 BT55 BU60 BV59 BV61 BP60 BR66 BR64 BR62 BT61 BN68 BL69 BJ71 BF70 BG71 BC67 BK70 BK67 BD71 BD69

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

SB_CK0 SB_CK#0 SB_CKE0 SB_CK1 SB_CK#1 SB_CKE1

BU33 BV34 BT26 BV38 BU39 BT24

M_CLK_DDR2 22 M_CLK_DDR#2 22 M_CKE2 22 M_CLK_DDR3 22 M_CLK_DDR#3 22 M_CKE3 22

D

SB_CS#0 SB_CS#1

BP46 BT43

M_CS#2 22 M_CS#3 22

SB_ODT0 SB_ODT1

BV45 BU49

M_ODT2 22 M_ODT3 22

SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7

BB4 BL4 BT13 BP22 BV47 BV57 BU65 BF67

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DM[7..0] 22

DDR SYSTEM MEMORY A

SB_DQS#0 SB_DQS#1 SB_DQS#2 SB_DQS#3 SB_DQS#4 SB_DQS#5 SB_DQS#6 SB_DQS#7

BE2 BM3 BU12 BT19 BT52 BV55 BU63 BG69

M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_DQS#[7..0] 22

C

SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7

BD4 BN4 BV13 BT17 BT50 BU56 BV62 BJ69

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

M_B_DQS[7..0] 22

22 22 22 22 22 22

M_B_BS0 M_B_BS1 M_B_BS2 M_B_CAS# M_B_RAS# M_B_WE#

BV43 BV41 BV24 BU46 BT40 BT41

SB_BS0 SB_BS1 SB_BS2 SB_CAS# SB_RAS# SB_WE#

SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15

BT34 BP30 BV29 BU30 BV31 BT33 BT31 BP26 BV27 BT27 BU42 BU26 BT29 BT45 BV26 BU23

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_A[15..0] 22

B

AUBURNDALE-1-GP-U3-NFA


JV10 CS

A


CPU SFF 3 of 8(DDR)Document Number

JV10-CSSheet1

Rev

-16 of 50


5

4

3

2

1

check list SAM JV50 JV70 CPU Core PSI# 1-k? pull-up to VTT and 1-k? pull-down to GND for POC. CPU1F SB 1D05V_VTT41 PSI# TP25 Do Not Stuff 1D

1D05V_S0 6 OF 10 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 AW14 AW12 AU60 AU59 AU12 AR60 AR59 AR12 AN60 AN59 AN35 AN33 AN17 AN15 AN14 AN12 AM10 AL60 AL59 AL17 AL15 AL14 AL12 AK35 AK33 AF39 AF37 AF35 AF33 AF32 AF30 AD39 BF60 BF59 BD60 BD59 BB60 BB59 AY60 AW60 AW35 AW33 AD37 AD35 AD33 AD32 AD30 W35 W33 W32 W30 W28 W26 W24 W23 U35 U33 U32 U30 U28 U26 U24 U23 R35 R33 R32 R30 R28 R26 R24 R23 AY10 AN9

1

1

1

1

1

1

C180 SC1U6D3V2KX-GP SC1U6D3V2KX-GP

C181 SC1U6D3V2KX-GP

C182 SC1U6D3V2KX-GP

C185 SC1U6D3V2KX-GP


C134 SC1U6D3V2KX-GP

1 2

C141 SC1U6D3V2KX-GP

2

2

2

2

2

41 CPU_Core_VID[6..0]

PSI# VID0 VID1 VID2 VID3 VID4 VID5 VID6 VTT_SELECT1 PROC_DPRSLPVR

2

F68 A61 D61 D62 A62 B63 D64 D66 AN1

CPU_Core_VID0 CPU_Core_VID1 CPU_Core_VID2 CPU_Core_VID3 CPU_Core_VID4 CPU_Core_VID5 CPU_Core_VID6

D

CPU VIDS CPU VIDS

41 PM_DPRSLPVR

F66

1

1

C405 SC10U6D3V3MX-GP


1 2


1.1V RAIL POWER

2

41 VCC_CORE RN25 SRN100J-3-GP 1 2C

IMVP_IMON

A41

ISENSE

4 3

41 41 44

VCC_SENSE VSS_SENSE VTT_SENSE

F64 F63 N13 R12

VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT

2

SENSE LINES SENSE LINES

C

1D8V_S0


B

2

W39 W37 U37 R39 R37

VCCPLL VCCPLL VCCPLL VCCPLL VCCPLL

POWER

1.8V 1.8V

1

B

1D5V_S3 1 2 VDDQ_CK BB14 BB12 C109 SC1U6D3V2KX-GP VDDQ_CK1 VDDQ_CK2

Please note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1V

2

1

L5 IND-1UH-2-GP

AUBURNDALE-1-GP-U3-NF JV10 CS

A


A

CPU SFF 4 of 8(POWER/VTT)Document Number

JV10-CSSheet1

Rev

-17 of 50


5

4

3

2

1

-1

SBD

modify C441

VCC_GFXCORE

CPU1G

7 OF 10D

DY2

SENSE LINES

C438 SC1U6D3V2KX-GP

C439 SC1U6D3V2KX-GP

C440 SC1U6D3V2KX-GP

C441 Do Not Stuff

C437 SC1U6D3V2KX-GP

C121 SC1U6D3V2KX-GP

C122 SC1U6D3V2KX-GP

C125 SC1U6D3V2KX-GP

C128 SC1U6D3V2KX-GP

SB-11 1 1 1

modify C487 C491 C443

C487 Do Not Stuff Do Not Stuff


C491 SC10U10V5ZY-1GP SC10U10V5ZY-1GP

C443 SC10U10V5ZY-1GP

C114 SC10U6D3V3MX-GP SC10U6D3V3MX-GP

DY2

C

- 1.5V RAILS

SB1 1 1 1 1 1 1 1 1 1 1 1C444 SC1U6D3V2KX-GP C445 SC1U6D3V2KX-GP C446 SC1U6D3V2KX-GP C447 SC1U6D3V2KX-GP C448 SC1U6D3V2KX-GP C449 SC1U6D3V2KX-GP C450 SC1U6D3V2KX-GP C451 SC1U6D3V2KX-GP C452 SC1U6D3V2KX-GP C453 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C132 SC10U6D3V3MX-GP SC10U6D3V3MX-GP

1D05V_S0

AN32 AN30 AN28 AN26 AN24 AN23 AN21 AN19 AL32 AL30 AL28 AL26 AL24 AL23 AL21 AL19 AK14 AK12 AJ10 AH14 AH12 AF28 AF26 AF24 AF23 AF21 AF19 AF17 AF15 AF14 AD28 AD26 AD24 AD23 AD21 AD19 AD17 W21 W19 U21 U19 U17 U15 U14 U12 R21 R19 R17 R15

VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VAXG VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

VAXG_SENSE VSSAXG_SENSE

AF12 AF10

VCC_AXG_SENSE 46 VSS_AXG_SENSE 46 GFX_VID[6..0] 46

1

1

1

1

1

1

1

1

2

2

2

2

2

2

2

2

1

GRAPHICS VIDs

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6 GFX_VR_EN GFX_DPRSLPVR GFX_IMON VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VTT0_DDR VTT0_DDR VTT0_DDR VTT0_DDR VTT0_DDR VTT0_DDR VTT0_DDR VTT0_DDR VTT0_DDR VTT0_DDR VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1

AF71 AG67 AG70 AH71 AN71 AM67 AM70 AH69 AL71 AL69 BU40 BU35 BU28 BN38 BM25 BL30 BJ38 BH32 BH28 BG43 BF16 BF15 BD35 BD33 BD32 BD30 BD28 BD26 BD24 BD23 BD21 BD19 BD17 BD15 BB35 BB33 BB32 BB30 BB28 BB26 BB24 BB23 BB21 BB19 BB17 BB15 AW32 AW30 AW28 AW26 AW24 AW23 AW21 AW19 AW17 AW15 AD15 AD14 AD12 AB12 AA12 W17 W15 W14 W12

GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6

GFX_VR_EN

1R203 4K7R2J-2-GP

GRAPHICS

GFX_VR_EN 46 GFX_DPRSLPVR 46 GFX_IMON 46

1

2

2

2

2

1

1

1

1

1

21D5V_S3 C115 SC1U6D3V2KX-GP C123 SC1U6D3V2KX-GP C127 SC1U6D3V2KX-GP C133 SC1U6D3V2KX-GP C126 SC10U6D3V3MX-GP SC10U6D3V3MX-GP

1 2


2

2

2

2

2

C



2

2

2

2

2

2

2

2

2

2

2

2

2

1

1

1

1

1

B

C454 Do Not Stuff





1

SB


VCAP2

DY2

DY2

-1 modify C457 C454

AK62 AK60 AK59 AH60 AH59 AF60 AF59 AD60 AD59 AB60 AB59 AA60 AA59 W60 W59 U60 U59 R60 R59

VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2 VCAP2

POWER

DDR3

1

PEG & DMI PEG & DMI

1D05V_S0

B

2

2

2

2

1

1

1

1


C107 SC1U6D3V2KX-GP

C116 SC1U6D3V2KX-GP

C124 SC1U6D3V2KX-GP

1 2

C135 SC1U6D3V2KX-GP

2

2

2

1

1

1

1

C187 SC1U6D3V2KX-GP

C188 SC1U6D3V2KX-GP

C189 SC1U6D3V2KX-GP

C190 SC1U6D3V2KX-GP

1

C191 SC1U6D3V2KX-GP

2

2

2

2

2


2

A

JV10 CS

A

Wistron Corporation Do not dummy these CAPsTitle Size A3 Document Number 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

CPU SFF 5 of 8(PWR/DDR/GFX/) JV10-CSSheet1

Rev

-18 of 50


5

4

3

2

1

CPU1H

8 OF 10 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AF57 AF55 AF53 AF51 AF50 AF48 AF46 AF44 AF42 AF41 AD55 AD51 AD48 AD44 AD41 AB55 AB51 AB48 AB44 AB41 AA55 AA51 AA48 AA44 AA41 W55 W51 W48 W44 W41 U55 U51 U48 U44 U41 R55 R51 R48 R44 R41 P60 N55 N51 N48 N44 N42 M60 M51 M44 L55 K60 K51 K44 J55 H60 H51 H44 G60 G55 G51 G44 F55 E60 E57 E53 E50 E46 E42 D59 D57 D55 D54 D52 D50 D48 D47 D45 D43 B60 B56 B53 B49 B46 B42 A57 A54 A50 A47 A43

VCC_CORE

VCAP0 BD55 BD51 BD48 BB55 BB51 BB48 AY57 AY53 AY50 AW57 AW53 AW50 AU55 AU51 AU48 AR55 AR51 AR48 AN57 AN53 AN50 AL57 AL53 AL50 AK57 AK53 AK50 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0 VCAP0

C175 SC1U6D3V2KX-GP

C161 Do Not Stuff

C152 SC1U6D3V2KX-GP

C160 Do Not Stuff

C150 SC1U6D3V2KX-GP

C140 SC1U6D3V2KX-GP

-1 modify C160 C161

1

1

1

1

1

DY2

DY2

2

2

2

1

1

1

1

1


C165 SC1U6D3V2KX-GP

C163 SC1U6D3V2KX-GP

C164 SC1U6D3V2KX-GP

C176 SC1U6D3V2KX-GP

1

C177 SC1U6D3V2KX-GP

2

2

2

2

2

D

2

2

1

D

-11 1 1 1 1 C186 SC10U6D3V3MX-GP C169 SC10U6D3V3MX-GP C146 SC10U10V5ZY-1GP C154 SC10U10V5ZY-1GP C168 Do Not Stuff 1 C167 Do Not Stuff


C179 SC1U6D3V2KX-GP

C162 SC1U6D3V2KX-GP

C178 SC1U6D3V2KX-GP

C174 SC1U6D3V2KX-GP

C172 SC1U6D3V2KX-GP

DY2

DY2

modify C167 C168

1

1

1

1

1

1

2

2

2

2

2

2

2

2

2

POWER

2

SB1 1 1 1 1 1 1 1 1 C463 SC1U6D3V2KX-GP C464 SC1U6D3V2KX-GP C465 SC1U6D3V2KX-GP C466 SC1U6D3V2KX-GP C467 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C468 SC1U6D3V2KX-GP C469 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C470 SC1U6D3V2KX-GP C471 SC1U6D3V2KX-GP SC1U6D3V2KX-GP 1 C472 SC1U6D3V2KX-GPC

SamCPU CORE SUPPLYC

Processor package decoupling DO NOT connect to any power railVCAP1 BD44 BD41 BD37 BB44 BB41 BB37 AY46 AY42 AY39 AW46 AW42 AW39 AU44 AU41 AU37 AR44 AR41 AR37 AN46 AN42 AN39 AL46 AL42 AL39 AK46 AK42 AK39 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1 VCAP1

2

2

2

2

2

2

2

2

2

1

1

1

1

1

C155 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C142 SC1U6D3V2KX-GP SC1U6D3V2KX-GP

C153 SC1U6D3V2KX-GP

C151 SC1U6D3V2KX-GP

C148 SC1U6D3V2KX-GP

C149 SC1U6D3V2KX-GP

1

C158 SC1U6D3V2KX-GP

2

SB1 1 1 1 1 1 C473 Do Not Stuff C474 SC10U6D3V3MX-GP C475 SC10U10V5ZY-1GP C476 Do Not Stuff C478 SC10U10V5ZY-1GP SC10U10V5ZY-1GP C480 Do Not Stuff Do Not Stuff 1 2 C481 SC10U10V5ZY-1GP

2

2

2

2

2

2

DY2

DY2

DY2

2

2

1

1

1

1

1

C143 SC1U6D3V2KX-GP

C156 SC1U6D3V2KX-GP

C157 SC1U6D3V2KX-GP

C144 SC1U6D3V2KX-GP

1

C147 SC1U6D3V2KX-GP

2

2

2

2

2

B

2

2

B

1

1

1

1





1

SBC486 SC10U6D3V3MX-GP

-1 modify C477 C479 C476 C473

2

2

2

2

JV10 CSA

A

2


Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Date:

CPU SFF 6 of 8(CPUCORE)Document Number

JV10-CSSheet1

Rev

-19 of 50

Friday, January 22, 2010

5

4

3

2

5

4

3

2

1

CPU1E

5 OF 10 RSVD#W66 RSVD#W64 RSVD#AC69 RSVD#AC71 RSVD#AA71 RSVD#AA69 W66 W64 AC69 AC71 AA71 AA69 R66 R64

D

D

CFG0 1 R216 Do Not Stuff

PCI-Express Configuration Select

CFG0 CFG3

C

AL4 AM2 AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2 AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17

RSVD#R66 RSVD#R64

DY2

CFG0

1:Single PEG 0:Bifurcation enabled

RSVD_NCTF#BT5 RSDV_NCTF#BR5 RSDV_NCTF#BV6 RSDV_NCTF#BV8 RSVD#AV69 RSVD#AK71 RSVD#AN69 RSVD#AP66 RSVD#AH66 RSVD#AK66 RSVD#AR71 RSVD#AM66 RSVD#AK69 RSVD#AU71 RSVD#AT70 RSVD#AR69 RSVD#AU69 RSVD#AT67 RSVD_TP2 RSVD_TP1 RSVD#AV4 RSVD#AU2 RSVD#BE69 RSVD#BE71

BT5 BR5 BV6 BV8 AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67 AP2 AN7 AV4 AU2 BE69 BE71B

CFG3 1 R217 Do Not Stuff

CFG3 - PCI-Express Static Lane Reversal

DY2

CFG3

1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...C

AU1 T4 T2 U1 V2B

RSVD_TP0 RSVD#T4 RSVD#T2 RSVD#U1 RSVD#V2 RSVD#AV71 RSVD#AW70 RSVD#AY69 RSVD#BB69 RSVD#D8 RSVD#B7 RSVD#A10 RSVD#B9 RSVD_NCTF#C5 RSVD_NCTF#A6 RSVD_NCTF#E3 RSVD_NCTF#F1

AV71 AW70 AY69 BB69 D8 B7 A10 B9 C5 A6 E3 F1

RESERVED

A

NCTF_DC_TEST#BV71 NCTF_DC_TEST#BV69 NCTF_DC_TEST#BV68 NCTF_DC_TEST#BV5 NCTF_DC_TEST#BV3 NCTF_DC_TEST#BV1 NCTF_DC_TEST#BT71 DC_TEST_BT69 DC_TEST_BT3 NCTF_DC_TEST#BT1 NCTF_DC_TEST#BR71 NCTF_DC_TEST#BR1 NCTF_DC_TEST#E71 NCTF_DC_TEST#E1 NCTF_DC_TEST#C71 DC_TEST_C69 NCTF_DC_TEST#C3 NCTF_DC_TEST#A71 NCTF_DC_TEST#A69 NCTF_DC_TEST#A68 NCTF_DC_TEST#A5

NCTF TEST PIN: A5,A68,A69,A71,C3,C71,E1,E71,BR1,BR71, BT1,BT71,BV1,BV3,BV5,BV68,BV69,BV71

BV71 BV69 BV68 BV5 BV3 BV1 BT71 BT69 BT3 BT1 BR71 BR1 E71 E1 C71 C69 C3 A71 A69 A68 A5

1

TP27 Do Not Stuff

1

TP20 Do Not Stuff

1

TP21 Do Not Stuff TP26 Do Not Stuff

JV10 CS

1


A

AUBURNDALE-1-GP-U3-NF Size A45 4 3 2

CPU SFF 7 of 8(RESERVED)Document Number

JV10-CSSheet 101

Rev

-1of 50


5

4

3

2

1

CPU1I

9 OF 10

D

C

B

A

BU62 BU58 BU55 BU51 BU48 BU44 BU37 BU32 BU25 BU21 BU18 BU14 BU11 BU7 BP42 BN64 BN6 BM70 BM51 BM44 BM32 BM24 BM17 BL57 BL55 BL48 BL40 BL28 BL20 BK63 BK60 BK53 BK34 BK10 BJ64 BJ21 BJ9 BJ1 BH70 BH57 BH55 BH47 BH24 BH20 BH15 BG51 BG36 BF62 BF30 BF13 BF8 BE70 BE65 BE9 BE1 BD57 BD53 BD50 BD46 BD42 BD39 BD14 BB71 BB62 BB57 BB53 BB50 BB46 BB42 BB39 BB7 BB1 BA70 AY71 AY66 AY62 AY59 AY55 AY51 AY48 AR42 AR39 AR35 AR33 AR32 AR30 AR28 AR26 AR24 AR23 AR21 AR19 AR17 AR15 AR14 AR4 AR1 AP70 AP64 AN62 AN55 AY44 AY41 AY37 AY35 AY33 AY32 AY30 AY28 AY26

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AY24 AY23 AY21 AY19 AY17 AY15 AY14 AY12 AY8 AY4 AW67 AW62 AW59 AW55 AW51 AW48 AW44 AW41 AW37 AV9 AV1 AU70 AU62 AU57 AU53 AU50 AU46 AU42 AU39 AU35 AU33 AU32 AU30 AU28 AU26 AU24 AU23 AU21 AU19 AU17 AU15 AU14 AU4 AT64 AT10 AR62 AR57 AR53 AR50 AR46 AN51 AN48 AN44 AN41 AN37 AN5 AN4 AM64 AM8 AL62 AL55 AL51 AL48 AL44 AL41 AL37 AL35 AL33 AL1 AK70 AK64 AK55 AK51 AK48 AK44 AK41 AK37 AK32 AK30 AK28 AK26 AK24 AK23 AK21 AK19 AK17 AK15 AJ70 AH62 AH57 AH55 BV66 BV64 BT68 BR69 BR68 BR3 BN71 BN1 BL71 BL1 R14 H71 F71 E69 E68 A66 A64 E5 C68

CPU1J

10 OF 10

AH53 AH51 AH50 AH48 AH46 AH44 AH42 AH41 AH39 AH37 AH35 AH33 AH32 AH30 AH28 AH26 AH24 AH23 AH21 AH19 AH17 AH15 AH4 AG64 AG9 AG6 AF69 AF62 AF1 AE70 AE64 AD62 AD57 AD53 AD50 AD46 AD42 AD4 AC67 AC64 AC10 AC5 AC1 AB70 AB62 AB57 AB53 AB50 AB46 AB42 AB39 AB37 AB35 AB33 AB32 AB30 AB28 AB26 AB24 AB23 AB21 AB19 AB17 AB15 AB14 AB9 AA66 AA64 AA62 AA57 AA53 AA50 AA46 AA42 AA39 AA37 AA35 AA33 AA32 AA30 AA28 AA26 AA24 AA23 AA21 AA19 F20 F4 E37 E33 E30 E16 E12 D41 D38 D34 D31 D27 D24 D20 D17 D13 D10 D6 B65 B40

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

A40 A36 A33 A29 A26 A22 A19 A15 A12 A8 B62 B58 B55 B51 B48 B44 A59 A55 A52 A48 A45 AA17 AA15 AA14 AA4 W69 W62 W57 W53 W50 W46 W42 W6 W1 V70 U64 U62 U57 U53 U50 U46 U42 U39 U9 U4 T1 R70 R62 R57 R53 R50 R46 R42 R5 P4 N63 N57 N53 N50 N46 N30 N21 N15 M53 M42 M36 M1 L70 L57 L48 L47 L13 K64 K53 K43 K36 K34 K32 K25 K17 K11 K6 K4 J65 J57 J48 J47 J40 J9 H53 H43 H36 H1 G70 G57 G53 G48 G47 G43 G30 G24 G20 G15 F61 F48 F47 F28

D

C

B

JV10 CS

A


CPU SFF 8 of 8(VSS)Document Number

AUBURNDALE-1-GP-U3-NF4 3

JV10-CSSheet1

Rev

AUBURNDALE-1-GP-U3-NF Date: Friday, January 22, 20105

-111 of 50

5

4

3

2

1

RTC_X1 RTC_AUX_S5 RTC_X2 R163 330KR2F-L-GP INTVRMEN 1 2

integrated VccSus1_05,VccSus1_5,VccCL1_5

INTVRMEN LAN100_SLP

High=Enable High=Enable

Low=Disable Low=Disable

1 2 R168 10MR2J-L-GP

integrated VccLan1_05VccCL1_05

1 4 1

2R164 1MR2J-1-GP

SM_INTRUDER#

D

3 2

2 2

SBC307 SC5P50V2CN-2GP PCH1A RN40 SRN20KJ-GP-U RTC_X1 RTC_X2 ICH_RTCRST# SRTCRST# 1 OF 10

D

C304 SC5P50V2CN-2GP 34 34 34 34

X3 X-32D768KHZ-34GPU

82.30001.661 2ND = 82.30001.B21

1

1

RTC_AUX_S5

B13 D13 C14 D17 A16 A14

RTCX1 RTCX2 RTCRST#

2 1

3 4 1C297 SC1U10V3KX-3GP

FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 FWH4/LFRAME#

D33 B33 C32 A32 C34 A34 F34 AB9

LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3

36,37 36,37 36,37 36,37

LPC_LFRAME# 36,37

SRTCRST#

RTC

LPC

SM_INTRUDER# INTVRMEN

INTRUDER# INTVRMEN

LDRQ0# LDRQ1#/GPIO23 SERIRQ

1

2

2

C296 SC1U10V3KX-3GP

2

G80 Do Not Stuff Do Not Stuff

INT_SERIRQ 36

1

ACZ_BIT_CLK ACZ_SYNC

A30 D29 P1

HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDO HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO13 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA0RXN SATA0RXP SATA0TXN SATA0TXP

C

ACZ_RST#_AUDIO ACZ_BITCLK_AUDIO ACZ_SYNC_AUDIO ACZ_SDATAOUT_AUDIO

1 2 3 4

RN45 SRN33J-7-GP 8 7 6 5

34

ACZ_SPKR ACZ_RST#

AK7 AK6 AK11 AK9 AH6 AH5 AH9 AH8 AF11 AF9 AF7 AF6 AH3 AH1 AF3 AF1 AD9 AD8 AD6 AD5 AD3 AD1 AB3 AB1 AF16 AF15

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C

SATA_RXN0_C C273 2

SCD01U50V2KX-1GP 1 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP 2 SCD01U50V2KX-1GP 2

SATA_RXN0 28 SATA_RXP0 28 SATA_TXN0 28 SATA_TXP0 28C

HDD

SATA_RXP0_C C272 1 SATA_TXN0_C C87 SATA_TXP0_C C83

1 1

ACZ_RST# ACZ_BIT_CLK ACZ_SYNC ACZ_SDATAOUT

C30 G30 F30 E32 F32

34 ACZ_SDATAIN0

ACZ_BIT_CLK

PCH_SPI_CLK

IHDA

SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3RXN SATA3RXP SATA3TXN SATA3TXP

1

EC11 Do Not Stuff Do Not Stuff

1

ACZ_SDATAOUT EC14 Do Not Stuff Do Not Stuff 36 ME_UNLOCK#

B29 H32 J30

DY2

DY2

SATA

When unused all JTAG pins may be NCDo Not Stuff TP14

SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP

1 1

PCH_JTAG_TCK

M3 K3 K1 J2 J4

JTAG_TCK JTAG_TMS

SBR292 51R2F-2-GP

JTAG

JTAG_TDI JTAG_TDO TRST#

1D05V_S0 SATAICOMP

2

SATAICOMPO SATAICOMPI

1

2

-1B

R40 37D4R2F-GPB

37 PCH_SPI_CLK 37 PCH_SPI_CS#0

1 R305 1 R306

2 2

SPI_CLK_R 0R2J-2-GP SPI_CS#0_R 0R2J-2-GP

BA2 AV3 AY3

SPI_CLK SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISOIBEXPEAK-M-GP-NF

SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19

T3 Y9 V1

SATA_LED# 14,27 SATA_DET#0_R SATA_DET#1_R 17 RN17 SRN10KJ-7GP 17 PCH_GPIO17 SATA_DET#0_R INT_SERIRQ

1D8V_S0

1D5V_S0

37 PCH_SPI_MOSI

1

1

-1R152 Do Not Stuff

37 SPI_MOSO_R

AV1

R151 Do Not Stuff

DY2

DY2

SPI_CS0#, SPI_MISO, SPI_MOSI, SPI_CLK: No series resistor required if routing length is 1.5"-6.5"

SPI

1 R307

2

SPI_MOSI_R 0R2J-2-GP

AY1

3D3V_S0

ACZ_SYNC

RTC CONN3D3V_AUX_S5

17 PCH_GPIO37

5 6 7 8

4 3 2 1

R150 Do Not Stuff

DY2A

23.25218.001 Pin define ,connector part numberRTC_BAT

1

RTC_AUX_S5

2 3 4 2 1 3

-1

SWPA Pin define

JV10 CS

A

1

Wistron Corporation2nd = 20.F1035.002 20.F0772.002ACES-CON2-11-GP RTC2 Title Size A3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

C381 SC1U16V3ZY-GP

1D26 BAS40CW-GP

RTC_BAT_1

2

1

If reserve 1.5/1.8V option for VCCVRM.Not Power plan change only. Please refer figure2.HDA_SYNC will be strap to define VCCVRM is 1.5 or 1.8V source. Means need have Pull high/low resistor to option, P/H voltage base on HAD Link is 1.5V or 3.3V(Figure 3).

R233 1KR2J-1-GP

2

PCH 1 of 9(SATA/RTC/HDA)Document Number

83.00040.E81 2nd = 83.00040.M81

JV10-CSSheet1

Rev

-112 of 50


5

4

3

2

1

3D3V_S5

LAN MINICARD1D

31 31 31 31 33 33 33 33 33 33 33 33

PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3

SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2

1 C359 1 C358

TXN1 TXP1

BG30 BJ30 BF29 BH29 AW30 BA30 BC30 BD30 AU30 AT30 AU32 AV32 BA32 BB32 BD32 BE32 BF33 BH33 BG32 BJ32 BA34 AW34 BC34 BD34 AT34 AU34 AU36 AV36 BG34 BJ34 BG36 BJ36 AK48 AK47

PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2

SMBALERT#/GPIO11 SMBCLK SMBDATA SML0ALERT#/GPIO60

B9 H14 C8 J14 C6 G8 M14 E10 G12 T13 T11 T9

PCH_GPIO11 SMB_CLK

8 7 6 5RN12 SRN2K2J-2-GP 3D3V_S5 3D3V_S0

PCH1B

2 OF 10

SB

1 2 3 4

SML0_CLK KBC_SCL1 PCH_GPIO60 17 SML0_CLK SML0_DATA

SML0_DATA KBC_SDA1

8 7 6 5RN47 SRN2K2J-2-GPD

SMB_DATA


1 C361 1 C360

TXN2 TXP2

SMBus

SML0CLK SML0DATA SML1ALERT#/GPIO74 SML1CLK/GPIO58

MINICARD2


1 C374 1 C372

TXN3 TXP3

PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0#/GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1#/GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P PCIECLKRQ2#/GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3#/GPIO25 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4#/GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5#/GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ#/GPIO56IBEXPEAK-M-GP-NF

Change 4.7K KBC_SCL1 KBC_SDA1

SMB_CLK SMB_DATA

1 2 3 4

3D3V_S0

PCH_GPIO74 17 KBC_SCL1 36 3,21,22 PCH_SMBDATA KBC_SDA1 36 SMB_CLK

1 2 3

6 5 4

SMB_DATA

PCI-E*

SML1DATA/GPIO75 CL_CLK1Link

Controller

PCH_SMBCLK 3,21,22

CL_DATA1 CL_RST1#

check list 100-MHz differential clock from PCH to processor. Connect to PEG_CLK#/PEG_CLK pins of the processor PEG_A_CLKRQ#

Q23 2N7002KDW-GP

84.2N702.A3F

PEG_A_CLKRQ#/GPIO47 CLKOUT_PEG_A_N CLKOUT_PEG_A_P

H1 AD43 AD45 AN4 AN2 AT1 AT3 AW24 BA24 AP3 AP1 F18 E18 AH13 AH12 P41 J42 AH51 AH53 AF38 T45 P43 T42 N50

SBCLK_EXP_N CLK_EXP_P CLKOUT_DP_N CLKOUT_DP_P R308 1 1 R309 Do Not Stuff 2 2 Do Not Stuff TP45 TP46 Do Not Stuff Do Not Stuff CLK_EXP_N_R 5 CLK_EXP_P_R 5C

C

PEG

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P

1 1

From CLK BUFFER

SB MINICARD1 100 MHz MINICARD233 CLK_PCIE_MINI1# 33 CLK_PCIE_MINI1 33 MINI1_CLKREQ# 33 CLK_PCIE_MINI2# 33 CLK_PCIE_MINI2 R299 1 1 R300 1 R35 R301 1 1 R302 1 R130 R303 1 1 R304 1 R158 Do Not Stuff 2 2 Do Not Stuff 2 Do Not Stuff Do Not Stuff 2 2 Do Not Stuff 2 Do Not Stuff Do Not Stuff 2 2 Do Not Stuff 2 Do Not Stuff

14 PCIE_CLK_RQ0# CLK_PCH_SRC1_N CLK_PCH_SRC1_P PCIE_CLK_RQ1# CLK_PCH_SRC2_N CLK_PCH_SRC2_P PCIE_CLK_RQ2# CLK_PCH_SRC3_N CLK_PCH_SRC3_P PCIE_CLK_RQ3#

P9 AM43 AM45 U4 AM47 AM48 N4 AH42 AH41 A8 AM51 AM53

CLKIN_DMI_N CLKIN_DMI_P CLKIN_BCLK_N CLKIN_BCLK_P CLKIN_DOT_96N CLKIN_DOT_96P CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P REFCLK14IN CLKIN_PCILOOPBACK XTAL25_IN XTAL25_OUT XCLK_RCOMP CLKOUTFLEX0/GPIO64

CLK_DMI# 3 CLK_DMI 3 CLK_CPU_BCLK# 3 CLK_CPU_BCLK 3 DREFCLK# 3 DREFCLK 3 CLK_SATA# 3 CLK_SATA 3 CLK_ICH14 3 17 PCH_GPIO28 PCIE_CLK_RQ4# CLK_PCI_FB 16 14 XTAL25_IN XTAL25_OUT XCLK_RCOMP PM_RSMRST# RN9 SRN10KJ-7GP 8 7 6 5 3D3V_S5

33 MIN2_CLKREQ# 31 CLK_PCIE_LAN# 31 CLK_PCIE_LAN 31 LAN_CLKREQ#

LAN

1 2 PEG_B_CLKRQ# 3 4

B

17 PCIE_CLK_RQ1# PCIE_CLK_RQ4#

B

M9 AJ50 AJ52

1

2R37 90D9R2F-1-GP

1D05V_S0

SB14 PCH_GPIO72 PCH_GPIO11 8 PCIE_CLK_RQ3# 7 6 PCIE_CLK_RQ5# 5

33MHZ 33MHZ 33MHZCLK48 R185 33R2J-2-GP 1 2

Clock Flex

PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3VALW. PCIECLKRQ{1,2} should have a 10K pull-up to +1.05VS (But CRB is pull-up to +3VS).

PCIE_CLK_RQ5#

H6 AK53 AK51

CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67

3D3V_S5 RN44 SRN10KJ-7GP 1 2 3 4

2

1

EC38 Do Not Stuff

DY2

R215 1MR2J-1-GP XTAL25_OUT

3D3V_S0 3D3V_S5

1 2 3 4

RN13 SRN10KJ-7GP 8 7 PCIE_CLK_RQ2# 6 5 PEG_A_CLKRQ#

1

2X4 XTAL-25MHZ-102-GP

1

PEG_B_CLKRQ#

P13

48MHZCLK48_Cardreader 30

XTAL25_IN

2 1 C349 SC12P50V2JN-3GP

PCH_GPIO39 17 SUS_PWR_DN_ACK 14,36

2 1 C350 SC12P50V2JN-3GP

82.30020.851 2nd = 82.30020.971

A

JV10 CS CLK_PCIE_LAN CLK_PCIE_LAN# CLK_PCI_FB EC12 Do Not Stuff

SB Hosonic 12P ITTI C349 12P,C350 15P

A

EC7 Do Not Stuff5

EC5 Do Not Stuff


1

1

DY2

DY2

DY2

1

PCH 2 of 9(PCIE/CLK/SMB)Document Number

JV10-CSSheet1

Rev

-113 of 50

Date: Friday, January 22, 20104 3 2

5

4

3

2

1

PCH1C 4 4 4 4D

3 OF 10 FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT FDI_FSYNC0 FDI_FSYNC1 BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 BJ14 BF13 BH13 BJ12 BG14 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

BC24 BJ22 AW20 BJ20 BD24 BG22 BA20 BG20 BE22 BF21 BD20 BE18 BD22 BH21 BC20 BD18 BH25

DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP DMI_ZCOMP DMI_IRCOMP

4 4 4 4 4 4 4 4 3D3V_S5 RN11 SRN10KJ-7GP 1 2 3 4 4 4 4 4 PCH_GPIO12 17 PCIE_WAKE# 31,33 EC_SWI# 17,36 PCH_GPIO57 17 1D05V_S0 1 2

D

8 7 6 5

FDI_INT 4 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 4 4 4 4C

DMI

DMI_IRCOMP_R

BF25

FDI

R51 49D9R2F-GP

FDI_LSYNC0 FDI_LSYNC1

C

Delete PM_PWRBTN# pull high3D3V_S5 3D3V_S0 RN50 SRN10KJ-7GP 1 2 PM_SYSRST#_R 3 AC_PRESENT 4 PM_SYSRST#_R T6 M6 SATA_LED# 12,27 PCIE_CLK_RQ0# 13 41 CORE_PWRGD 17 PM_PWROK_1 1 R165 2 Do Not Stuff R22 1 R162 1KR2F-3-GP 1 1 36 RSMRST#_KBC 3 PM_RSMRST# 13,36 SUS_PWR_DN_ACK R157 100KR2J-1-GP 2 D18 Do Not Stuff 2 1 M1 P5 P7 A6 F14 2 1 2 Do Not Stuff ME_PWROK B17 K5 A10 D9 C16 SYS_RESET# SYS_PWROK PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST# WAKE# CLKRUN#/GPIO32 J12 Y1 PCIE_WAKE# 31,33 8 7 6 5 PM_CLKRUN# 17,36

System Power Management

SUS_STAT#/GPIO61 SUSCLK/GPIO62 SLP_S5#/GPIO63 SLP_S4# SLP_S3# SLP_M# TP23 PMSYNCH SLP_LAN#/GPIO29

P8 F3 E4 H7 P12 K8 N2 BJ10 F6

LAN_RST#1

PM_SUS_CLK 26,36

R167 10KR2J-3-GP

5 PM_DRAM_PWRGD 13 PM_RSMRST#

2B

PM_SLP_S4# 36,43 PM_SLP_S3# 23,26,36,39,43,44 PM_SLP_M# 36

B

DY

Add RTC Data lose function DY D2

SUS_PWR_DN_ACK/GPIO30 PWRBTN# ACPRESENT/GPIO31 BATLOW#/GPIO72 RI# IBEXPEAK-M-GP-NF

36,49 PM_PWRBTN# 36 AC_PRESENT 13 17 PCH_GPIO72 PM_RI#

Do Not Stuff 2nd = 83.BAT54.N81 3nd = 83.00054.T813D3V_AUX_S5

H_PM_SYNC 5

1

R12 10KR2J-3-GP 2 PM_RSMRST#

1 R11 100KR2J-1-GP 2 3 2 1

4A

JV10 CS 51123_PGOOD 42

5 6 Q4


A

2N7002KDW-GP

84.2N702.A3F 2ND = 84.DM601.03F

All_PWRGD modify 51123_PGOOD from 3V/5V power

PCH 3 of 9(DMI/FDI)Document Number

JV10-CSSheet1

Rev

-114 of 50


5

4

3

2

1

Panel backlight enable control for LVDS used to gate power into the backlight circuit SBPCH1DD

4 OF 10

36 KBC_BL_ON_IN

R34

1

2 Do Not Stuff 3 4

PCH_BL_ON PCH_LCDVDD_ON

PCH_BL_ON 23 PCH_LCDVDD_ON 23 L_BKLTCTL

T48 T47 Y48 AB48 Y45 AB46 V48 AP39 AP41 AT43 AT42

L_BKLTEN L_VDD_EN L_BKLTCTL L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK

SDVO_TVCLKINN SDVO_TVCLKINP SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP

BJ46 BG46 BJ48 BG48 BF45 BH45

D

RN14 SRN100KJ-6-GP

23 CLK_DDC_EDID 23 DAT_DDC_EDID LCTL_CLK LCTL_DATA R45 2 2K37R2F-GP

2 1

1

LIBG

SDVO_CTRLCLK SDVO_CTRLDATA DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

T51 T53 BG44 BJ44 AU38 BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 Y49 AB49 BE44 BD44 AV40 BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36

PCH_HDMI_CLK 25 PCH_HDMI_DATA 25

3D3V_S0 RN16 SRN2K2J-2-GP 8 7 6 5

23 LVDS_TXACLK23 LVDS_TXACLK+ 23 LVDS_TXAOUT023 LVDS_TXAOUT123 LVDS_TXAOUT223 LVDS_TXAOUT0+ 23 LVDS_TXAOUT1+ 23 LVDS_TXAOUT2+

AV53 AV51 BB47 BA52 AY48 AV47 BB48 BA50 AY49 AV48 AP48 AP47 AY53 AT49 AU52 AT53 AY51 AT48 AU50 AT51

LVDS

1 2 3 4C

LCTL_DATA CLK_DDC_EDID LCTL_CLK DAT_DDC_EDID

PCH_HDMI_DETECT 25 PCH_HDMI_DATA2-_L PCH_HDMI_DATA2+_L PCH_HDMI_DATA1-_L PCH_HDMI_DATA1+_L PCH_HDMI_DATA0-_L PCH_HDMI_DATA0+_L PCH_HDMI_CLK-_L PCH_HDMI_CLK+_L C363 C362 C365 C364 C353 C354 C355 C368

Digital Display Interface

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2

SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP

PCH_HDMI_DATA2- 25 PCH_HDMI_DATA2+ 25 PCH_HDMI_DATA1- 25 PCH_HDMI_DATA1+ 25 PCH_HDMI_DATA0- 25 PCH_HDMI_DATA0+ 25 PCH_HDMI_CLK- 25 PCH_HDMI_CLK+ 25

C

B

B

RN55 SRN150F-1-GP

8 7 6 5

1 2 3 4

CRT_BLUE CRT_GREEN CRT_RED

24 CRT_BLUE 24 CRT_GREEN 24 CRT_RED 24 CRT_DDCCLK 24 CRT_DDCDATA 24 CRT_HSYNC 24 CRT_VSYNC

AA52 AB53 AD53 V51 V53 Y53 Y51 AD48 AB51

CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN

U50 U52 BC46 BD46 AT38 BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36JV10 CS

1

2

CRT_IREF

R38 1KR2D-1-GP

IBEXPEAK-M-GP-NF

1K 0.5% ohmA

CRT


A

PCH 4 of 9(LVDS/CRT/DP)Document Number

JV10-CSSheet1

Rev

-115 of 50


5

4

3

2

1

PCH1E RN43 SRN8K2J-2-GP-U PCI_FRAME# PCI_REQ1# PCI_TRDY# INT_PIRQH# 3D3V_S0D

5 OF 10

1 2 3 4 5

10 9 dGPU_SELECT# INT_PIRQD# 8 PCI_STOP# 7 PCI_IRDY# 6

3D3V_S0

These pins are left as NC, because the function is disable.RN49 SRN8K2J-2-GP-U

3D3V_S0

3D3V_S0

1 2 3 4

RN46 SRN8K2J-4-GP 8 PCI_SERR# 7 INT_PIRQA# 6 INT_PIRQE# 5 INT_PIRQC#

NVRAM

PCI_REQ0# INT_PIRQB# INT_PIRQF# PCI_REQ3#

1 2 3 4 5

3D3V_S0 10 9 PCI_PLOCK# INT_PIRQG# 8 7 PCI_DEVSEL# PCI_PERR# 6

PCI

H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 J50 G42 H47 G34

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# PIRQA# PIRQB# PIRQC# PIRQD# REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 NV_DQS0 NV_DQS1 NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8 NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15 NV_ALE NV_CLE NV_RCOMP NV_RB# NV_WR#0_RE# NV_WR#1_RE# NV_WE#_CK0 NV_WE#_CK1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS#

AY9 BD1 AP15 BD8 AV9 BG8 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 BD3 AY6 AU2 AV7 AY8 AY5 AV11 BF5 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 B25 D25 N16 J16 F16 L16 E14 G16 F12 T15D

These pins are left as NC, because the function is disable.

USB TablePair 0 1USBPN0 USBPP0 USBPN1 USBPP1 USBPN3 USBPP3 USBPN4 USBPP4 29 29 29 29 33 33 23 23

Device USB3 USB2 NC MINICARD1 WECAM NC NC NC 3G USB1(HS) NC Blue Tooth MINIC2(3G) CardreaderB C

C

PCI_GNT0# PCI_GNT1#

1 1

DY DY

2 2

SamBOOT BIOS Strap PCI_GNT#0 PCI_GNT#1

R15 Do Not Stuff R21 Do Not Stuff

USE SPI

INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# PCI_REQ0# PCI_REQ1# dGPU_SELECT# PCI_REQ3# PCI_GNT0# PCI_GNT1#

G38 H51 B37 A44 F51 A46 B45 M53 F48 K45 F36 H53 B41 K53 A36 A48 K6

2 3 4 5 6 7 8 9 10 11 12 13SB

3D3V_S0 Pull up 8.2k?BOOT BIOS Location

0 1 0 1

0 0 1 1

LPC(Default) Reserved PCI SPI

INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#

PCIRST# SERR# PERR# IRDY# PAR DEVSEL# FRAME# PLOCK# STOP# TRDY# PME# PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4IBEXPEAK-M-GP-NF

PCI_SERR# PCI_PERR# PCI_IRDY#B

E44 E50 A42 H44 F46 C46 D49 D41 C48 M7 D5

USB

USBPN8 USBPP8 USBPN9 USBPP9 USBPN11 USBPP11 USBPN12 USBPP12 USBPN13 USBPP13

33 33 38 38 38 38 33 33 30 30

PCI_DEVSEL# PCI_FRAME# 5,31,33,36,37,39,49 PLT_RST#

Modify SIV USB report

1

PCI_PLOCK# PCI_STOP# PCI_TRDY#

USB_RBIAS_PN

R14 DYDo Not Stuff

1

2

USBRBIAS OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14

2

R166 22D6R2F-L1-GP 3D3V_S5

37 13 36 CLK_PCI_KBC

PCLK_FWH CLK_PCI_FB R29

2 1 1

3 4 2 47R2J-2-GP

CLK_PCI_SIO_R CLK_PCI_FB_R CLK_PCI_KBC_R

2R27 10KR2J-3-GP USB_OC#0 JV10 CSA

RN53 SRN22-3-GP

N52 P53 P46 P51 P48

A

PCLK_FWH

CLK_PCI_KBC

1

EC39 Do Not Stuff

1


1

DY2

DY2


PCH 5 of 9(PCI/USB)Document Number

JV10-CSSheet1

Rev

-116 of 50


5

4

3

2

1

GPIO8 has a weak[20K] internal pull up. No need to have external pull down/up. GPIO8 pin set to high at reset.PCH_GPIO0

PCH1F

6 OF 10

Y3 C38 D37 J32 F10 K9

D

MISC

GPIO15 has a weak[20K] internal pull down. No need to have external pull up/down. GPIO 15 pin is set to low at reset. Low : ME Crypto TLS with no confidentiality High : ME Crypto TLS with confidentiality

BMBUSY#/GPIO0 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 SATA4GP/GPIO16 TACH0/GPIO17

EC_SMI# PX_HDMI# 36 EC_SCI# EC_SWI#

CLKOUT_PCIE6N CLKOUT_PCIE6P

AH45 AH46

CLKOUT_PCIE7N CLKOUT_PCIE7P

AF48 AF47

D

14,36

GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.

14 PCH_GPIO12 PCH_GPIO15 PCH_GPIO16 12 PCH_GPIO17 PCH_GPIO22 Do Not Stuff Do Not Stuff TP2 TP5

A20GATE

U2

KA20GATE 36

T7 AA2 F38 Y7 H10 AB12 V13

SBDo Not Stuff 2 2 Do Not Stuff BCLK_CPU_N 5 BCLK_CPU_P 5

CLKOUT_BCLK0_N/CLKOUT_PCIE8N CLKOUT_BCLK0_P/CLKOUT_PCIE8P

AM3 AM1 BG10 T1 BE10 BD10

BCLK_CPU_N_R BCLK_CPU_P_R

R310 1 1 R311

3D3V_S5 3D3V_S5

1 1

PCH_GPIO24 PCH_GPIO27

GPIO

RN10 SRN10KJ-7GP

SCLOCK/GPIO22 GPIO24 GPIO27 GPIO28 STP_PCI#/GPIO34

PECI RCIN#

H_PECI 5 KBRCIN# 36 H_PWRGD 5,49 RN22 SRN56J-4-GP 4 3

CPU

4 3 2 1

5 6 7 8

PCH_GPIO74 13 PCH_GPIO60 13 PM_PWROK_1 14 PM_RI# 14

PROCPWRGD THRMTRIP#

13 PCH_GPIO28 STP_PCI#

To CPUPCH_THERMTRIP_R

1 2

1D05V_S0

M11 V6 AB7 AB13

RN48 Do Not Stuff 4 1 3 DY 2

PCH_GPIO35 PCH_GPIO45 PCH_GPIO46 PCH_GPIO36 12 PCH_GPIO37 PCH_GPIO38

SATACLKREQ#/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 SLOAD/GPIO38 SDATAOUT0/GPIO39 PCIECLKRQ6#/GPIO45 PCIECLKRQ7#/GPIO46 SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_28 VSS_NCTF#A4 VSS_NCTF#A49 VSS_NCTF#A5 VSS_NCTF#A50 VSS_NCTF#A52 VSS_NCTF#A53 VSS_NCTF#B2 VSS_NCTF#B53 VSS_NCTF#BE1 VSS_NCTF#BE53 VSS_NCTF#BF1 VSS_NCTF#BF53 VSS_NCTF#BH1 VSS_NCTF#BH53 VSS_NCTF#BJ1 VSS_NCTF#BJ2 VSS_NCTF#BJ4 VSS_NCTF#BJ49 VSS_NCTF#BJ5 VSS_NCTF#BJ50 VSS_NCTF#BJ52 VSS_NCTF#BJ53 VSS_NCTF#D1 VSS_NCTF#D53 VSS_NCTF#E1 VSS_NCTF#E53 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 BA22 AW22 BB22

1 DY 2 R52 Do Not Stuff

PM_THRMTRIP-A# 5,39

DY?C

V3 P3

C

R33 1KR2J-1-GP 2 1

13 PCH_GPIO39 PCH_GPIO15 PCH_GPIO45 PCH_GPIO46

AY45 AY46 AV43 AV45 AF13 M18 N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39 P6 C10B

H3 F1 AB6 AA4 F8 B4 B52 BH2 BH52 D2 A4 A49 A5 A50 A52 A53 1 B2 B53 BE1 BE53 BF1 BF53 BH1 BH53 1 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 1 BJ53 D1 D53 E1 E53

3D3V_S0

PASSWORD CLEAR2RN54 SRN10KJ-7GP Do Not Stuff Do Not Stuff

PCH_GPIO48 PSW_CLR#

1

4 3 2 13D3V_S0

5 6 7 8

PCH_GPIO36 PCH_GPIO48 PCH_GPIO16 PM_CLKRUN# 14,36

14

PCH_GPIO57

G91

NCTF

RSVD

TP12 TP13

NCTF TEST PIN: A4,A49,A5,A50,A52,A53,B2,B53,BE1, BE53,BF1,BF53,BH1,BH53,BJ1,BJ2,BJ4, BJ49,BJ5,BJ50,BJ52,BJ53,D1,D53,E1,E53

RN51 SRN10KJ-7GP

4 3 2 1

5 6 7 8

PSW_CLR# PCH_GPIO35 SATA_DET#1_R 12 PCIE_CLK_RQ1# 13 TP13 Do Not Stuff

TP14 TP15 TP16 TP17 TP18 TP19 NC_1 NC_2 NC_3 NC_4 NC_5 INIT3_3V# TP24

TP12 Do Not Stuff

1

B

RP1 SRN10KJ-L3-GP PX_HDMI# EC_SMI# PCH_GPIO22 PCH_GPIO38 3D3V_S0

1 2 3 4 5

10 9 8 7 6

3D3V_S0

EC_SCI# STP_PCI# PCH_GPIO0

TP19 Do Not Stuff

TP18 Do Not Stuff

IBEXPEAK-M-GP-NF

A

JV10 CS

A


PCH 6 of 9(GPIO/RSVD)Document Number

JV10-CSSheet1

Rev

-117 of 50


5

4

3

2

1

U33 G9091-330T11U-GP 1D05V_S0 5V_S0

1.432AD

PCH1G AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31 VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE

POWERCRT

3D3V_S0_DAC 7 OF 10 VCCADAC VCCADAC VSSA_DAC VSSA_DAC AE50 AE52 2 AF53 AF51

74.09091.J3F 2nd = 74.09198.G7F 3nd = 74.07716.A7F1 2 3 VIN GND EN VOUT NC#4 5

3D3V_S0_DAC

69mA1 1 C346 SCD1U10V2KX-5GP C347 1 SCD01U16V2KX-3GP C313 SC1U16V3ZY-GP 2

D

1

1

1


C71 SC1U6D3V2KX-GP

4 2

C345 SC1U16V3ZY-GP

1 2


2

2

VCC CORE

2

Imax = 300 mA

VCCALVDS VSSA_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS

AH38 AH39 AP43 AP45 AT46 AT45

300mA 59mA1 C92 SCD01U16V2KX-3GP SCD01U16V2KX-3GP 2

3D3V_S0

1D05V_S0 AK24 TP23 Do Not Stuff 1 BJ24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 AN30 AN31 AN35 AT22 1D05V_S0 TP22 1 Do Not Stuff BJ18 AM23 1 C82 SC1U6D3V2KX-GP IBEXPEAK-M-GP-NF VCCIO VCCAPLLEXP

VCCTX_LVDS 1 C91 SC10U6D3V3MX-GP SC10U6D3V3MX-GP

L2 IND-1UH-2-GP 1

1D8V_S0 2

LVDS

1D05V_S0C

3.062A1 1 1 1 C99 SC10U6D3V3MX-GP SC10U6D3V3MX-GP C73 SC1U6D3V2KX-GP C77 SC1U6D3V2KX-GP C72 SC1U6D3V2KX-GP 1 C75 SC1U6D3V2KX-GP 2 2 2 2 2

VCC3_3 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCC3_3 VCCVRM[1] VCCFDIPLL

AB34 AB35 AD35

2

C

HVCMOS

VCC3_3 VCC3_3

357mA1 2

3D3V_S0 C70 SCD1U10V2KX-5GP 1D8V_S0 2 1D5V_S0_1D8V_S0 1D5V_S0 1

SB1D5V_S0_1D8V_S0

VCCVRM

AT24 AT16 AU16

196mA 61mA1 2

R47 Do Not Stuff 1 DY 2 R49 Do Not Stuff

DMI

VCCDMI VCCDMI

1D05V_S0 C80 SC1U6D3V2KX-GP

PCI E*

B

3D3V_S0

NAND / SPI

357mA1D5V_S0_1D8V_S0

1

C79 SCD1U10V2KX-5GP

VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND

1

AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15

VCCPNAND which power the DC NAND interface must be powered even if dual channel NAND interface is not connected since it also supplies power to other functions inside PCH.1D8V_S0

B

156mAC84 SCD1U10V2KX-5GP 2

2

FDI

VCCIO

VCCME3_3 VCCME3_3 VCCME3_3 VCCME3_3

AM8 AM9 AP11 AP9

3D3V_S0

85mA1 2 C88 SCD1U10V2KX-5GP JV10 CSA

A

2


PCH 7 of 9(PWR/VCORE/LVDS)Document Number

JV10-CSSheet1

Rev

-118 of 50


5

4

3

2

1

PCH1J TP17

POWER

10 OF 10

1D05V_S0

1

AP51 AP53 AF23 AF24

VCCACLK VCCACLK VCCLAN VCCLAN DCPSUSBYP VCCME VCCME VCCME VCCME VCCME VCCME

Do Not Stuff

VCCIO VCCIO VCCIO VCCIO VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCIO V5REF_SUS

V24 V26 Y24 Y26 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 U23 V23 F24

1 2

C93 SC1U6D3V2KX-GP 3D3V_S5D

D

1

1

DCPSUSBYP

Y20 AD38

C57 SCD1U10V2KX-5GP

C50 SC1U6D3V2KX-GP

1 2

C43 SC1U6D3V2KX-GP

2

SCD1U10V2KX-5GP

1

AD411D05V_S0

1.849A1 1C61 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C62 SC1U6D3V2KX-GP

AF43 AF41 AF42 V39 V41 V42 Y39 Y41 Y42

1

USB

2

AD39

C63 SC10U6D3V3MX-GP

3D3V_S5 3D3V_S5 C59

2

2

2

VCCME VCCME VCCME VCCME VCCME

Clock and Miscellaneous

SC1U6D3V2KX-GP 2 1

VCCME

2

C68

2D16 Do Not Stuff

DY11D05V_S0

3D3V_S0

Do Not Stuff5V_S5

1D05V_S0 C67

2 1 100R2J-2-GPC47 SCD1U10V2KX-5GP

5VALW_PCH_VCC5REFSUS

1

1

SCD1U10V2KX-5GP 1D5V_S0_1D8V_S0 1D05V_VCCA_A_DPL

2

2

VCCVRM VCCADPLLA VCCADPLLA VCCADPLLB VCCADPLLB VCCIO VCCIO VCCIO VCCIO

PCI/GPIO/LPC

AU24 BB51 BB53 BD51 BD53 AH23 AJ35 AH35 AF34

V5REF VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3

K49 J38 L38 1 M36 2 N36 P36 U35 AD13 1C69 SCD1U10V2KX-5GP 3D3V_S0 C58 SCD1U10V2KX-5GP 3D3V_S0

5VS_PCH_VCC5REF

2

L3 IND-10UH-215-GP


C351 SC1U6D3V2KX-GP

2

1

VCCRTCEXT

V9

DCPRTC

1

1

C

1

2

1D05V_VCCA_A_DPL

1mA 1mA

2 R149

DY

D2 Do Not Stuff

Do Not Stuff5V_S0

C

DY

1 100R2J-2-GP 1C51

R23

2

68mA 69mAVCCIO_1

1

2 1C97 Do Not Stuff Do Not Stuff

1D05V_VCCA_B_DPL

L4 IND-10UH-215-GP

1

1D05V_S0

1D05V_VCCA_B_DPL

C352 SC1U6D3V2KX-GP

DY2

2

1

C74 SC1U6D3V2KX-GP

1

C94 SC1U6D3V2KX-GP

2 R315 1 Do Not Stuff 2 R316 1 Do Not Stuff

2

2

VCCIO_2

AH34 AF32 V12SC1U6D3V2KX-GP

VCCIO VCCIO DCPSST VCCSATAPLL VCCSATAPLL AK3 AK1

1

-12

C95

1

+VCCSST

TP16 Do Not Stuff

2

1

1D05V_S0

C65

Y22

DCPSUS VCCIO

1

2

B

1

C64

3D3V_S5

AH22 AT20 AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22 AD22 AA34 Y34 Y35 AA35 L30 1C41 SC1U6D3V2KX-GP SC1U6D3V2KX-GP 1D05V_S0

2

SC1U6D3V2KX-GP

2

C60 SCD1U10V2KX-5GP

PCI/GPIO/LPC

VCCSUS3_3 VCCSUS3_3 VCCSUS3_3

SATA

C55 SCD1U10V2KX-5GP 1D05V_S0

1

2

CPU

1

C367 SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP

1

2

2

HDA

A12 1C303 SCD1U10V2KX-5GP

VCCRTC

RTC

2

A

2

SCD1U10V2KX-5GP SCD1U10V2KX-5GP

163mA1

C81 SC1U6D3V2KX-GP

B

SCD1U10V2KX-5GP

2

P18 U19 U20 U223D3V_S0

VCCSUS3_3

VCCVRM VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCME VCCME VCCME VCCME VCCSUSHDA

1D5V_S0_1D8V_S0

V15 V16 Y16

VCC3_3 VCC3_3 VCC3_3

AT18C357 SCD1U10V2KX-5GP

V_CPU_IO V_CPU_IO

AU18RTC_AUX_S5

23D3V_S5 R288 Do Not Stuff 1 DY 2 IBEXPEAK-M-GP-NF

-11D5V_S0

1R289 Do Not Stuff

2A

JV10 CS


PCH 8 of 9(PWR\SATA\USB)Document Number

JV10-CSSheet1

Rev

-119 of 50


5

4

3

2

1

PCH1I

9 OF 10

D

C

B

A

AY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16 E20 E24 E30 E34 E38 E42 E46 E48 E6 E8 F49 F5 G10 G14 G18 G2 G22 G32 G36 G40 G44 G52 AF39 H16 H20 H30 H34 H38 H42

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

H49 H5 J24 K11 K43 K47 K7 L14 L18 L2 L22 L32 L36 L40 L52 M12 M16 M20 N38 M34 M38 M42 M46 M49 M5 M8 N24 P11 AD15 P22 P30 P32 P34 P42 P45 P47 R2 R52 T12 T41 T46 T49 T5 T8 U30 U31 U32 U34 P38 V11 P16 V19 V20 V22 V30 V31 V32 V34 V35 V38 V43 V45 V46 V47 V49 V5 V7 V8 W2 W52 Y11 Y12 Y15 Y19 Y23 Y28 Y30 Y31 Y32 Y38 Y43 Y46 P49 Y5 Y6 Y8 P24 T43 AD51 AT8 AD47 Y47 AT12 AM6 AT13 AM5 AK45 AK39 AV14

PCH1H

8 OF 10

AB16 AA19 AA20 AA22 AM19 AA24 AA26 AA28 AA30 AA31 AA32 AB11 AB15 AB23 AB30 AB31 AB32 AB39 AB43 AB47 AB5 AB8 AC2 AC52 AD11 AD12 AD16 AD23 AD30 AD31 AD32 AD34 AU22 AD42 AD46 AD49 AD7 AE2 AE4 AF12 Y13 AH49 AU4 AF35 AP13 AN34 AF45 AF46 AF49 AF5 AF8 AG2 AG52 AH11 AH15 AH16 AH24 AH32 AV18 AH43 AH47 AH7 AJ19 AJ2 AJ20 AJ22 AJ23 AJ26 AJ28 AJ32 AJ34 AT5 AJ4 AK12 AM41 AN19 AK26 AK22 AK23 AK28

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSIBEXPEAK-M-GP-NF

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AK30 AK31 AK32 AK34 AK35 AK38 AK43 AK46 AK49 AK5 AK8 AL2 AL52 AM11 BB44 AD24 AM20 AM22 AM24 AM26 AM28 BA42 AM30 AM31 AM32 AM34 AM35 AM38 AM39 AM42 AU20 AM46 AV22 AM49 AM7 AA50 BB10 AN32 AN50 AN52 AP12 AP42 AP46 AP49 AP5 AP8 AR2 AR52 AT11 BA12 AH48 AT32 AT36 AT41 AT47 AT7 AV12 AV16 AV20 AV24 AV30 AV34 AV38 AV42 AV46 AV49 AV5 AV8 AW14 AW18 AW2 BF9 AW32 AW36 AW40 AW52 AY11 AY43 AY47

D

C

B

JV10 CS

A


IBEXPEAK-M-GP-NF

PCH 9 of 9(VSS)Document Number

JV10-CSSheet1

Rev

-120 of 50


5

4

3

2

1

6

M_A_A[15..0] M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

DM1

D

6 6 6 6

M_A_BS2 M_A_BS0 M_A_BS1 M_A_DQ[63..0]

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2DDR3-204P-92-GP

NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 1 197 201 2 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206C209 SCD1U10V2KX-5GP M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SODIMM0_1_SMB_DATA_R SODIMM0_1_SMB_CLK_R M_A_RAS# 6 M_A_WE# 6 M_A_CAS# 6 M_CS#0 6 M_CS#1 6 M_CKE0 6 M_CKE1 6 M_CLK_DDR0 6 M_CLK_DDR#0 6 M_CLK_DDR1 6 M_CLK_DDR#1 6 M_A_DM[7..0] 6

Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30 If SA0 DIM0 = 1, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA2 SO-DIMMA TS Address is 0x32

D

C

B

Layout NoteNear Pin 126DDR_VREF_S3_1

C399 Do Not Stuff C85 Do Not Stuff

C400 SCD1U16V2ZY-2GP 6 M_A_DQS#[7..0]

DY2 2

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120

R76 R79

1 1

2 Do Not Stuff 2 Do Not Stuff3D3V_S0

PCH_SMBDATA 3,13,22 PCH_SMBCLK 3,13,22

PM_EXTTS#0_R 5

2

C204 Do Not Stuff

DY1

1D5V_S3

C

1D5V_S3

SODIMM A DECOUPLING -1C386 SC10U10V5ZY-1GP C398 SC10U10V5ZY-1GP C170 SC10U10V5ZY-1GP

del C129 C183 modify C386,C398,C170

1

1

2

2

1

1

1

1

1

1 2

C393 SC1U10V2KX-1GP

C138 SC1U10V2KX-1GP

C396 SC1U10V2KX-1GP

C388 SCD1U10V2KX-5GP

2

1



2

2

2

2

2

B

1

1

6 M_A_DQS[7..0]

Layout NoteNear Pin 1DDR_VREF_S3_1

C86 SCD1U16V2ZY-2GP

DY2 2

6 6

M_ODT0 M_ODT1 DDR_VREF_S3_1

1

1

A

126 1 30 203 204

A

5,22 DDR3_DRAMRST# DDR_VREF_S3

JV10 CS


C212 SC1U6D3V2KX-GP

Layout Note: Place these Caps near SO-DIMMA.Title Size Custom

1

1

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.

2

2

62.10017.U91 2nd = 62.10017.P313nd = 62.10017.N91

DDR3 SODIMM1Document Number

JV10-CSSheet1

Rev

-121 of 50

Date: Friday, January 22, 20103 2

5

4

5

4

3

2

1

6

M_B_A[15..0] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

DM2

D

6 6 6 6

M_B_BS2 M_B_BS0 M_B_BS1 M_B_DQ[63..0]

98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2DDR3-204P-41-GP-U

NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 1SA1_DIM1 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SODIMM1_1_SMB_DATA_R SODIMM1_1_SMB_CLK_R M_B_RAS# 6 M_B_WE# 6 M_B_CAS# 6 M_CS#2 6 M_CS#3 6 M_CKE2 6 M_CKE3 6 M_CLK_DDR2 6 M_CLK_DDR#2 6 M_CLK_DDR3 6 M_CLK_DDR#3 6 M_B_DM[7..0] 6D

C

REVERSE TYPE

Layout NoteNear Pin 1B

DDR_VREF_S3_1


C89 6 M_B_DQS#[7..0] SCD1U16V2ZY-2GP

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120

R75 R78

1 1

2 Do Not Stuff 2 Do Not StuffPM_EXTTS#1_R 5

PCH_SMBDATA 3,13,21 PCH_SMBCLK 3,13,21 3D3V_S0

1

2 2

C208 SCD1U16V2ZY-2GP

1

C207 Do Not Stuff

1D5V_S3

R77 10KR2J-3-GP

DY2

C

1D5V_S3

SODIMM B DECOUPLING

-1 modify C184,C397,C391,C130

1

1

1

1





1 2


2

2

2

2

B

1

DY2 2

1

1

1

1

1

1

2

2

2

2

2

6 M_B_DQS[7..0]

Layout NoteNear Pin 1266 6 DDR_VREF_S3_1A

M_ODT2 M_ODT3 DDR_VREF_S3_1

126 1 30 203 204

2

1

C387 SC1U10V2KX-1GP SC1U10V2KX-1GP

C389 SC1U10V2KX-1GP

C394 SC1U10V2KX-1GP SC1U10V2KX-1GP


C171 SCD1U10V2KX-5GP SCD1U10V2KX-5GP


5,21 DDR3_DRAMRST#

A


C193 DDR_VREF_S3 SCD1U16V2ZY-2GP

JV10 CS

1

DY2 2

1


C214 SC1U6D3V2KX-GP


1

2

2

1

62.10017.N41 2nd = 62.10017.P41 3nd = 62.10017.V01

DDR3 SODIMM2Document Number

H = 5.2mm3 2

JV10-CSSheet1

Rev

-122 of 50

Date: Friday, January 22, 20105 4

5

4

3

2

1

CCD PinBLON_OUT_R 1 LCD1 IPEX-CON40-4-GP DCBATOUT_LCD1 1 1 C286 Do Not Stuff

Pin2 1 R145 1KR2F-3-GP R146 100KR2J-1-GP 2 BLON_OUT 36

Symbol CCD_PWR USBUSB+ GND NCD

1 2 3 4 5

2 RFC2 SCD1U16V2ZY-2GP 1 C288 SC10U35V0ZY-GP

1 F2 POLYSW-1D1A24V-1-GP

DCBATOUT

DY2

20.F1703.040D

-142

3G2

47 NP2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NP1 41 43 LCDVDD

69.50007.A41 2nd = 69.50007.A31

2

DBC_EN BLON_OUT_R BRIGHTNESS_CN CCD_PWR USBPN4 USBPP4 16 16

2 1 1 1 1 C291 SC4D7U10V5ZY-3GP SC4D7U10V5ZY-3GP C301 RFC3 Do Not Stuff Do Not Stuff SC1200P50V2KX-1GP RFC4 SC22P50V2JN-4GP 1 2 3D3V_S0 BRIGHTNESS_CN 1 C287 Do Not Stuff 2

R147 Do Not Stuff DY 1 1 R148 33R2J-2-GP

BRIGHTNESS 36 L_BKLTCTL 15

D MIC Pin Pin 1 2 3 4 Symbol DMIC_DAT 3D3V_S0_DMIC DMIC_CLK GNDC

46

DY2

3G2

3G2

F3 FUSE-1D1A6V-4GP-U

69.50007.691 69.50007.771

DY2

DMIC_CLK 34 DMIC_DAT 34 3D3V_S0_DMIC

2

SB

-1

C

45

SWAP Pin defineLVDS_TXAOUT0- 15 LVDS_TXAOUT0+ 15 LVDS_TXAOUT1- 15 LVDS_TXAOUT1+ 15 LVDS_TXAOUT2- 15 LVDS_TXAOUT2+ 15 LVDS_TXACLK- 15 LVDS_TXACLK+ 15 LCD_EDID_DAT LCD_EDID_CLK 3D3V_S0 RN42 SRN33J-5-GP-U 3 2 4 1 3D3V_S0

For Digital Mic PowerSBDBC_EN 1 R318 Do Not Stuff 2 1 U32

DY5V_S0

SBDY2

R156 Do Not Stuff 3D3V_S0_DMIC 1 RFC5 SC22P50V2JN-4GP 1 C299 SC1U10V2KX-1GP

Do Not Stuff

Do Not Stuff 2nd = 74.09198.G7F5 4 VOUT NC#4 VIN GND EN 1 2 3

44

DAT_DDC_EDID CLK_DDC_EDID

15 15

1

-1

PM_SLP_S3# 14,26,36,39,43,44 C310

3G2 2

DY Do Not Stuff2B

B

-1RFC6 SC1200P50V2KX-1GP C39

Layout 40 mil

1

1

3G2 2

-1 place near LVDS Conn.LVDS_TXAOUT0LVDS_TXAOUT0+ LVDS_TXAOUT1LVDS_TXAOUT1+ LVDS_TXAOUT2LVDS_TXAOUT2+ 1 2 RFC25 Do Not Stuff 1 DY 2 RFC26 Do Not Stuff 1 2 RFC27 DY Do Not Stuff 1 2 RFC28 DY Do Not Stuff 1 DY 2 RFC29 Do Not Stuff 1 2 RFC30 DY Do Not Stuff 15 PCH_LCDVDD_ON LCDVDD 1 C290 SC4D7U6D3V3KX-GP 1 2 3

U30 G5285T11U-GP

2

2

SCD1U16V2ZY-2GP

74.05285.07F 2nd = 74.09724.09FEN GND OUT IN#5 IN#4 5 4

3D3V_S0

1

C281 SC4D7U6D3V3KX-GP

JV10 CS

A

DY

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Custom Document Number

A

LCD CCD CONN JV10-CSSheet1

Rev

-123 of 50


5

4

3

2

1

Layout Note: Place these resistors close to the CRT-out connector

Hsync & Vsync level shiftFerrite bead impedance: 10 ohm@100MHzL8 SBK160808T-100Y-N-GP 5V_S0

68.00119.08115D

CRT_RED

1

2

CRT_R

1C6 SCD1U16V2ZY-2GP

2nd = 68.00230.021L7 SBK160808T-100Y-N-GP 68.00119.081 1

For System CRTD

2

15

CRT_GREEN

2

CRT_G 15 CRT_VSYNC 5V_S0

RN1 SRN33J-5-GP-U

14

2nd = 68.00230.021

1

15

CRT_BLUE

L6 SBK160808T-100Y-N-GP 68.00119.081 1

2

3U25A TSAHCT125PW-GP

CRT_VSYNC1_1

2 1

3 4

CRT_VSYNC1 CRT_HSYNC1

1

1

14

8 7 6 5

1

1

1



C263 SC6D8P50V2DN-GP SC6D8P50V2DN-GP SC6D8P50V2DN-GP

2

2

2

RN36 SRN150F-1-GP

DY

DY

DY

2

2

2

4

C268

C265

1

2nd = 68.00230.021

C262

7

2

CRT_B

73.74125.L13 2ND = 73.74125.L126CRT_HSYNC1_1

Do Not Stuff Do Not Stuff

15 CRT_HSYNC

5

1 2 3 4

7

U25B TSAHCT125PW-GP

73.74125.L13 2ND = 73.74125.L12

C

Layout Note: * Must be a ground return path between this ground and the ground on the VGA connector. Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.

C

DDC_CLK & DATA level shift5V_CRT_S0

5V_S0

A3D3V_S0

D1 RB551V-30-2GP

83.5R003.08F 2nd = 83.R5003.C8F 3nd = 83.R2004.C8F

4 3

F1 FUSE-1D1A6V-4GP-U 69.50007.691 2ND = 69.50007.771 5V_CRT_DDC 1 2 RN6 SRN2K2J-1-GP

K3D3V_S0

4 3 2 13D3V_S0 RN37 SRN10KJ-7GP

CRT I/F & CONNECTOR1 2B

5 6 7 8

CRT1 D-SUB-15-39-GP-U

20.20859.015DAT_DDC1_5

5V_CRT_S0

15 CRT_DDCDATA

4 5 6

3 2 1

CRT_IN#_R DAT_DDC1_5

B

1

1

C1 Do Not Stuff

1

CRT_HSYNC1 C4 CRT_VSYNC1

DY2

4 11

NC#4 NC#11

VCC_CRT DDCDATA_ID1 DDCCLK_ID3

9 12 15 1 2 3 14 13DAT_DDC1_5 CLK_DDC1_5 CRT_R CRT_G CRT_B CRT_VSYNC1 CRT_HSYNC1

C5 SCD01U16V2KX-3GP 15 CRT_DDCCLK

U26 2N7002KDW-GP

2

C3

CLK_DDC1_5 C2 Do Not Stuff Do Not Stuff

SC8P50V2DN-1GP

DY2

-1

SC8P50V2DN-1GP

5 6 7 8 10 16 17

84.2N702.A3F 2nd = 84.DM601.03FCLK_DDC1_5

1

GND GND GND GND GND GND GND

2

1

CRT_RED CRT_GREEN CRT_BLUE VSYNC HSYNC

5V_S0

227 CRT_IN#_R C261 Do Not Stuff Do Not Stuff

3 1

DY1

D10 Do Not Stuff

A

DY2

Pin 1 RED Pin 2 GREEN Pin 3 BLUE Pin 4 N/C Pin 5 GND Pin 6 RED_RTN Pin 7 GREEN_RTN Pin 8 BLUE_RTN Pin 9 +5 V Pin 10 GND Pin 11 N/C Pin 12 SDA Pin 13 Hsync Pin 14 VSync Pin 15 SCL

2

JV10 CS

A

Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Document Number

CRT conn JV10-CSSheet1

Rev

-124 of 50


5

4

3

2

1

HDMI CONNECTORHDMI1 SKT-HDMI19P-20-GP-U

22.10296.05123 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22

HDMI_TX2+D

HDMI_TX2HDMI_TX1+ HDMI_TX1HDMI_TX0+ HDMI_TX0HDMI_TXC+ HDMI_TXCTMDS_SCL TMDS_SDA 5V_S0 HDMI_HPD



DY23D3V_S0

DY2

Pin 1 TMDS Data2+ Pin 2 TMDS Data2 Shield Pin 3 TMDS Data2 Pin 4 TMDS Data1+ Pin 5 TMDS Data1 Shield Pin 6 TMDS Data1 Pin 7 TMDS Data0+ Pin 8 TMDS Data0 Shield Pin 9 TMDS Data0 Pin 10 TMDS Clock+ Pin 11 TMDS Clock Shield Pin 12 TMDS Clock Pin 13 CEC Pin 14 Reserved (N.C. on device) Pin 15 SCL Pin 16 SDA Pin 17 DDC/CEC Ground Pin 18 +5 V Power (max 50 mA) Pin 19 Hot Plug Detect 2nd = 22.10296.341 3nd = 22.10296.351 4nd = 22.10296.361

D

1

-11 1 1 1C


C46 Do Not Stuff

C56 SCD1U16V2ZY-2GP


1


1

C

DY2

2

2

2

2

3D3V_S0

5V_S0 5V_S0

3D3V_S0

2 11 15 21 26 33 40 46

35 34

8 7 6 5

1R48 20KR2J-L2-GP

NC#35 NC#34

VCC VCC VCC VCC VCC VCC VCC VCC

RN52 SRN2K2J-2-GP

2

DY1

3 2 DP8101_OE#

15 PCH_HDMI_DATA015 PCH_HDMI_DATA0+ 15 PCH_HDMI_CLK15 PCH_HDMI_CLK+ 15 PCH_HDMI_DATA115 PCH_HDMI_DATA1+ 15 PCH_HDMI_DATA215 PCH_HDMI_DATA2+ Recommended Equalization: [PC1,PC0]=01, 4dB 3D3V_S0 PC0 PC1

41 42 44 45 47 48 3 4

IN_D2IN_D2+ IN_D3IN_D3+ IN_D4IN_D4+ PC0 PC1 REXT RT_EN# OE# DDC_EN GND GND GND GND GND GND GND GND GND GND GND

OUT_D2OUT_D2+ OUT_D3OUT_D3+ OUT_D4OUT_D4+ SDA SCL HPD HPD_SINK SDA_SINK SCL_SINK

20 19 17 16 14 13 8 9 7 30 29 28

HDMI_TXCHDMI_TXC+ HDMI_TX1HDMI_TX1+ HDMI_TX2HDMI_TX2+

PCH_HDMI_DATA PCH_HDMI_CLK

1 2 3 4TMDS_SCL TMDS_SDA

38 39

IN_D1IN_D1+

OUT_D1OUT_D1+

23 22

HDMI_TX0HDMI_TX0+

D5 Do Not Stuff

HDMI in : Hi HDMI out : Low

Q5 2N7002-11-GP

G S

84.27002.W31 2ND = 84.27002.Y31B

B

2

DY

1 1R28

R32 Do Not Stuff

PCH_HDMI_DATA 15 PCH_HDMI_CLK 15 PCH_HDMI_DETECT 15 HDMI_HPD TMDS_SDA TMDS_SCL

DY Do Not Stuff2

2

1 R196 499R2F-2-GP

REXT_HDMI 6 RT_EN# 10 P8101_OE# 25 DDC_EN_PS8101 32

1R30 100KR2J-1-GP

PS8101-GP3D3V_S0 RN15 SRN4K7J-10-GP 1 PC0 2 DDC_EN_PS8101 3 4 RT_EN#

71.P8101.003 2ND = 71.03411.B03

8 7 6 5A

1 5 12 18 24 27 31 36 37

Date post:	24-Oct-2014
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