JWoo_advanced MOSFETs Final

8/10/2019 JWoo_advanced MOSFETs Final

1/112

Novel MOSFET-Like Transistor Structures

Jason C.S. Woo

,Electrical Engineering

Jason Woo IWSG2009


2/112

Outline

Needs for novel Device concepts

Schottky Transistors Tunnel Source (PNPN)MOSFET

Graphene MOSFETs

Jason Woo IWSG2009


3/112

Scaling Challenges

Challenges arising due to scaling in the sub-nm regime

Source/Drain-to

Channel

Channel Transport

Limitation

Parasitic Effects

(Source/Drain

Coupling,

Velocity saturation),

Gate Leakage)

Jason Woo IWSG2009


4/112

- -

Power vs. Node Frequency Vs. Node

300

350

400

450

(W/cm2)

Freq. = 20GHz65

75

85

95

cy

(GHz)

P=50W/cm2

P=100W/cm2

P=200W/cm2

50

100

150

200

250

Pow

erConsumption Freq. = 50GHz

Freq. = 80GHz

25

35

45

55

switchingfreque

0

30 40 50 60 70 80 90 100

Node (nm)

15

30 40 50 60 70 80 90 100

node (nm)

soon hit performance limit due to less-

scalable parameters like Vth, Vdd , signal-to-

-

Jason Woo IWSG2009

,

substrate conductivity


5/112

Impact of CMOS ScalingPros: Higher ftand fmax

Higher gm

Scaling

(Interconnect)

0.25m(1P5M)

0.18m(1P6M)

0.13m(1P8M)

0.09m(1P9M)

More interconnect levels

Lower switching powerconsumption

Vdd(V) 2.5 1.8 1.2 1.0-1.2

Vth(V) 0.46 0.42 0.34 0.29

ft(GHz) 30 60 80 120

Lower signal headroom

Lower breakdown voltage Lower effective ain r

fmax(GHz) 40 80 120 150

Ion(A/m) 600 600 550 510

Ioff(A/m) 10 20 320 10,000

Higher Vth & mismatch

Higher device leakage

Higher gate resistance

gm(mS/m) 0.3 0.4 0.6 1.0

ro(Km) 129 67 24 6

gmro 39 27 14 6

Less-scalableproperties:

Vdd, Vth

Ath(mVm) 7 5.5 4.5 3.6

A(%m) 2.0 1.9 1.8 1.7

Jason Woo IWSG2009

, , ,I/O impedance

Substrate conductivity

thth = =


6/112

Impact of Scaling on Analog Performance

100Lg=60nmVth=0.25 - 0.35 V

80

n

g= nm

Lg=150nmLg=250nm

Black: Bulk

Vth=0.25 0.35 VFor Mid gap gate

FDSOI MOSFET

60

ins

icGa Green: PDSOI

Blue: FDSOI

=Vds=0.8V

Ids=100A/m

20

Int

Tox=1.5nmTSi=15nm

foper=1GHz

0 50 100 150 2000

Jason Woo IWSG2009

T z


7/112

60

70

Physical Gate Length

2001 ITRS

[nm]

50

60

40

50

h,ideal[%

]

Max. Ratio of Rsdto Ideal Rch

DEDept

30

40

20

30

R

sd/R

eng

thor

10

20

2000 2002 2004 2006 2008 2010 2012 2014 2016 20180

SDE Junction Depth

GateL

0

)( thgs

oxchch

VV

tLR

Scaled with Lg (Lch , tox)

Jason Woo IWSG2009

jsd

shsdXN

RR Difficult to scale Rsh sd ch

(Nsd

, Xj

)


8/112

Relative Contributions of Resistance

500]

70]

NMOSFETs

300

400 NMOS scaled by ITRS

ance[

Rext

Rov5060 RcsdNMOS

bution

[%

100

200

riesResis

Rcsd

Rdp

20

30R

ext

Rov

ive

Contr

32 nm 53 nm 70 nm 100 nm0

S/DS

Physical Gate Length32 nm 53 nm 70 nm 100 nm

0

Rdp


Relat

Assumptions : Scaled according to ITRS projectionGradual doping & midgap silicide material

Jason Woo IWSG2009

cs ( Rcsd/Rseries is rising up to >> ~ 60 % for LG < 53 nm)


9/112

Relative Contributions of Resistanceomponen s

PMOSFETs700

m]

70]

400

500

600

tance[ PMOS scaled by ITRS

R

Rov

40

50

60 Rcsd PMOS

ibution

[

100

200

300

rie

sResis

R

Rdp

ext

10

20

30

Rdp

Rov

Rext

tiveCont

32 nm 53 nm 70 nm 100 nm0

S/DS

Physical Gate Length32 nm 53 nm 70 nm 100 nm

0


Rel

Relatively large Rov contribution, but still largest in Rcsd( Rcsd/Rseries : ~ 60 % , Rov/Rseries : 20 ~ 30 % for LG < 53 nm)

Jason Woo IWSG2009


10/112

vance ng neer ng

240270

Rove

[m]

Graded Junction

Midgap SilicideLG= 53 nm Potential solutions foradvanced S/DEngineering:

150

180R

dp

Rext

es

istan

Box Profile

ox ro i e

Midgap Silicide

Box-shaped highly-

doped ultrashallow SDE

60

90R

csd

Series Low-Barrier Silicide

(B= 0.2 eV)

junction

(i.e., laser annealing)

0

Source/Drain Engineering

S/ lowering

(i.e., ErSi for NMOS,

Jason Woo IWSG2009

,

lower bandgap Si1-xGexlayer)


11/112

ropose o u ons or g er ormanceLow Power Transistors

New Materials with Higher Mobilities

New Contact Materials (Metal and

co

New S/D Structures (e.g. Raised S/D) for Small

SOI, DG, to improve SCE

Jason Woo IWSG2009


12/112

2-D MOSFETs-- Double Gate FETs

Jason Woo IWSG2009P. Wong


13/112

3D FETs -- Nanowire Transistors(1D Transport)

Samsung 2005

Jason Woo IWSG2009


14/112

I-V Ballistic DOS Ca acitance

Taur, TED 2008

Jason Woo IWSG2009


15/112

Essentially, Try to Make Scaled

s o ow ca ng

Device Miniaturization byimproving Electrostatic and

ranspor mo y an v

Jason Woo IWSG2009


16/112

Alternatives?

Novel Transports Mechanisms

New Materials High Mobilities Bnadgap Engineering

Others

Jason Woo IWSG2009


17/112

Lateral Asymmetric Channel (LAC) MOSFETConventional

L =0.12 m

Tilt angle LAC1018

1019

1020

ity

ation

3)

LAC: Tilt=10o

polypoly BF2(NMOS)

S D 151016

1017

Impu

LACConcent

(cm

-0.1 -0.05 0 0.05 0.1Lateral Position (m)

Formation of Channels in the Simulated channel profiles for devices

LAC and conventional structures.Usual tilt angle: 10o-15owith same Vth from source to drain1.5 nm away from the SiO2/Si interface.

Jason Woo IWSG2009


18/112

LAC Transistor

2LACDPConventional

2

/s)

LAC

DPConventional

1

1.5

locity(1

07c

05V/cm

)

0.5

eCarrierVe

Ey(1

-0.05 0 0.05Lateral Position y (m)

0-0.05 0 0.05Lateral Position y (m)

0Av

LAC Devices: Hi her do in near the source end

Ids = W Cox(Vgs-Vth(y)-V(y))v(y)

High lateral electric field near the source end in channel region High average carrier drift velocity near the source end in channel region High current drive,

Jason Woo IWSG2009


19/112

0.4LAC Tox =25

LAC Tox =36

15Vgt=0.3V, V ds=0.8V for Conv.Vds=0.8V, I ds same as Conv.

~

0.2

0.3 Conv. T ox =25

Conv. T ox =36

mS/m

)

10

Id(V-1)

gt . - . .

0.1NMOS=

gm(

5

LAC Tox=25LAC =36

gm

0 0.2 0.4 0.6 0.8 1.00

Ids same at same Lg & Toxds .

0 0.2 0.4 0.6 0.8 1.00

Conventional, T ox=25Conventional, T ox=36

NMOS

Lg(m)Lg(m)

g m is higher in SP devicesg m/Id ratio is very high compared to conventional devices when biased at same

current density :

Jason Woo IWSG2009

- ue to g current r ve, sma gt s nee e . so g gm


20/112

Hi h do in near the source Lower Mobilit

Sharp doping profile in sub45 nm transistors

Jason Woo IWSG2009


21/112

Split Gate Design

1.3

Potential profile for the HL device

H L L =45nm

H -- L gate

0.3

0.5

cm) H-L gateH gate

0.9

1.1

potential(V

) Vds=0.2 V

Vds=0.4 V

Vds=0.6 V

Vds=0.8 V

Vds=1.0 V

WH-WL=0.3eV

Vgt=0.2V, Vds=0V

Source Drain

-0.1

0.1

ield(M

V

10.0 20.0 30.0 40.0 50.0 60.0

Channel position (nm)

0.5

.

p- sub

-0.5

-0.3

ateralE-

0

20

40

EX(kV/cm) H gate

H - L gate

s= . The work-function of the H gateis higher than that of the L gate 0.0 20.0 40.0 60.0

Channel position (nm)

-0.7Channel-X (nm)

An electric field peak is generated in the channel close to the sourceside which enhances source carrier injection into the channel ( gm ).

Jason Woo IWSG2009

out can e ncrease ue o e re uce c anne - eng -mo u a on.


22/112

Simulation: Gm and Rout in scaled MOSFETs

2250Empty Symbol: H deviceSolid Symbol: HL device

50 400Empty symbol: H gate

1750

/mm)

30

40

(K

100

200

300Solid symbol: HL gate

Lg = 130 nmRout(K

1250

Gm(mS

=

20Rou

0 50 100 150 200 2500

Bias current ( m)

750

Lg = 90 nmLg = 130 nmLg = 180 nm 0 100 200 300 400

0

Lg = 45 nm

Both g and r can be improved by using this split gate design

0 100 200 300 400 500Bias current ( m)

Jason Woo IWSG2009

for different channel length considered.


23/112

Sb-induced Work Function Shift in the NiSi Gate

T = 2.6nm

NiSi/Oxide Capacitor, 100m x m

2.6nm

100

e(pF) undoped NiSi

50

Capatan

(1.5x1015cm-2)

-2.0 -1.5 -1.0 -0.5 0.0 0.5Gate Bias (V)

0

NiSi Gate: Gate full silicidation and no oxide degradation. Antimony implantation in the polysilicon gate reduces the

Jason Woo IWSG2009

.segregation effect at the NiSi/oxide interface.


24/112

Process Flow

PR Sb

PolySiN

SiNPoly oxide 4.5nm/50nm/200nm

Sb im lant ener

(a) (c)

dose and angle: 25KeV,1.5x1015 cm-2, 30o

L TO

SiN SiNNiSi

NiSi NiSiSiN SiN

r e spacer w :~ 80nm

Si Si

(b) (d)

10mins @ 450 oC

Jason Woo IWSG2009


25/112

Id-Vg and Id-Vds curves

(Substrates are undoped)5.0m ti lt-angle doped(Sb) NiSi gate

4.0m Lg=0.6

m Vg=2 V

=

n ope gate

10

m

)

1E-4

10

m)

2.0m

. .

Vg =1.0 V

rrent(A/.

VDS=0.1 V

rrent(A/

Undoped NiSi

1E-5

0.0

1.0m Vg=0.5 V

Vg=0 VDrainc

-1E-7

1E-6

Drainc

Tilt-angle Sb

-doped NiSi

Improved current drive capability is observed for the NiSi gate

. . . . . .

Vds (V)

. . . . . .

Vg (V)

Jason Woo IWSG2009

ev ce w ang e b mp an a on rom e ra n s e, .e, e

split-gate device.


26/112

Scalable?

2250

1750m)

Solid Symbol: HL device

1250(mS/

40

50

)

750

g

10

20

30

Rout(K

0 100 200 300 400 500250

0 100 200 300 400

Bias Current (A/m)

0Lg = 45 nm

Jason Woo IWSG2009

Bias Current (

A/

m)


27/112

Improved speed-gain performance

350Vth=0.15--0.25Vth=0.25--0.35

300Hz)

Lg=45nm

IDS =100

A/

m

g= nm

250FT(G

200Lsp=27.5 nmLsp=30 nmLsp=35 nmLsp=40 nmLsp=45 nmEmpty symbol: H device

-

-- --

10 20 30 40Intrinsic Gain

150

Jason Woo IWSG2009

performance compared with conventional MOSFETsperformance compared with conventional MOSFETs


28/112

Laterally Asymmetric SiGe MOSFET

channel

Channel Engineering using Band gap Engineering Concept: Modificationof threshold voltage across the channel

across the channel

Jason Woo IWSG2009


29/112

Tension Compression Tension

zzz

Si1-xGexSi1-yCySi

SiSi Si1-xGex

Ec EcEc

Strained

Ec~5y [eV] Ec~0.6x [eV]

zzz

Ev Ev Ev

Si1-xGexStrained -SiSi1-xGex SiStrainedSi1-yCySi

Ev~0.5x [eV]

Jason Woo IWSG2009

Suitable for

PFET

Suitable for

NFET

Suitable for

NFET


30/112

-

Gate

Poly-Si

Source Drain

P Si0.30Ge0.70n+ Si0.30Ge0.70 n

+ Strned-SiP Strned-Si

BOX

Si

Jason Woo IWSG2009


31/112

Digital Performance: Ion/IoffComparison

Lg=50 nm, tsi=20 nm, tox=1.5 nm, Na=2x18 cm-3

Ioffsame, VDS=1.0V1.6x10-3 As mmetric

A/m)

1x10-4

10-3

1.0x10-3

1.2x10-3

1.4x10-3

/m)

Asymmetric

Channel MOSFET

ra

incurrent

1x10-5

-4

6.0x10-4

8.0x10-4

raincurrent(

anne

Conventional

Si MOSFET

0.0 0.2 0.4 0.6 0.8 1.0

10-7

10-6

0.0 0.2 0.4 0.6 0.8 1.0

2.0x10-4

.DSi MOSFET

Gate Voltage(V)Gate Voltage(V)

Improved Ion/Ioff ratio (15% improvement)

Jason Woo IWSG2009

Comparable Subthreshold Swing (S)


32/112

Analog Performance Trends: Gm & Rout ComparisonsLg=50 nm, tsi=20 nm, tox=1.5 nm, Na=2x18 cm-3

Ioffsame, VDS=1.0V

-3

2.2x10-3

3.0x104

/m)

1.6x10-3

1.8x10

-3

. x

2.0x104

2.2x104

2.4x104

2.6x104

2.8x10

m)

AsymmetricChannel MOSFET Asymmetric

Channel MOSFET

Gmsat(S

1.0x10-3

1.2x10-3

1.4x10-3

41.2x10

4

1.4x104

1.6x104

1.8x104

Rout

(/

ConventionalSi MOSFET

Conventional

Si MOSFET

0 100 200 300 400 500

6.0x10-4

8.0x10-4

0 100 200 300 400 500

4.0x103

6.0x103

8.0x103

.

Ibias (A/m ) Ibias (A/m )Higher gm & gm/Ids ratio (low power) due to enhanced source injection

Jason Woo IWSG2009

Higher Intrinsic gain (gm x rout)


33/112

Best Semiconductor Junctions

Jason Woo IWSG2009S.M. Sze Semiconductor devices Wiley, 1985


34/112

III-V/Si Co-Inte ration IssuesIssues: Incom atibilit with Si CMOS rocess/infrastructure in lar e area

material growth and wafer bonding

Poor device yield Poor device reliability

Serious thermal mismatch

Potential Solutions: m e e eterogeneous growt at t e nanosca e ev ce eve n

selective drain/channel/source areas

Choose the best heterojunctions for the best circuit functions

,

carrier transport, higher breakdown and lower leakage currents Continue to use silicon as a substrate for mass production

compatibility

Jason Woo IWSG2009


35/112

Selective Heterojunctions for Functions

Si Si

o y

Oxide INSb/InAs/Ge InPGaN?

High-K Insulator

InSb/InAs/Ge?Si/SiGe

Si Substrate/SOI Si Substrate/SOI

-

device areas may lead to ultra-high performanceand excellent reliabil ity

Jason Woo IWSG2009


36/112

195z)

P=50W/cm2

P=100W/cm2PotentialP=10W/cm2155

cy

(G

P=200W/cm2

Scaled CMOS95

115

r

eque

55

75

tching

1535Sw

Jason Woo IWSG2009

node (nm)


37/112

Analog Behavior -

27000z)210 COSMOSGoals

17000

a

in(G160

t(GHz

> 4X

> 10X

7000

12000

ft*

60Silicon CMOS

200030507090110130150170

Node nm

10

Jason Woo IWSG2009


38/112

Novel Source Injection MOSFETNovel Source Injection MOSFET

I. As mmetricI. As mmetric SchottkSchottk TunnelinTunnelin

Source Injection MOSFETSource Injection MOSFETA novel device structure incorporating gate controlledA novel device structure incorporating gate controlled

source injection by schottky barrier tunnelingsource injection by schottky barrier tunneling

Jason Woo IWSG2009


39/112

MotivationMotivationScaled MOSFET performance is increasingly limited by:

1. Parasitic Resistances : 2. Electrostatics and transport :Source / Drain junction resistance Non Scalability of subthreshold swing

(diffusion limited) as well as built involtage of p-n junctions

Metal Source/ Drain junctionsSource injection of carriers through

Schottky Source Tunneling MOSFET:Schottky Source Tunneling MOSFET:

Fully Silicided Source/Drain junctions

Gate controlled source injection through schottky barrier

Jason Woo IWSG2009

tunneling


40/112

Schottky Barrier FETsSchottky Barrier FETsIssues and ProblemsIssues and ProblemsGateMetal

Lar e causes reduction in drive current

Source DrainDrain Side SB causes reverse drain leakage as

well as degradation in current in the linear regionHigh resistance region under the spacer causes

potential drop

Resistance likeResistance likebehavior observedbehavior observed

in the linear regionin the linear regionof the Iof the IDD--VVDD curvescurves

Jason Woo IWSG2009

QQ.. TT.. ZhaoZhao etet al,al, MicroelectronicMicroelectronic EngineeringEngineering,,VolVol.. 7070,, pppp.. 186186,, 20032003..


41/112

Schottky Barrier FETsSchottky Barrier FETsPotential solutionsPotential solutions

Gate

se sma b m n mum: . e r or

electrons and 0.25eV (PtSi) for holes)but b always positiveSource Drain

Use doped extension under the spacer

reducing eff. bEliminates high Resistance region

under the ate

Doped extension

The sourceThe source--channel andchannel anddrain channel contactsdrain channel contactsare now ohmic and notare now ohmic and not

but transistor becomes conventionallike

eliminates advantages of

Jason Woo IWSG2009

schottky in natureschottky in natureSchottky Barrier


42/112

How about Analog Applications Source injection of carriers by tunneling atthe source schottky junction

N+ Region on the drain side to form ohmic

contact between drain and channel

0 . 3 0

0 . 4 5J

T h e r m i o n i c I n c r e a s i n gG a t e V o lt a g e

ge(eV)

0 . 0 0

0 . 1 5T u n n e l i n g

ctionBandEd

Source

The gate controls tunnelingthrough the schottky barrier

by changing the tunneling

-4 -2 0 2 4 6 8 1 0 1 2 1 4

- 0 . 3 0

- 0 . 1 5

Cond

width as well as the availabledensity of states on thesemiconductor side

Jason Woo IWSG2009

D is ta n c e a l o n g c h a n n e l ( n m )


43/112

Effect of Barrier Height (b

)

1x102

= 0.25eV

At same tOX, subthreshold

1x100

1x101

0.45eV

.

at high b

1x10-2

1x10-1

0.65eV

A

/m)

is limited by the virtualcathode point in the channel

1x10-4

1x10-3

tOX

= 20

=

ID( us on m e

However, Short Channel

1x10-6

1x10-5 D

.

VD= 1.0Vec s are

considerably improved withtunneling at high b

Jason Woo IWSG2009

. . . . . .V

G(V)


44/112

Effect of Drain pocket (NDrn

)

1200

1500

b= 0.45eV

Vg=1.0 V

no drain pocketwith drain pocket

Degradation in ID mainly caused

600

900t

OX= 5

Vg=0.6 V

Vg=0.8 V

(A/

m)

due to a drop across the forward

biased schottky junction at the drain

0.0 0.2 0.4 0.6 0.8 1.00

Vg=0.4 VID.

1

10

Sim.D

1n10n

100nno pocket

F(A/m)

Increase in IOFF due to back injectionof holes from drain to source

1p10p

p

n+ drainpocket

IOF

A n

+

type pocket makes the drain sidejunction ohmic and hence prevents back-injection

Jason Woo IWSG2009

. . . . .V

D(V)


45/112

Scalability of the STS-FET

Dramatic Improvement in-0.25

0.30

150)

Induced Barrier Lowering(DIBL) with increasing b0.150.20

Vth(V

)

6090

-(

b

=0.25eV)

(b=0.45eV)

=0.65eV L(m

V/

0.45

e60 90 120 150 180

0.05

0.10

0

30 DI

0.00

0.15

0.30

increase in VD

BandEdL

G(nm)

source side is not affected

b drain volta e immune-0.30-0.15 Increasing Drain

Voltagenductio

n

Jason Woo IWSG2009

to drain field) 0 20 40 60 80 100- .

C

Distance along channel (nm)


46/112

Analog Performance: gm

1 0 0 0

1 2 0 0

6 0 0

8 0 0

(S/

m)

4 0 0 F D - S O I

B H = 0 . 3 0 e V

Gm

0 5 0 1 0 0 1 5 0 2 0 00

B H = 0 . 4 5 e V B H = 0 . 5 5 e V

B i a s C u r r e n t (

A /

m )At low bias currents, gm of the STSFET is higher than that of the conv.

-

Jason Woo IWSG2009

.is higher as the barrier height decreases.


47/112

Analog Performance: ROUT1 0

4

1 03

(K-m)

1 02 F D - S O I

B H = 0 . 3 0 e V

B H = 0 . 4 5 e V

Rout

0 5 0 1 0 0 1 5 0 2 0 01 0

1

B H = 0 . 5 5 e V

At low bias currents, ROUT of STSFET is superior to conv. SOIFET due~

Jason Woo IWSG2009

. . . . Tunneling mechanism high ROUT


48/112

Analog Performance: Gain (AV)1 0 3

1 02

F D - S O I

B H = 0 . 3 0 e V B H = 0 . 4 5 e V in

(A

v)

1 01

B H = 0 . 5 5 e VG

0 5 0 1 0 0 1 5 0 2 0 01 0

0

B i a s C u r r e n t A / m

The gain is ~10X more than that of conventional SOI-FETIncrease in gm and ROUT for low bias currents (


49/112

Frequency-Gain PerformanceSTS-FETSOI-FET

2.0x103 STS-FET

SOI-FET

10

Ibias

= 100 (A/m)Gain

1.5x103

Gain

102

n

trinsic

2

1.0x10 Ibias = 100 (A/m)

Vth= 0.2 - 0.35V

ntrinsic

101

Vth= 0.2 - 0.35V

0.0

.

ft(GHz) ft(GHz) Improvement in Frequency-Gain performance for different

Jason Woo IWSG2009

Suitable for High performance, low power transistors

N FET d i


50/112

N-FET device

1x102

1x103

1.1VVD=1.6V

ID-VG char. for the NiSi STS nFET LG = 0.15m

250

300

350 Sim. DataExp. Data

ldSwing

ec)

1x10-1

1x1001x10

1 c ott yTunneling Current

0.1V

0.6V

m)

100

150

200

SS = 60 + 4.7 x tO X

Subthresh

(mV/

-4

1x10-3

1x10-2

=

ID(A/

0 10 20 30 40 5050

O xide thickness ()

0 1 2 3 41x10

-6

1x10-5

. t

OX=30

10n100n

1

no pocket

Sim.Exp.

/m)

G

1p10p

100pn+ drain

pocket

IOFF(

Observed drain leakage due to back-injection of h+ (ambipolar transport)

Jason Woo IWSG2009

0.0 0.4 0.8 1.2 1.6V

D(V)

S


51/112

Summary Need to explore alternate structures to achieve high

erformance low ower transistors

Asymmetric Schottky Tunneling Source MOSFETconcep s n ro uce

b

~ 0.3 0.65eV, EOT < 10,

Drain-side pocket to improve linear characteristics

Optimized device structure highly immune to Short

Channel Effects Very Scalable Transistor Structures

Jason Woo IWSG2009


52/112

gm is higher than conv. SOI-FET at low bias currents,

applications

Big Improvement in ROUT and intrinsic gain(g

mxR

OUT) even at L

G< 90nm at low currents

Exceptional frequency-gain performance for low,

Promising Alternative for mixed mode, RF and SOC

Jason Woo IWSG2009

applications

N l S I j ti MOSFETN l S I j ti MOSFET


53/112

Novel Source Injection MOSFETNovel Source Injection MOSFET

II. QM-Injection Transistors

Vs/dbVth Vsupply

concepts made possible bynano-dimensions to achieves eep su res o sw ng anballistic carrier transport togive high Ion.

g er off an re uce on offrat o

Jason Woo IWSG2009

s/db -Vth Threshold Voltage

S Subthreshold Swing

B k d


54/112

BackgroundChallenges arising due to scaling in the sub-30nm regime

Channel Trans ort Parasitic EffectsSource/Drain-

to ChannelElectrostatic

Limitation

(MobilityReduction, Velocity

(Source/Drain

Resistance/Capacitance, Gate

Subthreshold Swing >

60mV/Decade min VTH for given

sa ura on ea age off low Ion/Ioff

Improved Device Architecture (Double or Tri-gate MOSFETS) New materials to enhance transport (SiGe or Ge channel) New Gate Dielectrics to reduce gate leakage (High-K dielectrics)

Rationale of these approaches:

Make the device Long-channel like

Jason Woo IWSG2009

(instead of exploiting new device physics opportunitiesafforded by nano-dimensions)

54

V Scaling


55/112

V Scaling Low power devices with continued VDD scaling need

- Reduced V to have reasonable I at low V

- Small IOFF

even with low Vth

Conv. MOSFET Subthreshold Swing limited to

60mV/dec (@300K) due to diffusion mechanism

Alternate mechanisms of carrier injection not limited

by diffusion limited swing:

Tunneling

Impact IonizationNeed of high VDD (> EG/q) to have working FETs

Jason Woo IWSG200955

M ti ti


56/112

Motivation

In order to continue scaling of transistors for low power,

These alternate structures must be optimized for both analogand di ital erformance conducive to SOC a lications

The Tunnel Source MOSFET:

PNPN FET

Significant low-power

Jason Woo IWSG2009

H g Res stance to SCEs xtreme y sca a ePerformance improvementOver conventional devices

56

Tunnel Transistors


57/112

Tunnel TransistorsPrevious efforts on p-i-n structure using gate modulatedtunneling injection

TFET (P-I-N)Nirschl. T et al, EDL, vol. 28, 4, pp. 315, 2007

Vertical TFETBhuwalka et al, TED, vol. 51, 2, pp. 279, 2004

, . , . , . , . - ,

W. M. Reddick and G. A. J. Amaratunga, APL., vol. 67, no. 4, pp. 494497, 1995 Qin Zhang, Wei Zhao, Alan Seabaugh, EDL, Vol. 27, No. 4, 2006, pp. 297-300

Jason Woo IWSG2009

,junction causes 100X reduction in current

57

Tunnel Transistors


58/112

Tunnel Transistors

Experimental TFETW. Y. Choi et al, EDL, vol.28, 8, pp. 743

p-i-n FETK. Boucart et al, ESSDERC 2006, pp. 383

Experimental verification of the p-i-n concept, however a 100Xreduction in current compared to conv. FET

Jason Woo IWSG2009

ambipolar nature of the device

58

Alternative Tunnel Transistor


59/112

Alternative Tunnel Transistor

Possible solutions

Increase the lateral electric field at the source sideunc on an re uce unne ng w

Asymmteric structure to eliminate ambipolar conductionAlternative Solution:

Tunnel source PNPN-FET has advantages over p-i-n

Reduced potential drop at the tunnel junction Improved drive current Reduced ambi olar conduction


Device Concept


60/112

Device Concept

Novel device concept based on Band-to-Band Tunneling

(Tunneling width is reduced by the fully depleted N+

layer)SilicideSilicideSilicide

n+ source

fully

depleted

Gaten+ source

fully

depleted

Gaten+ source fully

depleted

pocket

Gate

o ypocket

P+ Source N+ Drain

o ypocket

P+ Source N+ Drain

o y

P+ Source N+ Drain

Bulk (p)Bulk (p)BOX


Tunnel Source PNPN n MOSFET


61/112

Tunnel Source PNPN n-MOSFET

Gate Electrode controls the source-to-channel tunnelingcurren y

-band of the tunneling-source junction and the conduction

band of the channel, thus modulating the availability ofdensity of states for tunneling

mo u at ng t e tunne ng w t w c s a rea y ma esmall because of the narrow and fully depleted n-pocket)


Device Concept


62/112

Device Concept

Conduction Band Conduction Band

a

Valence Band Valence Band

When VG < VTurnon, I is small since the electrons from the P+

valence band can tunnel only to the trap states When V

G

> VTurnon

, electrons from the P source valenceband tunnel to empty states in the conduction band of thechannel

Jason Woo IWSG2009

(VTurnon Gate voltage required for conduction and valence

bands to overlap) 62

FD Pocket Essential


63/112

FD Pocket Essential

1.0

1.5

(eV)

W= 4 nm

1.0

1.5W= 15 nm

(eV)

-0.5

0.0

0.5

Energy

ECEV -0.5

0.0

0.5

EC

EVEne

rgy

-2.0

-1.5

- .

Electro

Just Full Depletion -2.0-1.5

-1.0

Electro

0.00 0.05 0.10 0.15 0.20- .

Distance along channel (m)0.00 0.05 0.10 0.15 0.20

-2.5

Distance along channel (m)

W width of the n+pocket

Band diagrams illustrate the importance of full depletion of thepocket. For pocket which is only partially depleted, injection

Jason Woo IWSG2009

mechanism is no longer tunneling

63

Device Simulation


64/112

Device Simulation

Quantum Mechanical TunnelingBand-to-Band

governed by

Tunneling Probability (Tt)

Fermi Selection RuleFFVV(E)*(E)* [1[1--FFCC(E)(E)]*]*u(E)u(E)

Where u(E) =1 if there is availability of states

governe y

Tunneling width

(incorporating phonon

to tunnel to; 0 otherwise. FV(E) and FC(E) are

Fermi-Dirac distribution functions for the

initial and final energy states.

Tunneling current: Esaki Diode integralIV-C=AFV (E)*nV (E)*Tt *[1-FC (E)]*nC (E)* u(E)dE


Methodology for ATLAS simulations


65/112

Methodology for ATLAS simulations

Initial Guess for ATLAS

Band-to-Band tunneling

ATLAS Device Simulator

with Band-to-Band tunneling

parameter (BB.A)o e on use o eva ua e

channel current (Ichan

)

Esaki tunnel diode formalism used

to calculate tunneling current (Itun)

at the tunneling source junction using

Solution converged

Used as starting guess

simulated structure from ATLAS

0.999 < Itun/Ichan < 1.001?Tweak parameter

BB.A

NoYes


Device Calibration


66/112

Device Calibration

m2) Parameters:

sity(A/c Effective mass m,

tuned to obtain a fit

rentDen with the

experimental data

Cu rom s con unne

diodes

Reverse Voltage (V)

Theoretical Reverse bias tunneling diodecurrent matched with ex erimental +/n+

Jason Woo IWSG2009

diodes.Ref: M.W. Dashiell et al, TED, Vol.47, no.9, 1707 (2000)

66

Pocket Design


67/112

Pocket Design

300

360

W=4nm

Pocket Doping = 5x1019

cm-3

1.6x1020

70

80ID= 1 nA/m

ID= 100 nA/m

180

240W=15nmConv SOI

mV/dec)

8.0x1019

1.2x1020

AX(c

m-3)

50

60

V/d

ec)

0

60

120SS

0.0

4.0x1019N

D

20

30 SS(

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1V

G- V

T(V)

Pocket should be fully depleted for subthreshold swing to go below

2 4 6 8 10Pocket Width W (nm)

Pocket width should be small (


68/112

ev ce Sca ab ty

0.30

0.32

260

0.26

0.28

(V) 220

240

V/V)

0.22

0.24

VTHLIN

180

200 SOI

IBL(

40 50 60 70 80 90 1000.18

0.20

140

160

anne engtG

nm

Optimized structure is very scalable

Jason Woo IWSG2009

. -respect to Vth roll off and DIBL

68

Low Standby Power Performance


69/112

5

1x106

PNPN

1x104OFF

1x102

1x103

T =60nm

TOX

= 1.1nmT

OX= 2.5nm

ION/

40 50 60 70 80 90 1001x10

1 Conv SOI

LG

(nm) Degradation in subthreshold swing and IOFF with scaling is

negligible for the tunneling device

Jason Woo IWSG2009

As a result, ION/IOFF is improved by 3 orders over conventional

SOI with scaling highly beneficial for low standby power

applications 69

Low Operating Power Performance


70/112

3540

(a)T

OX= 1.1nm

TOX

= 2.5nm

) 3035

(b)T

OX= 1.1nm

TOX

= 2.5nm

2025

30 LG = 45nmV

TH

= 0.3-0.35 V

(K

20

25PNPN

G= nm

VTH

= 0.3-0.35V

xROUT

51015

Conv. SOI

PNPN

ROU

510 Conv. SOIG

M

0 200 400 600 800 10001200

ID(

/

m)0 200 400 600 800 10001200

0

ID(/m)

Tunnel n-FET also exhibits an improvement in ROUT

over theconventional SOI for the given channel length as in (a). This can beattributed again to reduced drain coupling and resistance to SCEs.

Jason Woo IWSG2009

Intrinsic gain (GM x ROUT) is higherthan the conventional device, asshown in (b), especially at low IBIAS.

70

Vertical PNPN MOSFET


71/112

Ve c OS

Tunneling junction doping profile needs to be sharp,

than ion implantation

Vertical PNPN Transistor

p+ Source n+ poc et

In addition, vertical transistors have the advantages: Immunity to short-channel effects (multi-gate

structure

chann

e

Gate

Gate

Lithography independent critical dimensions (lessprocess variation) Higher on-current (multiple channels in one device)

n+ Drain

l

Potential in 3-dimensional integration


Summary


72/112

y Need to explore alternate structures to continue scaling for lowpower applications

The Tunnel Source MOSFET (PNPN tunnel nFET) has very lowstandb ower due to smaller than 60mV/dec subthreshold swin

Optimized device structure highly immune to Short ChannelEffects Very Scalable Transistor Structures

Achievement of Sub-threshold swing well below the diffusionlimit of 60mv/dec (at 300K) with Very Low IOFF and consequently a

g er ON OFF rat o

Improvement in intrinsic gain (gmxROUT) even for sub-90nm



73/112

Ultimate High-Mobility Channel

Jason Woo IWSG2009


74/112

0D

fullerenes

1D

carbon nanotube

3D

graphite

0D fullerenes, 1D carbonnanotube and 3D graphite can beregarded as the wrap and stacksof several layers of graphene.

Graphene

rap ene:

single sheet of graphiteunwrapped SWNT

Jason Woo IWSG2009

Graphene Deposition Methods


75/112

Mechanical exfoliation

Jason Woo IWSG2009

P i ip Kim, et a . (2005) K.S.Novoselov, et al. (2004)



76/112

Epitaxial growth ---- thermal desorption of Si on (0001) face of singlecrystal 6H-SiC;

Jason Woo IWSG2009

Walt A.de Heer, et al. (2006)

Chemicall Converted Gra hene


77/112

Review: Graphite is oxidized via modified Hummers method andsimultaneously reduced and dispersed in anhydrous hydrazine.

N2H5+

N2H5+

Thermall anneal

N2H5+

Solution processable chemically converted graphene has been

2 5

Jason Woo IWSG2009

growth tests with the CERA team.

77

Chemicall Converted Gra hene


78/112

1. Reduction of these new graphite oxides have been achieved2. Sin le sheet dis ersions usin urification techni ues

previously described is being investigated

3. These films are useful for the development of Graphene

propoerties.

10 um




79/112

4. Chemical vapor deposition using Ni as catalyst.

Alfonso Reina, et al. Nano Lett. (2009)

Jason Woo IWSG2009



80/112

Chemical synthesize from reduced graphite oxide.

N2H4

Spin coat onsubstrate

Vincent Tung, et al. Nature Nanotech., (2009)

Jason Woo IWSG2009



81/112

Radio frequency plasma-enhanced chemical vapor deposition.

Jason Woo IWSG2009

J.J.Wang, et al. (2004)


82/112

Current Technology1. Mechanical Exfoliation

Scotch tape is used to peel and stamp single and/or few layers fromHOPG (the yield is exceedingly low).

2. Reduction of Silicon Carbide1,100C can be used to make very small regions ofgraphitic carbon

.Difficulty is the strong van der Waals forces between sheets

Graphene properties demonstrated to date are marginal for RFElectronics not clear that this process can be easily enhanced to

Jason Woo IWSG2009

.


83/112

Fundamental Challenges of CVD Grapheneon Ni

Non-homogeneity of graphene thickness;

The expected grain boundaries in graphene.

The multiple grained structure of blank Ni films on

various substrates:

The unavoidable multiple nucleation of graphene; The inability to control the location of graphene grain

Jason Woo IWSG2009

boundaries.

83

Large size monolayer graphene and the Raman spectra


84/112

One

LTwo

L

30um

-

OM

image

o

t e

grap ene

graphene film without grain boundary

Jason Woo IWSG2009

One layer graphene

84

Graphene transfer using PDMS


85/112

Pickup Transfer

Continuous film

tGraphene

PDMS

(Grapn/Ni/)SiO2/Si

Sample062920093

(1) Pick-up process : Attaching the PDMS with the CVD-grown Grapn/Ni/SiO2/Si and

2 3 (2) Transfer process : Putting the FLG/PDMS onto the 300 nm SiO

2/Si substrate to transfer

Jason Woo IWSG2009

- of 2 inch diameter wafer.

85

Graphene as grown and after transferred


86/112

Graphene was synthesized by CVDusin cam hor as carbon source

SEM image of the graphenegrown on Ni poly-crystalinesurface at 850oC.

Transfer

2699

Jason Woo IWSG2009

after transferred onto SiO2surface.

Raman spectrum of the transferredgraphene which indicates the graphene.

86


87/112

1. Pattern and etch of annealed Ni film;

2. Thick Ni film deposited on patterned surfaces +anneal + CMP

3. Annealin of atterned Ni with a ca in la er

Jason Woo IWSG2009

Process flow


88/112

SiO2 SiO2TiN

Si substrate

Pattern TiN/SiO2substrate

Deposit Ni/SiO2on SiO2

Anneal at1000C 5minTiN

Ni

SiO2

Jason Woo IWSG2009

emoveo geflat surface

88

SEM icture of annealed

Part 1

l


89/112

sample

Jason Woo IWSG2009

Over 90% Ni patterns havebecome single crystal

89

Structure of Graphene


90/112

2-dimensional Dirac-Fermions

In plane: honey comb structure

w eren a oms an

Out of plane: Van de Waals force Zero band-gap

Jason Woo IWSG2009

Linear E-k relationship

Physical Properties of Graphene


91/112

Semi-metal with zero band-gap and large .

High mobility in the plane ( ~15,000cm2

/Vsat room tem erature

Nearly ballistic transport in m scale( velocity ~108cm/s )

2D structure more compatible withcurrent MOSFET process technology.

---- Graphene has great potential to be usedas a channel material in MOSFET devices.

Jason Woo IWSG2009

Carrier Densities in Monolayer Graphene


92/112

Linear E-k relationship

E = k is reduced Planck constant,

Fis Fermi velocity ~ 1x106m/s

Carrier Densities per unit area in monolayer graphene

6

7

cm-2)

electron densityhole densit

,1)(2 0

/)(2 +=

+

+ kTEEF

vse

e

dggn

Fc

h

3

4

nh(x1012

,1)(2 0

/)(2 +=

+

+ kTEEF

vsh

e

dggn

Fv

hni =10

11cm-2

Intrinsic Carrier Density -0.2 -0.1 0 0.1 0.2 0.30

1ne,

-0.3

2,2 == vs gg

Jason Woo IWSG2009

ni ~ 1011/cm2-1012/cm2 F

- c,v

Metal-Oxide-Graphene Capacitor Structure


93/112

0.8

Metal Oxide

0.6

.

Cox

Graphene

0.4

0.5Ctot2

-1 -0.5 0 0.5 10.3 monolayer graphene ~ 3.37 gate oxide: tox=2nm

Jason Woo IWSG2009

G metal-graphene =

Graphene Field-effect Transistors with Metal Source and

Drain - Simulation


94/112

n+Metal n+MetalGrapheneMetal Metal -1

101

Total Current

)

p-SiSiO2p-SiSiO2

10-3Electron Current Hole Current(m

A/

-

10-5IDS tgraphene ~ 3.37

gate oxide: tox=2nm metal- ra hene =0

Ambipolar conduction: IDS = Ie+Ih

-1.0 -0.5 0.0 0.5 1.0

VGS(V)

Jason Woo IWSG2009

on off ~ or GS= an GS=

Issues of Graphene Field-effect Transistors

T di l i d i i


95/112

Choose different gateTop-gate dielectric deposition:-- Function layer needed

Gate

TH -- ause ranspor egra a onin graphene

Bottom dielectric

Si substrate

Graphene

Interaction between grapheneand bottom dielectricSeries resistance

Contact resistance

-- cause ranspor egra a on

Add to parasitic resistances and Trap states in graphene consume

Jason Woo IWSG2009

charges but not conductive

Effect of Parasitic Resistance and Capacitance on Current

LV


96/112

sc

c

Gc

sGc

DD RQ

WQ

LVR

RVR

VI

=

+= .resistanceparasiticischarge,conductiveis,)(,

)(

oxgraccDsDD

CCCCC

VQ

VQ

VIRVW

VI

++==2

,)(

defgraox

gra

D

DsDDox

egraox

CCC

C

V

IRVVC

L

W

++

= 2)(

Ideal expression

Effect of parasitic resistance

Effect of quantum capacitance of graphene and defect capacitance.

Jason Woo IWSG2009

Effect of Parasitic Resistance

on Current


97/112

on Current0.25 Ideal case, on/off ~ 68

0.20

/m)

s= , on o ~Rs=100, on/off ~ 20Rs=200, on/off ~ 12

W/L=1;

=15,000cm2

/Vst =2nm

0.10IDS(m

DS= .ox

VDS=10mV

0 0.2 0.4 0.6 0.8 10

.

V V

Reduce IDS: Rs=50, IDS @VGS=1Vdecrease ~57%

Jason Woo IWSG2009

Reduce gm: change the shape of IDS-VGS

Reduce Ion/Ioff: Rs=50, on/off ratio


98/112

Evaporated SiO2 on Exfoliated Graphene


99/112

20nm SiO2 deposited togetherwith gate metals using e-beamevaporat on an t-o process

Current degraded (~30%) aftertop-gate stack deposition

Jason Woo IWSG2009

M. C. Lemme, etc. Solid-State Elec.2008

ALD Al O on Graphene


100/112

-

no dangling bonds or functional groups to

Al2O3 using functional group

-Al2O3

2 3

formation

Jason Woo IWSG2009

ALD Al2O3 using O3 as Function Layer


101/112

a HOPG surface treated b ozone retreatment. b ALD Al O surface onozone-treated HOPG. (c) TEM image of cross-section after Al2O3 deposition.

Fresh HOPG sample

Pre-treated by ozone, oxygen atoms absorbed on the surface

ALD Al2O3 using TMA+O3

Jason Woo IWSG2009

, . . . .

ALD Al2O3 using NO2 as Function Layer


102/112

First applied on single wall carbon nanotubes

NO2 attracted on carbon surface through physical

Aluminum centers of TMA attracted to oxygen end ofNO2

Jason Woo IWSG2009

Demon B. Farmer, et al, Nano. Lett. (2006)J. R. Williams, et al. Science (2007)

Al[CH3]3 (trimethylaluminum) and H2O precursors


103/112

[ 3]3 ( y ) 2 p Physisorption of NO2 50 cycles of the ALD process

ph

ene

ph

ene

SiO

2gr

SiO

2gr

Jason Woo IWSG2009

ALD Al2O3 using Evaporated Al as Function Layer


104/112

Graphene, covered by Al2O3

E-beam evaporate 1~2nm Al on graphene

Al bein oxidized in ambient before ALD

ALD Al2O3 deposited on oxidized Al

Jason Woo IWSG2009

Seyoung Kim, etc. Appl. Phys. Lett. 2009

Graphene FETs with Al O Dielectrics


105/112

Jason Woo IWSG2009

IBM, IEDM 2008

Ambipolar Conduction of Graphene

El t t1.6


106/112

Electron current1.2m

)Simulation of Graphene FET with

1.2

1.6

) Hole dominates 0.4

0.8

ID(

mA/me a con ac s

0.8

(mA/

-1.0 -0.5 0.0 0.5 1.00.0

VG (V)

-1.0 -0.5 0.0 0.5 1.00.0

.I

/m) Hole current

1.2

1.6

G

ID(m

0.4

0.8

The sum of electron and holecurrent is ambipolar.

Jason Woo IWSG2009

VG (V)-1.0 -0.5 0.0 0.5 1.0

0.0Electron (or hole) current only isunipolar.

Schottky Tunneling Structure Applied in Graphene FETs

S DG


107/112

Em lo Schottk unctions atS DG

source/drain

to suppress ambipolarconduction

n+Metaln+

MetalGraphene

n+-Sin+-Si

increase Ion/Ioff

Schottky junction at source:

-

p-SiSiO2p-SiSiO2

band-bending near the junction

always electrons tunnelingthrou h the barrier

EC EC=EV

B .EFn

Schottky junction at drain: n+ drain supplies only few holesEV

VDS =0.01V

Jason Woo IWSG2009

hcon ource rap ene anne

Graphene FETs with Schottky Tunneling Source/Drain -

Ex erimental

LPCVD Polysilicon on insulated surface


108/112

y

Etch Pol silicon to form source/drain

Spin coat chemical synthesized graphene

Top-gate dielectric deposition -evaporate 500nm Al contacts on Polysilicon

E-beam evaporate 500nm Al as gate

Al

Poly-Si Poly-SiGraphene

AlAl

DielectricPoly

Poly

2

Si

rap ene

Jason Woo IWSG2009

2 3

ALD Al2O3 with Evaporated Al on CVD Graphene

CVD graphene transferred to SiO2 substrate


109/112

CVD graphene transferred to SiO2 substrate

vapora e nm us ng e- eam evapora on

Immediately transfer to ALD machine 2 3 2

SiO2Graphene

SiO2Graphene Oxidized Al

ALD Al2O3

SiSi

Jason Woo IWSG2009

AFM Images of Al2O3 on CVD Graphene

3 05

a) CVD Graphene on SiO2Before Al2O3 deposition


110/112

~3.05nmSiO2

2.05m

Graphene

~3.05nmb) 2nm evaporated Al on surface

2.05 m

SiO2

After Al2O3 deposition

Graphene ~3.05nm

c) 8nm ALD Al2O3 on top of Al

Jason Woo IWSG2009

Summary

Potential CVD Graphene Synthesis


111/112

Potential CVD Graphene Synthesis

Graphene Proporties Inteface Issues

Graphene MOSFET Processes Graphene Channel FET Structures

Graphene FETs Processing

Jason Woo IWSG2009


112/112

Date post:	02-Jun-2018
Category:	Documents
Upload:	anjireddy-thatiparthy
View:	220 times
Download:	0 times

JWoo_advanced MOSFETs Final

Documents