Post-Silicon ValidationPost-Silicon ValidationChallenges and OpportunitiesChallenges and Opportunities

Keshavan Tiruvallur, FellowKeshavan Tiruvallur, Fellow

Nagib Hakim , Principal EngineerNagib Hakim , Principal Engineer

Intel CorporationIntel Corporation

Copyright © 2011 Intel Corporation.  All rights reserved. Intel and the Intel logo Copyright © 2011 Intel Corporation.  All rights reserved. Intel and the Intel logo are tradem arks of Intel Corporation in the U.S. and/or other countries.are tradem arks of Intel Corporation in the U.S. and/or other countries.

Intel's VisionIntel's VisionThis decade we will create and extend com puting technology to This decade we will create and extend com puting technology to connect and enrich the lives of every person on earth. connect and enrich the lives of every person on earth.

Product Developm entProduct Developm ent

ExplorationExploration

PlanningPlanning

Developm entDevelopm ent

ProductionProduction

Intel Post-Si ValidationIntel Post-Si Validation

Validation and DebugValidation and DebugLogicLogic

Speed and ElectricalSpeed and Electrical

Com patibility SoftwareCom patibility Software

Custom er Platform sCustom er Platform s

Software StackSoftware Stack

Prevent

Detect

Survive

m issm iss

m issm iss

Innovation and Innovation and M ethodologyM ethodology

FixFix

FixFix

Logic Validation Com plexity DriversLogic Validation Com plexity Drivers

Accelerating Levels of Integration Accelerating Levels of Integration – Increased IP reuse, IP diversity, ConcurrencyIncreased IP reuse, IP diversity, Concurrency– Variable IP quality and levels of m aturityVariable IP quality and levels of m aturity– Increased role of Software and Firm wareIncreased role of Software and Firm ware

Im pact on ValidationIm pact on Validation– Im portance of pre-Si IP and product healthIm portance of pre-Si IP and product health– Higher Reliance on Virtual Platform s, Em ulationHigher Reliance on Virtual Platform s, Em ulation– New usage scenarios, workloads, concurrency trafficNew usage scenarios, workloads, concurrency traffic

Common Architecture For Validation, Coverage, DebugCommon Architecture For Validation, Coverage, Debug

Circuit Com plexity DriversCircuit Com plexity Drivers

Increasing com plexity and num ber of analog Increasing com plexity and num ber of analog circuits and I/O interfaces:circuits and I/O interfaces:– Perform ance, new form factors, and Fab technologyPerform ance, new form factors, and Fab technology– Variations, aging, Noise m itigationVariations, aging, Noise m itigation

– Increasing power m anagem ent and clock dom ains Increasing power m anagem ent and clock dom ains – Affects Tim ingAffects Tim ing

Im pact on Validation:Im pact on Validation:– Test chips to m itigate new fab process variationsTest chips to m itigate new fab process variations– Adaptability / Survivability features criticalAdaptability / Survivability features critical– Sm all form factors lim it DFx and observability Sm all form factors lim it DFx and observability

Better Pre-S ilicon Methods and ToolsBetter Pre-S ilicon Methods and Tools

Business and Efficiency DriversBusiness and Efficiency Drivers

Faster throughput driven by m arket needs and Faster throughput driven by m arket needs and num ber of SKUsnum ber of SKUs– Drives validation collateral reuse: Autom ation, content, and debugDrives validation collateral reuse: Autom ation, content, and debug– Requires a com prehensive pre- to post-Si validation readinessRequires a com prehensive pre- to post-Si validation readiness– Validation readiness crucial for on-schedule product launch Validation readiness crucial for on-schedule product launch

Security versus DebugSecurity versus Debug– Increasingly harder tradeoffsIncreasingly harder tradeoffs

Increasing Risk of Bug EscapesIncreasing Risk of Bug Escapes– Escape costs are higherEscape costs are higher– Drive DFx and survivability requirem entsDrive DFx and survivability requirem ents– Cost shifting from post-Si equipm ent to pre-Si and on-die features.Cost shifting from post-Si equipm ent to pre-Si and on-die features.

End to End (Pre to Post) Methods and ToolsEnd to End (Pre to Post) Methods and Tools

G oing ForwardG oing Forward

Optim ize the entire tim e-to-m arket:Optim ize the entire tim e-to-m arket:– Shift m ore effort to pre-Si: DFx, Em ulation, Virtual platform sShift m ore effort to pre-Si: DFx, Em ulation, Virtual platform s– M itigate circuit risks in pre-SiM itigate circuit risks in pre-Si– Invest in resiliency and survivability hooksInvest in resiliency and survivability hooks– Com prehend softwareCom prehend software

Validation ReadinessValidation Readiness– Deep engagem ent with design activities and IP providers (HW / Deep engagem ent with design activities and IP providers (HW / SW )SW )

– Stream line validation infrastructure, flows, collateral and content Stream line validation infrastructure, flows, collateral and content across products and generations.across products and generations.

Validation ExitValidation Exit– Risk assessm ent and m itigationRisk assessm ent and m itigation– OEM enablingOEM enabling

S treamlined, converged validation, debug methods – can we? S hould we?S treamlined, converged validation, debug methods – can we? S hould we?

W hat EDA industry can do W hat EDA industry can do

Enable seam less pre- to post- and post- to pre-Si Enable seam less pre- to post- and post- to pre-Si analysisanalysis– Validation content optim ization and coverageValidation content optim ization and coverage– Circuit analysis scaling to full systemCircuit analysis scaling to full system– Including power grids, clocks, m ixed-signal, off-chip com ponents.Including power grids, clocks, m ixed-signal, off-chip com ponents.– Better Correlation to silicon results.Better Correlation to silicon results.

– Form al m ethods in content generation and debug.Form al m ethods in content generation and debug. Develop com prehensive validation SW environm ents:Develop com prehensive validation SW environm ents:– For plug-n-play content tool integration and reuse.For plug-n-play content tool integration and reuse.– To stream line validation readiness efforts and m odel developm ent.To stream line validation readiness efforts and m odel developm ent.– To help autom ate validation tasks and debug.To help autom ate validation tasks and debug.

Take Leadership in transforming academic research to Take Leadership in transforming academic research to industrial useindustrial use

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