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User Guide

Keysight DisplayPort Extended TestsN5990A-156 Embedded DisplayPortN5990A-157 DisplayPort Type-C (via USB-C)

Calibration and Test Procedure Descriptions

Notices© Keysight Technologies 2017

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Manual Part NumberN5990-91200

Edition

Edition 2.0, February 2017

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2 Keysight N5990A - 156 & 157 DisplayPort Extended Tests User Guide

Keysight N5990A - 156 & 157 DisplayPort Extended Tests User Guide 3

Contents

1 Introduction

2 ValiFrame DisplayPort Station

Configure DUT 8Source Test Configuration 11

3 Basic Informations about Calibration and Test Procedures

4 Connection Diagrams

Connection Diagrams for Embedded DisplayPort 16J-BERT N4903B Configuration 16J-BERT M8020A Configuration 20J-BERT N4903B and Switch Configuration 23J-BERT M8020A and Switch Configuration 25Switch Connections 27

Connection Diagrams for DisplayPort Type-C 28ParBERT Configuration 28J-BERT N4903B Configuration 35J-BERT M8020A Configuration 40J-BERT N4903B and Switch Configuration 45J-BERT M8020A and Switch Configuration 49Testing Type-C Dongle DUTs 52Using differential probe in calibration procedures 53Switch connections in Type-C tests 54


Contents

5 Sink Calibration Procedures

Calibration Overview 56

Embedded DisplayPort Sink Cal ibrations 57ISI Calibration 57Random Jitter Calibration 60Fixed Sinusoidal Jitter Calibration 63Eye Opening Calibration 66Aggressor Amplitude Calibration 69

DisplayPort Type-C Sink Calibrations 73

6 Sink Test Procedures

Embedded DisplayPort Sink Tests 76Jitter Tolerance Test 76

DisplayPort Type-C Sink Tests 80

7 Source Test Procedures

Keysight DisplayPort Extended Tests N5990A -156 Embedded DisplayPortN5990A-157 DisplayPort Type-C (via USB-C)

User Guide

1 Introduction

The BitifEye “ValiFrame” Test Automation software is globally marketed and supported by Keysight Technologies (formerly Agilent Technologies) as N5990A.

This document describes the calibrations and test procedures, conducted by the extension modules, for sink tests Embedded Display Port and Display Port Type-C in detail.

The software implements the compliance tests according to the requirements of the eDP1.4 and DP 1.2b MOI (Method of Implementation) draft, and also offers some additional custom characterization tests to provide more details of the DUT (Device Under Test) behavior beyond the limits of compliance testing.

NOTEPlease regard, that eDP or DP-Type-C are supplements to the standard ValiFrame-Display Port-Module. They only work in conjunction with a basic license for this.


User Guide


Configure DUT / 8

Refer to the documentation of the Display Port Base Module N5990A for fundamental user instructions and software usage like installing, Station Configuration, supported instruments and so on.



Configure DUT

After starting the DisplayPort program, you need to configure the DUT specifications.

If you have licensed the modules eDP (for embedded DisplayPort) or DP Type-C (for DisplayPort via USB-C AltMode), you have additional options in the basic Configure Dialog (see Figure 1, Figure 2 and Figure 3).

Figure 1 Configuration Parameters for Type-C devices


ValiFrame DisplayPort Station 2

Figure 2 Basic Configuration Parameters for Embedded DisplayPort



Figure 3 Sink Basic Configuration Parameters (for Embedded DisplayPort)

Table 1 lists the additional options for eDP and DP Type-C modules.

Table 1 Additional DUT Parameter List for extension modules

Parameter name Parameter Description

Products Parameter

Product Type The product type can be chosen additionally as:• eDP Sink: Embedded displays.• eDP Source: Motherboards, ICs and Graphic Cards.

CTS Version For eDP, you can choose different parameter sets defined for your needs and derived from latest CTS eDP 1.4For DP Type-C choose the DisplayPort CTS 1.2b.

Test Parameters

Fixture Type For testing Type-C devices or hosts, choose the fixtures “Type-C“.

Dongle DUT If the DUT is a Dongle converter from USB Type-C to other video formats, choose this check box. In this case, some tests are omitted.


ValiFrame DisplayPort Station 2

Source Test Configuration

Source test license for eDP and DP Type-C is included in the standard DisplayPort source test license. For more information, refer to the basic DisplayPort manual.


User Guide

3 Basic Informations about Calibration and Test Procedures

The ValiFrame software suite offers a wide range of features for automated and reproducible tests. For the extended DisplayPort modules, they are the same as for basic DisplayPort module. To get all necessary informations about these common features, refer to the corresponding chapter in the base manual.


User Guide


Connection Diagrams for Embedded DisplayPort / 16

Connection Diagrams for DisplayPort Type-C / 28



Connection Diagrams for Embedded DisplayPort

Use the required instrument list according to the MOI for DP1.2b for each configuration, because a MOI eDP1.4 does not exist.

The software only supports the pattern generators J-BERT N4903B and J-BERT M8020A, however, ParBERT isn’t supported by eDP.

J-BERT N4903B Configuration

Calibrations

For calibrations using the J-BERT N4903B configuration, use the connection diagram as shown in Figure 4.

Figure 4 Connection Diagram for eDP J-BERT N4903B Calibrations


Connection Diagrams 4

Instructions:

• Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and 60 ps TTCs.

• Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the Product Configuration) via blocking capacitors and 150 ps TTCs.

• Connect the power divider outputs to the aggressor lanes of the DisplayPort Plug fixture.

• Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).

• Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the negative clock output.

• Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.

Aggressor Amplitude Calibration

For Aggressor Amplitude Calibration using the J-BERT N4903B configuration, use the connection diagram as shown in Figure 5.

Figure 5 Connection Diagram for eDP J-BERT N4903B Aggressor Amplitude Calibration



Instructions




• Connect one of the aggressor lanes (any lane other than the lane under test) from the DisplayPort Receptacle fixture to the oscilloscope in the following way depending on the selection of scope connection type:

• Differential Probe should be connected to CH1of the oscilloscope.

• Direct SMA connections should be connected to CH1 and CH3 of the oscilloscope.


• Connect a 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.

Sink Tests

For Sink tests using the J-BERT N4903B configuration, use the connection diagram as shown in Figure 6.



Figure 6 Connection Diagram for eDP J-BERT N4903B Sink Tests

Instructions




• Connect the AUX Controller to the DisplayPort Plug fixture.

• Connect the DisplayPort Plug fixture to the DUT.



J-BERT M8020A Configuration

Calibrations

For calibrations using the J-BERT M8020A configuration, use the connection diagram as shown in Figure 7.

Figure 7 Connection Diagram for eDP J-BERT M8020A Calibrations

Instructions


• Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.


• Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope in the following way depending on the election of scope connection type:

• Differential Probe should be connected to CH1of the oscilloscope

• SMA connections should be connected to CH1 and CH3 of the oscilloscope






For Aggressor Amplitude Calibration using the J-BERT M8020A configuration, use the connection diagram as shown in Figure 8.

Figure 8 Connection Diagram for eDP J-BERT M8020A Aggressor Amplitude Calibration

Instructions




• Connect one of the aggressor lanes (any lane other than the lane under test) from the DisplayPort Receptacle fixture to the oscilloscope in the following way depending on the election of scope connection type:







Sink Tests

For Sink tests using the J-BERT M8020A configuration, use the connection diagram as shown in Figure 9.

Figure 9 Connection Diagram for eDP J-BERT M8020A Sink Tests

Instructions








J-BERT N4903B and Switch Configuration

Calibration

For calibrations using the J-BERT N4903B and switch configuration, use the connection diagram as shown in Figure 10.

Figure 10 Connection Diagram for eDP J-BERT N4903B and Switch Calibrations

Instructions

• Connect the J-BERT data output to the switch, according to the detailed switch connections (refer to Connection Diagrams for DisplayPort Type-C on page 28), via blocking capacitors and 60 ps TTCs.


• Connect the power divider outputs to the switch according to the detailed switch connections.

• Connect the switch outputs to the DisplayPort Plug fixture.

• Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope in the following way depending on the selection of scope connection type:







Sink Tests

For Sink tests using the J-BERT N4903B and switch configuration, use the connection diagram as shown in Figure 11.

Figure 11 Connection Diagram for eDP J-BERT N4903B and Switch Sink Tests

Instructions

• Connect the J-BERT data output to the to the switch, according to the detailed switch connections (refer to Connection Diagrams for DisplayPort Type-C on page 28), via blocking capacitors and 60 ps TTCs.








J-BERT M8020A and Switch Configuration

Calibrations

For calibrations using the J-BERT M8020A and switch configuration, use the connection diagram as shown in Figure 12.

Figure 12 Connection Diagram for eDP J-BERT M8020A and Switch Calibrations

Instructions





• Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope in the following way depending on the election of scope connection type:


• Direct SMA connections should be connected to CH1 and CH3 of the oscilloscope





Sink Tests

For Sink tests using the J-BERT M8020A and switch configuration, use the connection diagram as shown in Figure 13.

Figure 13 Connection Diagram for eDP J-BERT M8020A and Switch Sink Tests

Instructions









Switch Connections

The switch connection diagram for eDP, is the same as that for standard DisplayPort. So, refer to the base documentation for DisplayPort Valiframe Software, to get the necessary informations about setting up the switch and the connections to the instruments.



Connection Diagrams for DisplayPort Type-C

The connection diagrams for DP Type-C are based on the MOI for DP1.2b, so use the Equipment List in Appendix A of this MOI.

ParBERT Configuration

Calibrations

For calibrations using the ParBERT configuration, use the connection diagram as shown in Figure 14.

Figure 14 Connection Diagram for DP-Type-C Calibrations with ParBERT and ISI Box

NOTEThe Type-C fixtures are symmetrical and can be connected in two directions. They should be connected reversal, i.e.Tx1 of one fixture has been connected to Tx2 of the other fixture (instead of Tx1).



Instructions

• Connect the vector signal generator RF OUTPUT to the first ParBERT clock module CLK INPUT.

• Connect the function/arbitrary generator OUT 1 to the ParBERT generator DELAY CTRL input of the first ParBERT group.

• Connect the data output OUT of the data ParBERT generator group to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek box was not selected, use your own ISI Adjustment).

• Connect the Artek CLE1000-A2 output to the lane under test of the USB-C Plug fixture.

• Connect the aggressor lanes via blocking capacitors and 150 ps TTCs to the USB-C Plug fixture according to your setup.

• With power divider, connect the data output of the first clock ParBERT generator to the 3- or 4-way power dividers. Connect the power divider outputs to the aggressor lanes of the fixture.

• Without power dividers, connect each output of the clock ParBERT generators to each aggressor lane of the USB-C Plug fixture.

• Connect the lane under test from the USB-C Receptacle fixture to the oscilloscope in the following way depending on the election of scope connection type:



• Connect CH4 of the oscilloscope to the clock output of the first data ParBERT generator group.

• Connect a 50 Ω terminations to the aggressor lanes of the USB-C Receptacle fixture.


For Aggressor Amplitude Calibration using the ParBERT configuration, use the connection diagram as shown in Figure 15.



Figure 15 Connection Diagram for DP-Type-C Aggressor Amplitude Calibrations with ParBERT and ISI Box

Instructions






• With power divider: connect the data output of the first clock ParBERT generator to the 3- or 4-way power dividers. Connect the power divider outputs to the aggressor lanes of the fixture.

• Without power dividers: connect each output of the clock ParBERT generators to each aggressor lane of the USB-C Plug fixture.



• Connect one of the aggressor lanes (any lane other than the lane under test) from the USB-C Receptacle fixture to the oscilloscope according to the selected way: either with Differential Probe (connected to CH1, refer to Figure 33 on page -53) or directly with SMA connections (connected to CH1 and CH3).

• Connect CH4 of the oscilloscope to the clock output of the first data ParBERT generator group.

• Connect 50 Ω terminations to the aggressor lanes of the USB-C Receptacle fixture.

Skew Calibration

Skew calibration test procedure is available in Expert Mode. It‘s the same connection diagram as described in the manual for base DisplayPort software.

Sink Tests

For Sink tests using the ParBERT configuration use the connection diagram shown in Figure 16.



Figure 16 Connection Diagram for DP Type-C Sink Test with ParBERT

Instructions










• Connect the AUX Controller to the Type-C Plug fixture.

• Connect the wires Vbus, GND, CC1 And CC2 of the Type-C Plug fixture to the correspondent wires of an appropriate USB-C source device (mobile phone, tablet, interface board or similar).

• Connect the Type-C Plug fixture to the DUT.

Zero-Length Tests

For Zero-Length tests using the ParBERT configuration use the connection diagram shown in Figure 17.

Figure 17 Connection Diagram for DP Type-C Zero-Length Test with ParBERT



Instructions



• Connect the data output OUT of the data ParBERT generator group to the lane under test of the Type-C Plug fixture via blocking capacitors and 60ps TTCs (no ISI channel).

• Connect the aggressor lanes via blocking capacitors and 150 ps TTCs to the Type-C Plug fixture according to your setup.




• Connect the wires Vbus, GND, CC1 And CC2 of the Type-C Plug fixture to the correspondent wires of an appropriate USB-C source device (mobile phone, tablet, interface board or similiar)


NOTEIn DisplayPort Software version 2.40 or later, the ISI-Box can remain in the setup during the zero length test. It is disabled and doesn’t apply extra ISI to the test signal.



J-BERT N4903B Configuration

Calibrations

For calibrations using J-BERT N4903B configuration use the connection diagram shown in Figure 18.

Figure 18 Connection Diagram for DP Type-C Calibrations with J-BERT N4903B and ISI Box

Instructions

• Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek box was not selected, use your own ISI Adjustment).

• Connect the Artek CLE1000-A2 to the lane under test of the Type-C Plug fixture.


• Connect the power divider outputs to the aggressor lanes of the Type-C Plug fixture.

• Connect the lane under test from the Type-C Receptacle fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1, refer to Figure 33 on page -53) or directly with SMA connections (connected to CH1 and CH3).




• Connect 50 Ω terminations to the aggressor lanes of the Type-C Receptacle fixture.


For Aggressor Amplitude Calibration using the J-BERT N4903B configuration use the connection diagram shown in Figure 19.

Figure 19 Connection Diagram for DP Type-C Aggressor Amplitude Calibration with J-BERT N4903B and ISI Box

Instructions







• Connect one of the aggressor lanes (any lane other than the lane under test) from the Type-C Receptacle fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1, refer to Figure 33 on page -53) or directly with SMA connections (connected to CH1 and CH3).



Sink Tests

For Sink tests using the J-BERT N4903B configuration use the connection diagram shown in Figure 20.

Figure 20 Connection Diagram for DP Type-C Sink Tests with J-BERT N4903B



Instructions:








Zero-Length Tests

For Zero-Length tests using the J-BERT N4903B configuration use the connection diagram shown in Figure 21.



Figure 21 Connection Diagram for DP Type-C Zero Length Tests with J-BERT N4903B

Instructions

• Connect the J-BERT data output to the lane under test of the Type-C Plug fixture via blocking capacitors and 60 ps TTCs.




• Connect the wires Vbus, GND, CC1 And CC2 of the Type-C Plug fixture to the correspondent wires of an appropriate USB-C source device (mobile phone, tablet, interface board or similar)




J-BERT M8020A Configuration

Calibrations

For calibrations using the J-BERT M8020A configuration use the connection diagram shown in Figure 22.

Figure 22 Connection Diagram for DP Type-C Calibrations with J-BERT M8020A and ISI Box

Instructions












For Aggressor Amplitude Calibration using the J-BERT M8020A configuration use the connection diagram shown in Figure 23.

Figure 23 Connection Diagram for DP Type-C Aggressor Amplitude Calibration with J-BERT M8020A and ISI Box



Instructions





• Connect one of the aggressor lanes (any lane other than the lane under test) from the Type-C Receptacle fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1, refer to Figure 33 on page -53) or directly with SMA connections (connected to CH1 and CH3).



Sink Tests

For Sink tests using the J-BERT M8020A configuration use the connection diagram shown in Figure 24.



Figure 24 Connection Diagram for DP Type-C Sink Tests with J-BERT M8020A

Instructions










Zero-Length Tests

For Zero-Length tests using the J-BERT M8020A configuration use the connection diagram shown in Figure 25.

Figure 25 Connection Diagram for DP Type-C Zero Length Tests with J-BERT M8020A

Instructions

• Connect the J-BERT data output to the lane under test of the Type-C Plug fixture via blocking capacitors and 60 ps TTCs.








J-BERT N4903B and Switch Configuration

Calibrations

For calibrations using the J-BERT N4903B and switch configuration use the connection diagram shown in Figure 26.

Figure 26 Connection Diagram for DP Type-C Calibrations with J-BERT N4903B and Switch




Instructions

• Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs.

• Connect the Artek CLE1000-A2 to the switch according to the detailed switch connection description in J-BERT M8020A and Switch Configuration on page 25.


• Connect the power divider outputs to the switch according to the detailed switch connection description in J-BERT M8020A and Switch Configuration on page 25.

• Connect the switch outputs to the Type-C Plug fixture.




Sink Tests

For Sink tests using the J-BERT N4903B and switch configuration use the connection diagram shown in Figure 27.



Figure 27 Connection Diagram for DP Type-C Sink Tests with J-BERT N4903B and Switch

Instructions











Zero-Length Tests

For Zero-Length tests using the J-BERT N4903B and switch configuration use the connection diagram shown in Figure 28.

Figure 28 Connection Diagram for DP Type-C Zero-Length Test with J-BERT N4903B and Switch

Instructions

• Connect the J-BERT data output to the switch, according to the detailed switch connection description in J-BERT M8020A and Switch Configuration on page 25, via blocking capacitors and 60 ps TTCs.


• Connect the power divider outputs to the switch according to the detailed switch connection description in s J-BERT M8020A and Switch Configuration on page 25.




• Connect the Type-C Plug fixture to the DUT



J-BERT M8020A and Switch Configuration

Calibrations

For calibrations using the J-BERT M8020A and switch configuration use the connection diagram shown in Figure 29.

Figure 29 Connection Diagram for DP Type-C Calibrations with J-BERT M8020A and Switch

Instructions










• Connect 50 Ω terminations to the aggressor lanes of the Type-C Receptacle fixture

Sink Tests

For Sink tests using the J-BERT M8020A and switch configuration use the connection diagram shown in Figure 30.

Figure 30 Connection Diagram for DP Type-C Sink Tests with J-BERT M8020A and Switch

Instructions


• Connect the Artek CLE1000-A2 to the switch according to the detailed switch connection description in Switch connections in Type-C tests on page 54.




• Connect the power divider outputs to the switch according to the detailed switch connection description in Switch connections in Type-C tests on page 54.





Zero-Length Tests

For Zero-Length tests using the J-BERT M8020A and switch configuration use the connection diagram shown in Figure 31.

Figure 31 Connection Diagram for DP Type-C Zero-Length Test with J-BERT M8020A and Switch



Instructions

• Connect the J-BERT data output to the switch, according to the detailed switch connection description in J-BERT M8020A and Switch Configuration on page 25. Use blocking capacitors and 60 ps TTCs.







Testing Type-C Dongle DUTs

If the software was configured with the option “Dongle DUT” (see Configure DUT on page 8), it is possible to test video converter dongles (e.g. DP-to-HDMI-converters).

This implicates some differences to standard DP Type-C sink DUTs:

• The dongle itself has a Type-C plug, so we need a receptacle fixture instead of a plug fixture. Furthermore, the calibrations are made with a plug instead of a receptacle fixture. So in all connection diagrams, plug and receptacle fixtures are swapped.

• The dongle converter is intended to be plugged in directly into the source. Therefor, all tests are made with zero cable length, that means no extra applied ISI.



Figure 32 Connection Detail for Dongle DUT

Using differential probe in calibration procedures

If you are using a differential probe in the calibration procedure, you have to take care of

• selecting the right probe-type in the setup of the scope channel.

• terminating the middle connector of the probe with a short. Don‘t use a 50 Ω terminator for this.

Figure 33 Connection Detail of using the Differential probe



Switch connections in Type-C tests

When the switch is used, the connection diagram is shown in two images. The first image illustrates the complete setup, and the switch is represented as a gray box (see Figure 26 to Figure 31). Clicking on the button “Show Switch Connection” changes to the second image. This one shows just the switch matrix with its input and output connections in detail (Figure 34).

Pressing the button “Show General Connections” returns to the entire-setup diagram.

Figure 34 Connection Diagram for Switch Connections with DP Type-C plug


User Guide


Calibration Overview / 56

Embedded DisplayPort Sink Calibrations / 57

DisplayPort Type-C Sink Calibrations / 73

To get reliable results during automated tests of a DUT, first the instrument setup needs to be calibrated.



Calibration Overview

For principles and basic parameters of the calibration procedures, refer to the base manual of DisplayPort Valiframe Software.


Sink Calibration Procedures 5

Embedded DisplayPort Sink Calibrations

The Calibration procedures for eDP is different.

This section contains the set of calibrations required for the eDP Sink test procedures.

The calibrations are organized in groups depending on the following data rate:

• Reduced Bit rate (1.62 Gbps)

• Rate_2 (2.16 Gbps)


• High Bit rate (2.7 Gbps)



• High Bit rate 2 (5.4 Gbps)

ISI Calibration

Purpose

This procedure is used to calibrate the ISI.

There is a separate calibration for each supported data rate.

Procedure

For this purpose, either the EzJit+ application or the Histogram on the real-time scope can be used. All jitter components are disabled and the HBR2 Compliance Pattern (CP2520) is set for every data rate.

There is no ISI generator, so the ISI value is just measured and averaged over a number of cycles. To get the ISI value, DDJ(p-p) is measured with EzJit+ or the histograms are used to measure TJ.

This calibration always passes because there is no target ISI value.

Connection Diagram

Follow the pictures of the Connection Diagrams section (Chapter 4, Connection Diagrams) depending on your configuration.



Parameters

The parameters used in expert mode for this calibration are:

• Calibration

• Oscilloscope Bandwidth

• Measured ISI with histogram

• Measured Depth

• Measurement Cycles

• Pattern

• Sequence File

• Aggressor Clock Divider

• Pattern Period Length

• Pattern Period Length Auto Detect

• PLL

• Loop Bandwidth

• Damping Factor

• Voltages

• Differential Voltage

These parameters are described in the “Table 5-1: Sink Calibration Parameters” in the base manual of DisplayPort Valiframe Software.

Dependencies

No calibrations are required for this method.

Results

An example of HTML viewer for the ISI Calibration procedure is shown in Figure 35. The results comprise:

• The common parameter list (in expert mode)

• A calibration data table for the ISI that is being calibrated (see Table 2)



Figure 35 Example of HTML Viewer for eDP ISI Calibration

Table 2 Data Table for eDP ISI Calibration


Result This calibration always passes.

Measured ISI The averaged value of the ISI measurements.



Random Jitter Calibration

Purpose

This calibration calibrates the random jitter (RJ).


Procedure

For this purpose the EzJit+ application running on the real-time scope is used. The test automation starts by applying small RJ amplitudes and increases them. For every set RJ value, the corresponding amplitude is measured and averaged over a number of cycles.

Connection Diagram


Parameters


• Calibration



• Jitter

• Use Explicit Clock

• Stop Jitter

• Jitter Step Count

• Pattern

• Sequence File




• Voltages





Dependencies

The calibrations required for this method is:

• ISI Calibration

Results

An example of HTML viewer for the Random Jitter Calibration procedure is shown in Figure 36. The results comprise:

• A calibration data graph


• A calibration data table for the Random Jitter that is being calibrated (see Table 3)



Figure 36 Random Jitter Calibration



Table 3 Data Table for eDP Random Jitter Calibration

Fixed Sinusoidal Jitter Calibration

Purpose

This calibration calibrates the fixed sinusoidal jitter (SJFIXED), which consists of sinusoidal jitter of 200 MHz frequency.


Procedure

For this purpose the EzJit+ application running on the real-time scope is used. The test automation starts with small SJ amplitudes and increases and measures them for each set amplitude. It is averaged over a number of cycles.

Connection Diagram


Parameters


• Calibration



• Jitter

• Use Explicit Clock

• Stop Jitter

• Jitter Step Count

• Pattern

• Sequence File



Set Jitter The applied random jitter value.

Actual Jitter The measured random jitter value.





• Voltages



Dependencies

The calibration required for this method is:

• ISI Calibration

Results

An example of HTML viewer for the Fixed Sinusoidal Jitter Calibration procedure is shown in Figure 37. The results comprise:



• A calibration data table for the Sinusoidal Jitter that is being calibrated (see Table 4)



Figure 37 eDP Fixed Sinusoidal Jitter Calibration



Table 4 Data Table for eDP Fixed Sinusoidal Jitter Calibration

Eye Opening Calibration

Purpose

This calibration calibrates the eye opening at TP3_EQ.


Procedure

It starts with large amplitude and all the jitter impairments (RJ, SSC, SJFIXED, and SJSWEEP) are applied to the data signal. Aggressor signals are not considered for this calibration. The scope is configured to show the real-time eye.

The test automation uses the location between 37.5% and 62.5% of the horizontal UI, where the eye opening is maximum, for measurement.

After that, the generator output voltage is decreased and the same measurement is repeated. This allows an amplitude range to be calibrated. The eye opening is measured and averaged over a number of cycles.

Connection Diagram


Parameters


• Calibration


• Memory Depth


• Jitter

• RJ Amplitude (RMS)


Set Jitter The applied random jitter value.

Actual Jitter The measured random jitter value.



• Fixed SJ Amplitude

• Fixed SJ Frequency

• SJ Frequency

• Pattern

• Sequence File


• PLL

• Loop Bandwidth

• Damping Factor

• Voltages

• First Differential Voltage

• Minimum Eye Opening

• Applied Voltage Step


Dependencies

The calibrations required for this method are:

• ISI Calibration

• RJ Jitter Calibration

• High Speed Sinusoidal Jitter Calibration

• Fixed Sinusoidal Jitter Calibration

Results

An example of HTML viewer for the Eye Opening Calibration procedure is shown in Figure 38. The results comprise:



• A calibration data table for the Eye that is being calibrated (see Table 5)



Figure 38 Example HTML Viewer for eDP Eye Opening Calibration



Table 5 Data Table for eDP Eye Opening Calibration


Purpose

This calibration calibrates the differential output voltage of the aggressor signal.


Procedure

The test automation starts by applying a high differential voltage and decreases it in each step. The corresponding aggressor signal amplitude is measured on the scope.

Connection Diagram


Parameters


• Calibration


• Memory Depth


• Pattern

• Sequence File


Set Voltage The generator set output voltage.

Measured Voltage Measured eye opening with the scope




• Voltages

• First Differential Voltage

• Minimum Eye Opening

• Applied Voltage Step


Dependencies

No calibrations are required for this method.

Results

An example of HTML viewer for the Aggressor Amplitude Calibration procedure is shown in Figure 39. The results comprise:



• A calibration data table for the Aggressor Amplitude that is being calibrated (see Table 6)



Figure 39 eDP Aggressor Amplitude Calibration



Table 6 Data Table for eDP Aggressor Amplitude Calibration


Set Voltage Set Clock Generator output voltage.

Measured Voltage Measured aggressor signal voltage.



DisplayPort Type-C Sink Calibrations

The calibration procedures for DP Type-C are the same as for Standard DisplayPort. So, refer to the base manual of DisplayPort to get all relevant informations about calibrating your setup.


User Guide


Embedded DisplayPort Sink Tests / 76DisplayPort Type-C Sink Tests / 80

For basic informations about sink test procedures, refer to the main manual of DisplayPort module.



Embedded DisplayPort Sink Tests

The Sink tests for Embedded DisplayPort are implement according to the eDP 1.4 CTS.

The Sink test groups are divided by lane (1–4), and subdivided by supported data rate (Reduced Bit rate, Rate_2, Rate_3, High Bit rate, Rate_5, Rate_6, High Bit rate 2) and SJ Frequency (2.1, 9, 18 and 90 MHz).

Jitter Tolerance Test

Purpose

This test procedure is described in the eDP 1.4 compliance test specification. It generates a stressed eye and verifies that the receiver sustains a BER of 10e–9.

Procedure

The test automation sets up the instrument with the calibrated amplitudes and jitter values required by the specification. First, it runs the link training, which is done in two steps: frequency and symbol lock phase. Afterward, the data pattern is applied (CP2520) and the error counter started. A count-down timer is displayed and, when it is finished, the result of the test is decided depending on the number of errors.

Connection Diagram

Follow the pictures of the Connection Diagrams section ( Chapter 4, Connection Diagrams) depending on your configuration.

Parameters


• Bit Error Rate Testing

• Link Quality Pattern Hint

• Allowed Number of Errors

• Observation Time

• DPCD

• Extra DPCD

• Extra DPCD Order

• Jitter


Sink Test Procedures 6

• RJ Amplitude (RMS)

• Fixed SJ Amplitude (pk–pk)

• Fixed SJ Frequency

• SJ via Clock Jitter

• Pattern

• Sequence File


• SSC

• Use SSC

• SSC Frequency

• SSC Amplitude

• Voltage Levels

• Tested lane voltage

• Aggressor Lane Voltage


Dependencies

The calibrations required for this method are:

• ISI Calibration

• RJ Jitter Calibration

• Fixed Sinusoidal Jitter Calibration

• Eye Opening Calibration

• Aggressor Amplitude Calibration

Results

An example of HTML viewer for the Jitter Tolerance Test procedure is shown in Figure 40. The results comprise:

• The common parameter list (in expert mode).

• A data table for the Result (see Table 7).



Figure 40 Example HTML Viewer for eDP Jitter Tolerance Test

Table 7 Data Table for eDP Jitter Tolerance Test


Result Pass/Fail, pass means this test was passed.

Jitter Frequency The frequency of the sinusoidal jitter injected during the test.

Sinusoidal Jitter Amplitude

The amplitude of the sinusoidal jitter injected during the test.

Number of Errors The number of errors counted during the test.


Sink Test Procedures 6

Min Spec The minimum allowed number of errors.

Max Spec The maximum allowed number of errors.

Details Description of the possible problems found during the test.




DisplayPort Type-C Sink Tests

The sink tests for DisplayPort Type-C are the same as for standard DisplayPort. So, refer to the basic manual to get all relevant informations about them.


User Guide

7 Source Test Procedures

Source test procedures for eDP are included in the basic license for DisplayPort Valiframe Software. The measurements are conducted by the Keysight oscilloscope application.

For further informations about these test procedures, refer to the basic manual.

This information is subject to change without notice.© Keysight Technologies 2017Edition 2.0, February 2017

www.keysight.com

http://www.keysight.com

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