Precision Test Solutions To

Maximize Yield and Reduce

Catastrophic Risk In Today’s

Smaller Geometry ICs

Analyze • Detect • Measure • ControlTM

KeyTek ESD & Latch-Up Test Systems

When Electronic Device Failure Is Not An Option

Increased integration of functionalityon single, smaller geometry devicessignificantly increases the real risk ofdevice failure due to ESD (ElectrostaticDischarge). And it’s a fact: ESD hazards are a leading cause of devicefailure in the field today. This risk factor has widespread and potentiallycatastrophic implications: it can impactboth product "time to market" cycles,as well as end-product reliability. If notaddressed, these issues could resultin severe financial consequences.

Experience the many benefits ofworking together with recognizedexperts in the field of ESD & Latch-Uptesting. Our commitment to the discipline—and to the semiconductorindustry—is wide ranging; we activelylead and participate on global standards committees and havehelped define test methodologies toachieve regulatory standards and product quality objectives.

Our goal is to support you with lifelong service—from applicationssupport, calibration services, and preventative maintenance to full technical field support.

Precision KeyTek semiconductor ESD& latch-up test systems can help youdesign and produce more reliable electronic products while achievingoptimum IC production output. It’swhat the market demands. And it’s a mission we share.

Minimize uncertainty. ESD and Latch-Up testing can be an arduousprocess. Defining quality standardsand test methodologies for yourdevices. Determining the right systems to meet your parameters—both now and in the future. Rapidacquisition of the correct test systemsto achieve your objectives. Maximizingyield critical to your success.

Thermo has your solution.

It begins with people of technologyworking with people of technology.Specialists understanding the challenges you face. Talking the same language. Rolling up oursleeves with you to solve the problemat hand. Questioning everything. And anticipating the consequences ofevery action we take. With fervor andcommitment.

So if you’re a semiconductor qualityprofessional, test engineer or devicedesigner, let us help you achieve yourgoals with a solution tailored to yourspecific test requirements. Becauseby doing so, you’ll gain better controlof your IC design and manufacturingprocess. You speed time-to-marketcycles. And you take a proactiveapproach to reducing the uncertaintyof semiconductor development andmanufacturing.

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Best practices. Fulfilling expectations. Today, Thermo hasaligned its operations to focus on fullymeeting—and exceeding—customer expectations at every level. And astechnologies and regulatory issuesevolve, to address change factors withresponsive solutions. You only have totour our manufacturing facility tounderstand how this commitmentbenefits our customers. And you’reinvited.

What you’ll see is people driving technology. Translating "lean manufacturing" into customer-focusedproduct development. And acceptingthe responsibility to make it happen,both rapidly and cost effectively.Building in quality throughout theprocess.

Understanding that it’s not just whatyou do, but what you don’t do that canmean the difference between successand "lost opportunity." With all its ramifications.

Then, helping you to best utilize yourtest systems with applications supportand training. And very importantly,responsive customer service.Transforming precision semiconductortest technology into indispensable productivity tools that optimize yourcapabilities and yield. And your return on investment.

You have expectations for your testsystems and for your success. Forthe people at Thermo, it’s our businessto fulfill them.

There’s always an appropriate and cost-effective test strategy to achieveyield objectives. It’s a fact. Rarely,however, does it identify itself.

But with the resources and expertisethe people of Thermo bring to bear,together we’ll find it.

And in doing so, help take you, yourorganization, and its products to thenext level of success.

KeyTek ESD and Latch-Up TestTechnology For SemiconductorDesigners and Manufacturers

As the semiconductor industryevolves to meet the requirementsof today’s higher performance electronic products, advances indevice geometries and I/C packageslead to increased sensitivity andsusceptibility levels of individualdevices to ESD (ElectrostaticDischarge) events.

Larger ICs. Smaller internalgeometry. More integrated functions. The fact is today manyintegrated circuits are getting larger;system-on-a-chip (SOC) is drivingtheir internal geometry, and it is getting smaller. The demand forspeed requires more function beintegrated into a single device andbetter heat dissipation. Specializeddevices are getting smaller andsmaller in order to be used in verysmall products such as hearingaids, implantable drug infusion systems, and microelectronic-machines (MEMS).

The single most important issuerelated to managing the impact ofESD on devices and packages isthe ability to test for the potentiallydestructive effects of ESD, identify,and then harden sensitive structures prior to full-scale production. This enables engineers and designers to makecost-effective and appropriate corrective actions in the development process, rather than after the fact.

Given the tremendously high cost of IC production, and today’scustomer demands for precisely-timed component delivery schedules, an investment in theright ESD test system can rapidlyreturn substantial dividends as aresult of the time, material and lostopportunity costs it can save. Withthe smallest system footprints, lowest in-use-cost and highestinstalled base, Thermo ElectronCorporation continues to lead theworld with widely accepted "wholeof test" solutions.

Thermo offers the correct KeyTekESD and Latch-Up test system yourequire for every critical step of thesemiconductor design and manufacturing process.

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Relay-Based Operation With 128,256, 384, 512, or 768 Pin TestCapabilities

The KeyTek ZapMaster® Mk.2 hasbeen developed in response toglobal market demands for products that are smaller, faster, and smarter.

A turnkey, field upgradeable testsystem, the KeyTek ZapMasterMk.2 test system allows you to testyour devices for ESD and Latch-Upsusceptibility from the designphase through the post-productionqualification stage in an efficientand cost-effective manner.

Building on legendary performanceand reliability. The KeyTekZapMaster Mk.2 has been designed and developed based onthe heritage of the testing reliability,accuracy and durability of the original KeyTek ZapMaster. In constant testing use since the late-eighties, the KeyTek ZapMasterhas been embraced by leadingmanufacturers around the world,with an installed user base thatnumbers well into the hundreds.

Features

• Test devices up to 768 pins; systems available configured as128, 256, 384, 512 or 768 pins.

• Compatible with ALL 256 pinKeyTek ZapMaster test fixtureswhen equipped with the optionalMk.2 to ZapMaster Carrier, andALL Verifier DUT fixtures whenequipped with the optional Mk.2to Verifier DUT adapter. (Bothcases require the system be configured with 512 or 768 pins.)

This eliminates the need for manufacturers with existingKeyTek systems to replace test fixtures – a tremendous cost savings!

• Human Body Model (HBM) perESDA STM5.1, JEDECEIA/JESD22-A114, MIL-STD 883Eand AEC Q100-002 specifications,50V to 8KV.

• Machine Model (MM) per ESDASTM5.2, JEDEC EIA/JESD22-A115, and AEC Q100-003, 50V to2KV.

• Latch-Up testing per JEDECEIA/JESD 78 and AEC Q100-004including preconditioning, stateread-back and full control of eachtest pin.

• Pin Drivers for use during Latch-Up testing and parametricmeasurements:

• Vector input capability fromstandard tester platforms,

• 64k vectors per pin with read-back, and;

• Up to 10MHz vector rate programmable from an internal clock to quickly setthe device into the desiredstate for testing.

• Up to six separate V/I supplies forDUT power, curve tracing, andlatch-up stimulus with 4-wiresensing at the DUT board for highaccuracy. System design alsoprovides high current capabilitydirectly through the V/I matrix.

• Multiple self-test diagnostic routines to ensure system integrity throughout the entirerelay matrix, right up to the testsocket.

• Test reports include pre-stress,pre-fail (ESD) and post-fail data, as well as full curve trace and specific data point measurements. Data can be exported for statistical evaluation and presentation.

• Individual pin parametrics allowthe user to define V/I levels, compliance ranges, and curvetrace parameters for each pin individually.

• Reliable, relay-based operationthat enables test speeds that are 5 to 10* times faster thanrobotic mechanical driven testers.This can dramatically reducedevice qualification time.

And, while test protocols will largely dictate test speeds, theKeyTek ZapMaster Mk.2 provides 8 DUT (device under test) test capability (total of 8, 16 pin DUT’swhen configured with 128 pins,DUT pin count increases with system pin count), which can substantially increase testingthroughput.

* When compared to existing roboticmechanical devices. Test protocol may limit test speeds.

KeyTek ZapM

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Features and Technical Specifications

Rapid, Easy-To-Use Testing Operations

• Control by the Windows®-basedsoftware is both intuitive andcomprehensive.

• Allows tests to be set up quickly,and helps keep operator and programmer training to a minimum.

• A powerful embedded VME controller, capable of handling an enormous amount of test program and result data, controlsthe system hardware.

• Eliminates unnecessary datatransfer and increases throughput, a real time-saverwhen evaluating large devices.

Consistent, Precise ESD Waveforms

By locating multiple discharge networks close to the test fixtureboard itself, unwanted stray induc-tance and capacitance is kept to aminimum at every pin. This insures:

• Excellent waveform quality, and;

• Highly repeatable and reproducible test data.

KeyTek ZapMaster Mk.2 ESD TestCapabilities

• Human Body Model (HBM) andMachine Model (MM) testing tothe most prevalent industry standards.

• Latch-Up Testing Per JEDEC’sEIA/JESD 78 Method (whenequipped with the Pin Driversoption).

• Equipped with Voltage andCurrent (V/I) power supplies, each of which has a wide dynamic range enabling them to force and measure signalsspanning from the milli-volt andnanoamp range, up to 100 voltsand 10 amps. Provides a fast andversatile means of making anynumber of DC parametric leakagemeasurements and Latch-Uptests, while offering total controland protection of the DUT.(Additional V/I supply configurations are also available.)

• Advanced device preconditioningcapability. The preconditioningoption allows the DUT to be vectored with complex test andvector patterns, which gives the test operator excellent experimental tools and full production test control over theDUT. Each device pin can be driven with vectors up to 64kdeep, at selectable speeds of upto 10MHz, and with the read backcapability on every pin, and devicestate, comprehensive state verification is fast and easy.

• Switching matrix provides consistent and repeatable ESDpaths; also allows any pin to begrounded, floated, vectored orconnected in any order, to any ofthe installed pulse sources or V/Isupplies (a maximum of 5 DUTV/I’s are available for biasing).

Define, achieve and sustain yourcomponent reliability objectives -today and tomorrow. Custom configuration options enable you topurchase a system to meet your initial test needs and budgets.Then, when corporate or industrystandards demand test systems to be upgraded, it can be done at yoursite to minimize down time andeliminate the need and expense of shipping the unit back to the factory.

The need to meet future industrytest standards is always a concernwhen evaluating test systems, but due to the system’s flexiblemodular design, meeting thesestandards in the future will be easier and very cost effective.

Available options include: additionalpins, V/I supplies, high speed vectoring capabilities, test featuresand pulse sources.

Super fast, reliable & compact ESD and Latch-Up Test System enables you to accelerate ESD & Latch-Up test speeds—in just 4 square feet offloor space.

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Reproduces Real World CDMEvents

The KeyTek RCDM3 is a fully-automated, PC-controlled system that enables the user totest devices and identify potentialCharged Device Model (CDM) ESDfailure problems prior to the releaseof a device for production.

The KeyTek RCDM3 meets the twodominant CDM test methods, andcan be ordered with either or bothof these standards:

• ESDA STM 5.3.1 • JEDEC, JESD22-C101

For a robotic CDM test, the deviceis generally charged in an electricfield by placing the device betweena charged surface and a groundplane. The discharge is performedby bringing a grounded dischargepin into contact with one of thepins of the charged device. Thedevice then rapidly discharges andthe process is repeated for otherpins under test.

In the KeyTek RCDM3, an eventdetector ensures that each pin isdischarged, ensuring proper alignment and contact between the device and the system pin. event detector illuminates a lamp

on the system and displays a symbol on the system controllervideo display each time a CDMevent occurs. The events arelogged in the software and reportedat the completion of the test, providing the user with confirmation that all pins are being discharged properly during

the test. Any non-stressed pins areidentified and can be targeted forretesting.

Because of the potentially destructive nature of a CDM event,manufacturers demand easy andaccurate test configuration to allowefficient device characterization.With the proliferation of devicetypes and requisite tests, it’s criticalthat the testers enable operators toquickly get new device tests up andrunning. The KeyTek RCDM3 offersunique features to ensure thefastest set-up and test throughputavailable.

The KeyTek RCDM3 is the onlytester with three independent cameras to allow fast, precisionalignment of a new device, andthereby ensuring the operator isrunning tests quickly and efficiently.

The Charged Device Model. In the1970’s, design and test engineersbegan testing devices to welldefined ESD pulses thought to berepresentative of human discharges(Human Body Model, or HBM) andof discharges from other items(Machine Model, or MM). Thermo,a pioneer in ESD test technology,participated with industry organizations to develop appropriateESD test protocols that would allowstandards to be used effectivelythroughout the entire semiconductor industry. However,these tests were not sufficient todetermine the ability of a device towithstand the effects of the devicebecoming charged during handling,and then quickly discharged whencoming in contact with a metal

handler, or any surface at a differentpotential.

During handling, a semiconductorpackage can become charged andthat charge is triboelectrically coupled to the internal structure ofthe device. If the package or any ofits pins come into contact with ametal surface, the device will discharge in picoseconds, withpeak currents on the order of 10’sof amps; a potentially destructiveESD event.

KeyTek RCD

M3

Features and Technical Specifications

Features

• A self-contained turnkey system.

• Charged Device Model testingper JEDEC Standard JESD22-C101, with full user control of all stress levels and polarities(RCDM-JEDEC).

• Charged Device Model testing per ESDA STM 5.3.1 specification, with full user control of all stress levels andpolarities (RCDM-ESDA).

• Three camera configuration provides easy pin positioning for rapid device set-up and programming. Once package outlines are programmed, theycan be easily saved for futureretrieval. Orthogonal views withwide view and close-up screensprovide easy pin location.

• Built-in vacuum device hold down system which makesdevice positioning fast and accurate; also enables the testingof devices of virtually any size orconfiguration.

• Built-in waveform monitor facilitates oscilloscope monitoringof the discharge pulse for waveform verification purposes.Calibration of the high voltagepower supply is made simple viaa software routine and a testpoint located on the front panel(where a convenient wrist strapground point is also located).

• Test devices of any configuration;device geometry is virtually unlimited including stab andsmart cards.

• Direct Charge method chargesthe DUT through a selected pin,then discharges that pin and/orthe selected pins sequentially, viathe discharge probe to ground.The user has full control of thepins to charge and discharge.

• Field-Induced Charge method elevates the entire DUT to theselected voltage by charging theisolated charge plate, which thedevice is located on. Then theselected pin is discharged via thedischarge pin to ground. The userhas full control of the pins tocharge and discharge.

• Windows®-based application software provides a user-friendlyinterface for device definition, test plan generation and DUT orientation.

• Pre-defined pin map screens facilitate pin location. Only a fewpins need to be located to definethe entire device.

• Zap detection circuit for confirmed discharge event.

• Totally enclosed test chamberallows convenient connection to test in inert gas atmosphere.

• System interlocks interrupt theinternal tester movement—as asafety precaution for both theoperator and DUT (Device Under Test). In the event of anemergency, a stop switch is located within easy reach forimmediate system shut down.

Designed For Years of DependableService. The KeyTek RCDM3 testsystem has been designed toaccommodate testing of virtuallyany size device package. A complete, value-packed system,the KeyTek RCDM3 will be an indispensable testing tool for yearsto come, particularly as devicepackage geometries become smaller and more powerful.

It requires only an oscilloscope (not included) to perform comprehensive Robotic CDM testing; all other equipment, andWindows®-based software is included, eliminating the need forfuture capital outlays for upgrades.

Three-camera robotic charged device model test system for advanced integrated circuit evaluation.

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A Breakthrough In HighBandwidth ESD Stress Simulation

The KeyTek Eclipse VF-TLP transmission line pulser is theworld’s first “high bandwidth” pulsecurve tracer. A turnkey high powerTime Domain Reflectometer, it facilitates engineering evaluation of semiconductor structures underdynamic stresses.

A flexible interactive design tool,the KeyTek Eclipse VF-TLP providesmultiple threat simulation—HBM,Fast HBM and CDM—at packageand wafer levels. It provides ESDfailure thresholds and detailed ESDprotection structure information toallow the designer to characterizethe robustness of the design in areal world environment.

The KeyTek Eclipse features the True Time Domain (TDR) measurement method. Thisenables future parameter extraction and accurate multiplethreat simulation. It also displaystest environment feedback.

CDM simulation capability enablescomplete device stress simulation;probing for weakness and permittingdesigners to test cutting edge "ultra-fast" protection structuredesign.

The system incorporates a highlyintuitive user interface with timesaving automation of test tasks. Allsystem parameters, measurementsand results are displayed graphicallyand results can be simply exportedfor inclusion in test reports.Calibration methods are easy and convenient.

The KeyTek Eclipse VF-TLP shortensthe protection structure design evaluation/performance evaluationcycle and speeds and gives devicedesigners the confidence to publishtheir devices to corporate functionallibraries, while reducing costlyscraping of early device runs (WIP).

An easily configured system, it iscompact, fast, and accurate andenables you to flawlessly executetests to ensure greatest yield.

KeyTek Eclipse VF-TLP Systems

Eclipse Alpha. An entry-levelturnkey system, with HBM and fastHBM capability .

Eclipse Gamma and EclipseEpsilon. More highly capable allowing faster event simulationrequired by the CDM event andoffering information that can assistin device parameter extraction.

When configured with user-suppliedequipment, KeyTek Eclipse VF-TLPtesters facilitate enhanced andcost-effective test capability.

Features

• True Time Domain (TDR) measurement method.

• Comprehensive calibrationmethodology.

• Integrated device leakage andcurve tracing.

• Optional TDRT and Current Probemode available.

• Simulates HBM, real HBM andCDM events.

• True positive and negative polarities.

• Ultra “clean” pulses.

• Comprehensive Data evaluation tools.

• Accurate 50 Ω system impedance.

• High test throughput.

• Complete device failure characterization.

• Biased and non-biased pulsing.

• High Peak current, 5 A (into 50 Ω), 10 A into short circuit.

• Packaged 48 pin device fixture included.

KeyTek Eclipse V

F-TLPFeatures and Specifications

An easily configured test system simulating Human Body Model (HBM),real HBM and Charged Device Model(CDM) threats.

KeyTek Eclipse VF-TLP

This sheet is for informational purpose only and is subject to change without notice. © 2003 Thermo Electron Corporation. All rights reserved. Thermo Electron Corporation, Question everything, and Analyze. Detect. Measure. Control. are trademarks of Thermo Electron Corporation.

Single Source, Total Semiconductor ESD & Latch-Up Test Solutions.

Specialists who understand the challenges you face. Innovative ideas. Leading technologies.Breadth of high yield semiconductor test equipment. Thermo—your semiconductor test solutionspartner. Contact us today for details.

Control Technologies Division One Lowell Research CenterLowell, MA 01852Formerly doing business as Thermo KeyTek

(978) 275-0800(978) 275-0850 fax

Analyze • Detect • Measure • ControlTM

www.thermo.com/esd