KGD Packaging and Test Workshop KGD Packaging and Test Workshop, Napa, CA, September 8, 2003...

KGDKGD Packaging and Test Workshop Packaging and Test Workshop, Napa, CA, September 8, 2003 PWB/Substrate Design Tutorial: Smith, Chang

PWB/Substrate Design Tutorial

Larry Smith, Ph.D.

Chi-Shih Chang, Ph.D

September 8, 2003


Organization of Tutorial

Product Design Considerations (Chi-Shih Chang) Evolution to System-in-a-Package (SiP)

Chip-on-Board (CoB)System-on-a-Chip (SoC) and Stacked-Die TradeoffsSiP Implementation

SiP and stacked die design considerationsSubstrate technologiesElectrical designThermomechanical designBare substrate testingAssembled substrate testing

PWB Design (Larry Smith) What’s different about PWB design using die products?

General design issuesWirebond designsFlip-chip designsCAD Tools


Introductions

Larry Smith Design Manager, K&S Substrate Division

BGA substrates for high IO flip-chip Program Manager, MicroModule Systems

MCMs, SiPs, microBGAs Module Manager, Dell Computer

MCM for high-volume notebook computers Technical Director, MCC Packaging/Interconnect/HVED

ProgramR&D Consortium: design, fabrication, assembly, test, program

management

Background High-density thin-film interconnect Electrical, thermal, mechanical modeling


Introductions (cont’d)

Chi-Shih Chang SMS Micro, Inc. provides consulting services for electronics

packaging and signal integrity VP of Adv. Products, High Connection Density, Inc. Strategic Applications Manager, K&S Senior Fellow, Sematech Member of the IBM Academy of Technology

Background Semiconductor devices, IC designs, and testing Electromagnetics and transmission lines Electrical design and signal integrity Packaging technologies ITRS AP-TWG member since 1995







Design issuesWirebond footprint creationFlip-chip escape routingCAD Tools


Chip-on-Board (CoB): WB ICs

Bond fingers beyond die edges, allowing less dense PWB line width and spacing

Footprint on PWB much less than that of QFP Reduced connection length between ICs, less series

resistance, inductance & parasitic capacitance Use low modulus die adhesive to buffer the mismatch of the

coefficient of thermal expansion (CTE) of IC and that of PWB Programmable wire bonding accommodates future die shrink

without PWB redesign Wafer-level test & burn-in, if needed


WB IC Example

Source: M. Roston, et. al., “Assembly Challenges Related to Fine Pitch In-Line and Staggered Bond Pad Devices,” Proc. 53rd ECTC, May 28-30, 2003, New Orleans, pp. 1334-1343.


Short Wire for High Speed Applications

I. Memis, “IBM’s Organic Chip Carrier Products: UFP Wire Bond, SLC Flip Chip, Hyper BGA Flip Chip,” SEMICON West, July 2001


CoB: WLP ICs

Area array solder pads underneath die at 0.5-0.4 mm pitch, allowing relatively small number of I/Os

Footprint on PWB less than that of WB ICs Further reduced connection length between ICs Should reduce I/O array footprint (thus # I/Os) to a fraction of

the die size to facilitate future die shrink Wafer-level test & burn-in preferred. They may be made at

die-level, if necessary


CoB: Solder Flip-Chip ICs

Area array solder pads underneath die at 0.15-0.25 mm pitch, allowing a large number of I/Os

Large number of I/O pads available for V/G connections, capable of carrying current for high power IC. They also reduce inductance and switching noise

Large number of signal I/Os for wide data bus Very small footprint on PWB High density PWB needed Mismatch in CTE of IC and that of PWB presents a problem

for large IC, requiring underfill encapsulation


Solder Ball Flip Chip IC Example


CoB: Adhesive Flip-Chip ICs

Peripheral as well as area array connection pads underneath die at 0.1-0.2 mm pitch, allowing the maximum number of I/Os

Extremely high density PWB needed, unless number of I/O rows being limited

Minimum footprint on PWB Adhesive serves the function of underfill encapsulant to

mitigate CTE mismatch concern Relatively low temperature at assembly Limited current carrying capability, not suitable for high

current IC









SoC & Stacked-Die Tradeoffs

SoC benefits Integrating additional functions/features, thus reducing

the required number of ICsExtremely wide bus between functions on ICHigh speed connections between functions on ICReduced board area occupied

SoC Product Consideration (next chart)


SoC in a Competitive Marketplace

Product life & market volume may be limited Commodity uP, uC, DSP, flash, SRAM have higher volume &

lower cost SoC targets a specific system product

Mask cost adder (approx. $ 1M per mask set) Wafer cost

Additional process steps required to integrated analog, DRAM, flash, … etc.

Yield loss associated with additional process steps

Design time / Time-to-market Require new IC design for each new product

Adding new product features for product upgrade Require new IC design when adding new features


Stacked-Die Packages

Commodity ICs: uP, uC, DSP, SRAM, DRAM, Flash, Analog, RF, GaAs, ...

Ease of useHigher level of reuse/lower costFaster time-to-market

ExamplesFlash on SRAM (smaller die on top)Flash on flash (same die size, a spacer needed)Memory on baseband ICProcessor on processor

Stacked-die enabling technologies Stacked-packages alternative


Stacked-Die Example -1


Stacked-Die Example - 2


Stacked-Die Enabling Technologies

Wafer thinning Die-to-die bonding Low loop height wire bonding Die attach control Thin and dense substrate High yield assembly process High quality die products Mechanical stress management Testing


Stacked-Packages Alternative

Larger footprint and larger height than stacked-die package Higher profile than stacked-die packages Flexibility in supply chain Test and burn-in at individual package level


Stacked-Package Comparison

Source: Y. Yano, et. al., “Three-dimensional Very Thin Stacked Packaging Technology for SiP,” Proc. 52nd ECTC, May 29-31, 2002, San Diego, pp. 1329-1334.









SiP Implementation

SiP applications and examplesPortable products – Cell phone, digital camera, …Baseband processor, application processor, flash

Include passives on SiP, instead of on the motherboard (improved signal integrity)

SiP benefits


SiP with WB & Passive


SiP with WB & CSP & Passive


SiP with FC & CSP & Passive


Embedded Passives in Substrate

Source: A. Okubora, et. al., “A Novel Integrated Passive Substrate Fabricated Directly on An Organic Laminate for RF Applications,” Proc. 52nd ECTC, May 29-31, 2002, San Diego, pp. 672-675.


SiP Benefits

Small form factor (lower PWB cost) Light weight for portable products Less aggressive I/O pitch than that with COB (lower PWB

cost) Improved performance (reduced interconnect length) Mixed IC technologies Faster time-to-market Ease product upgrade









Substrate Technologies

Multi-layer FR-4 laminate Add buildup layers

Photo via (photo-sensitive dielectric needed)Laser via (general dielectric materials)

Reduce coefficient of thermal expansion (CTE)Copper-invar-copper (CIC) to replace copper V/G

reference planesGlass ceramic

Low dielectric constant / loss materialsReduce capacitive loadingReduce dielectric loss for serial data communications


Laser Microvia on Buildup Layer

Source: Y. Tsukada, et.al. “Features of New Laser Microvia Organic Substrate for Semiconductor Packaging,” SEMICON Singapore, May 2002


Two Laser Via Technologies


Substrate with Teflon on CIC


Laser Drilling through Reference Plane

Source: D. J. Alcoe, et. al., “A High Performance, Low Stress Laminate Ball Grid Array Flip Chip Carrier,” SEMICON West, July 2001.


ALIVH Structure & Technologies

Source: D. Andoh, et. al., “The Progress of ALIVH Substrate,” Proc. 52nd ECTC, May 29-31, 2002, San Diego, pp. 1419-1424.









Electrical Design

Power/ground distributionMultiple voltages on one plane

Signal lines (To be considered a transmission line?)Controlled impedance

Function (Line width, dielectric thickness, dielectric constant)

Signal crosstalkFunction (edge-to-edge spacing, dielectric thickness)NoiseMagnitude of received signal depending on data pattern (noise

immunity)Propagation time depending on data patterns (timing skew)

Migrate to “differential pair”


When is 10 mm wiring a transmission line (TL)?

Time-of-flight (TOF) 3.33 (ps/mm) x sqrt(4.0) x 10 mm = 66.7 ps 4 TOF = 0.267 ns

A 10 mm signal wiring is to be treated as a TL when the signal rise time is less than 0.267 ns, or f (GHz) 0.35 / 0.267 = 1.31 GHz

Important parameters: Characteristic impedance (Zo) Propagation time constant Or line capacitance & inductance


Effect of a transmission line (TL)

To get a 1.0 volt signal across a 50-ohm TL, 20 mA of current is required.

When the signal line width in the PWB reduces, it may become a 60-ohm TL. At this discontinuity, the voltage becomes 1.091 volts, and the current becomes 18.2 mA.

Excessive changes in voltage and current along a signal line may increase circuit delay time, reduces noise margin, or even impact circuit functionality.

This is a burden to circuit and system designers


Zo of a Transmission Line

Zo = (377/R)/[(WEFF/H1)+(WEFF/H2)+2.62(WEFF/H1)1/4]

WEFF (W + T) / 1.5, when 0.3 T / W 0.6Source: C.S. Chang, “Electrical Design Methodologies,” in Electronic Materials Handbook,

Volume 1 Packaging, ASM International, 1989, pp. 25-44.

H2

T

H1

W

Weff H1 H2 Er Zo

127 52 130 4 28.16100 98 144 3 50.06100 127 195 4 50.02


Zo Dependence on Design Parameters

Zo is inversely proportional to sqrt (R)

Zo increases when H1 increases Zo decreases when W and/or T increases Zo has weak dependence on H2, where H2 > H1 In typical PWB, any change in W would change Zo. This

discontinuity in Zo would cause signal reflection (noise)

H2

T

H1

W


Design Consideration for Parallel TLs To reduce cross-talk noise, a second reference

plane is very beneficial. Reduce signal line width to maintain the same Zo. Low cross-talk noise also reduces the effect of data

patterns (in data bus and address bus) on: Noise margin of receiver circuits Effective signal propagation time

H2

T

H1

W S W

positive negative


Two Parallel Transmission Lines

One line active Adjacent line picks up noise

Both lines active Common mode: both switching

the same polarity Difference mode: switching on

opposite polarities

The propagation constant of common and difference modes are: C = C + jC = [(Z11 + Z12)(Y11 + Y12)]

0.5 (1) D = D + jD = [(Z11 - Z12)(Y11 - Y12)]

0.5 (2) For a lossless coupled lines, we have C = D = 0, and

C = [(L11 + L12)(C11 + C12)]0.5 (3)

D = [(L11 - L12)(C11 - C12)]0.5 (4)

Source: S. Kim, C. S. Chang, and D. P. Neikirk, “Impact of Cross-over lines on Delay Time of Two Parallel Global Wires,” IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging, 10/25-10/27/1999, San Diego, CA, pp. 53-56.


Low Voltage Differential Pair

Point-to-point wiring net with far-end terminationEliminate reflected signal (multiple bits sent before the

first bit arrive at far-end) Two signal lines for each signal port

Eliminate common mode noise (Simultaneous switching noise)

Drastically reduce signal cross-talk between adjacent pairs(Minimize delay time dependence on data patterns in the bus)

Receiver circuit needs very small voltage swingReduce power consumptionTolerate signal attenuation, less concern with skin-

effect and dielectric losses (Accommodate longer line or higher frequency)


Differential Pair Transmission Lines

Two signal lines for each signal (2X wiring requirements, but reduce voltage/ground I/O#)

Immune to noise on reference planes (Tolerate a reference plane split into multiple voltages)

Low cross-talk noise from adjacent signal pairs. Spacing within a signal pair needs tight control.

H2

T

H1

W S W

positive negative


Differential Pair Transmission Lines

Low voltage swing & low power consumption Differential receiver circuit can correctly sense an input signal

even when it is attenuated to 10% or less (Single-ended receiver circuit allows attenuation at about 70%.)

Tolerate higher attenuation Longer distance between input & output Higher frequency

Skin effect loss proportional to square root of frequency (smooth copper surface beneficial)

Dielectric loss proportional to frequency (low loss material desirable)

Often used for broadband data communications


Orthogonal Fan-out Wiring in PBGA









Thermomechanical Design

Total power of all dice in a stack converted to power per unit area

Low CTE(eff) of the stacked-die causes thermomechanical stress on substrate

Not a problem for a small dieUse low modulus die adhesive, spacer and

encapsulantUse low CTE substrate


Thermomechanical Stress

Source: Y. Li, “Accurate Predictions of Flip Chip BGA Warpage,” Proc. 53rd ECTC, May 28-30, 2003, New Orleans, pp. 549-553.


Failure Associated with Stress - 1


Failure Associated with Stress - 2

Source: Y. Naka, et. al., “Highly Reliable and Low-Cost Multi-Chip Module Composed of Wafer Process Packages,” Proc. 53rd ECTC, May 28-30, 2003, New Orleans, pp. 881-885.


Failure after Temperature Cycling

Source: T. Sugiyama, et. al., “Board Level Reliability of Three-Dimensional System in Package (SIPs),” Proc. 53rd ECTC, May 28-30, 2003, New Orleans, pp. 1106-1111.









Bare Substrate Testing

Identify in-process failure mechanisms for process development

Locate failure sites for in-process repairs Assure good products for customer shipping Final test may be made in whole panel or as an

individual substrateTest equipment capital costTime to feed an individual substrate or time to load the

panel and to step-and-repeat between substratesTest time per substrate x # substrates / panelChallenges: Fine pitch WB fingers & FC pads


Testing Methods

Automatic optical inspection (AOI) Bed-of-nails electrical tests for short (between

adjacent lines) & open (continuity failure)

Fine-pitch probe head for high-density WB fingers & FC pads (die I/Os)

ChallengesOpen between die I/O and substrate I/OShort & open between die sites on SiP


Assembled Substrate Testing

Assure all WB fingers or FC pads on substrate are connected to IC I/O pads at assembly

Functional testTo locate failure sites/components for repair, requiring

design-for-testTo assure good assembled substrates for customer

shipping

Build-in self test (BIST) strongly recommendedCo-design efforts from IC design to final product







General design issuesWirebond designsFlip-chip designsCAD Tools


PWB Design: Objectives / Approach

What’s different about PWB design using die products Summary of design issues Wirebond footprint creation Flip-chip escape routing CAD Tools

Focus on general issues and techniques rather than specific solutions:

Very broad spectrum of die, substrate technologies, product requirements, organizational environments

Not providing specific substrate and assembly design rules:Wide spectrum of design rules ranging from conventional to advancedMoving target, steadily shrinkingCompany confidential


PWB Design: Outline Overview: What’s different about PWB design for die products

Interface with Product Design Design for Assembly Routing CAD tools

Wirebond designs Design rules Footprint design SiP examples Relationship between wire length and finger pitch CAD Tools

Flip chip designs Design issues Flip-chip pad design rules Substrate design rules Examples Electrical requirements


Interface with Product Design Product design responsibilities

Requirements definition Reliability, sizing, cost (module, system), electrical, thermal, EMI,

manufacturability, serviceability, … Packaging approach

Bill of Materials (BoM) and netlist Die, substrate, discretes, connectors

Assembly and test plan PWB design responsibilities

Creation of PWB artwork and support files, documentation Assumes BoM, netlist, electrical requirements, design rules

Overlap Use of die products involve more intensive co-design

Routing studies Netlist modifications

When converting from design using packaged die Substrate sizing and selection

Modeling and simulation


Netlist Modifications Netlist translation from packaged parts to die

Not a 1:1 correspondence between package pins and die padsUnused (N/C) signal pads may require connection to P,GBonding options (wirebond designs)

Speed grade, supply voltage, debug/test support

Requirements for resistors, capacitors May be able to shrink package and reduce cost by eliminating

unnecessary components Design for test

Test strategy may require addition of test points May impact pad design

Multiple netlists Substrate only (for bare substrate test) Substrate + die


Design for Assembly: Design Process Establish assembly design rules

Assume substrate technology, design rules already established May have major schedule impact! Need to establish assembly partner and process

Design rules are process and equipment-dependent May need to create rules compatible with multiple assemblers

Embed design rules into CAD tool Constraints, padstacks Correct by design Assembly requirements are usually not fully captured by well-defined

rules Establish review process; contact person

Design reviews Obtain footprint approval from assembly partner

Manufacturing files, diagrams for assembly Wirebond diagrams


Design for Assembly (cont)

Wirebond Bond finger design rules Footprint creation

Flip-chip Pad design rules

Component placement Minimum spacings:

Die-to-dieDie-to-substrate edgeDie-to-component

Issues:Flip-chip underfill; glob-top or molding process; handling; ..


Routing

Flip-chip escape routing Qualitatively different from BGA escape routing

Finer pitch requires more demanding lines/spaces/viasFlip chip footprints and escape patterns vary widely

Electrical requirements may have major impact on strategy For new die type, escape strategy may require multiple

iterations, false starts Wirebond escape routing

Accommodated by wirebond footprint, not addressed here Component-to-component (global) routing

SiP: may require denser PWB design rules Not addressed in this tutorial

Not unlike board design using packaged parts


CAD Tools and Techniques

Ability to embed assembly design rules into padstacks, constraint areas, …

Wirebond support Creation and editing of bond fingers Stacked die Wirebond DRC

Routing tools to support dense substrate technologies

Die data input *.LIQ and *.DIE files; *.gds files

Documentation Assembly diagrams Manufacturing files …







(Selected) Wirebond Design Rules Bond finger dimensions, layer-to-layer rules

Bond finger length and width Minimum spacing bond finger shape

Chamfered or rounded corners Soldermask clearances Pad-trace minimum distance

Bond finger location Fanout pattern Minimum distance from die (die attach) Maximum wire length (wire sweep, wire droop) Spacing between rows (wire droop)

Wire rules Maximum angle (wire pitch at die corners) Wire-to-wire spacings (three-dimensions) Length-matching


Bond Finger Design Rule Examples


Wirebond Fanout Pattern Examples

Ref:CAD Design Software:Hybrid/MCM Designer Suite


Wirebond Pad Footprint Design

Hard to have a “standard” footprint for a die Biggest difference in PWB design for bare die vs packaged die Depends on substrate and assembly design rules

Common to modify footprint for bonding variations: Design to support more than one version of die

Multiple suppliers Planned die revisions, shrinks May require use dummy pads

Bonding options Core logic and/or bus speed Supply voltage Test/debug Circuit changes

Need to edit footprint during placement/routing for system-in-a-package May modify pad locations to support denser placement CAD tool needs to support bond finger pad editing after creation

See examples below







Wirebond MCM Examples

MMS: Spectrum MCMTechnology used for multiple commercial products

MMS: Interleaved DRAM Module SiPDARPA program


MMS “Spectrum” MCM

CPU

TAG RAM

BurstRAM

Cache ControllerChip Set

TempSensor

DRAM

PCI to ISA/EIDEInterface

PCI to PCIBridge

GraphicsPower

Management

ControlAddress

Data

Control Data

PCI BUS

CPU BUS

SPECTRUM MODULE

Ref: 1999 International Conference on High Density Packaging and

MCMs (Denver, Colorado)

Thin Film Substrate4 copper thin-film layers18/14 micron lines/spaces

PWB “donut” boardSurface mounted connectors, caps


SiP Example (MMS “Spectrum” MCM)

Adjust bond fingers locations

for dense placement

Bonding options

Supports SRAM from 2 suppliers

Supports die shrinks


X-LAM Interleaved DRAM Module16245XCVR

16245XCVR

16373LATCH

1MX16DRAM

1MX16DRAMAddress to

DRAM [10]

Data to and from DRAM [32]

VDDODD

16573LATCH

Latched Address Bus [8]

Address Bus [10]

MEMORYBGA

[32]

Read/Write, Even/Odd

Control [18]

Data Bus [32]

[16]

[16]

[16]

[16]

[10]

[10]

16245XCVR

16245XCVR

16373LATCH

1MX16DRAM

1MX16DRAMAddress to

DRAM [10]

Data to and from DRAM [32]

VDDEVEN

[32]

[16]

[16]

[16]

[16]

[10]

[10]

[10]

[10]

[8]

Ref: 1999 International Conference on High Density Packaging and MCMs (Denver, Colorado)

27 mm BGA, 1.27 mm pitch

FilledPTH

Thin Film Build Up Layers:

Passivation Dielectric

Top Metal

Via 3 Dielectric

Metal 2

Via 2 Dielectric Metal 1

Via 1 Dielectric

Core Laminate Layers:

Core M1

Core Dielectric 1

Core M2

Core Dielectric 2

Core M3

Core Dielectric 3

Core M4

Core Solder Mask

Resistor network die (x5)

Finger-die distance

Finger-edgedistance

Adjust finger locations







Impact of Bond Finger Pitch

“Effective” finger pitch May use multiple rows of bond fingers; power/ground rings Not as much flexibility as single chip package, which may

employ multiple tiers of bond fingers on different layers

Minimum wire length See below

Wirebond footprint chart

Maximum number of die #IO Chart


Wirebond example: 2 routing layersDie: 86 micron pad pitchSubstrate: 3 mil lines/spaces; 12 mil via pad

5 mil finger width; 5 mil effective finger pitch (2 layers)3 mm wire length


Issues Related to Long Bond Wires:

Manufacturability Need to keep wirelength < 5 mm long to prevent excessive

sag and “sweep”Dependent on wire diameter

Electrical performance Self and mutual inductance proportional to wire length Cross talk; noise on power supply

Footprint on board Impacts board and product size

Short wires enabled by high-density substrates!


Example High-Density Wirebond Footprint

50 um die pad pitch125 um substrate finger pitch

360 wirebonds, 200 mils5.1 mm die


Impact of Wire Length on Footprint

Wirebond Footprint

100%

300%

500%

700%

900%

1100%

1300%

4 5 6 7 8 9 10

die size (mm)

foo

tpri

nt

area

/die

are

a

2 mm

3 mm

4 mm

5 mm

wirelength


Effective Finger Pitch Required

Finger Pitch vs Wire Lengthfor 60 micron average die pad pitch

60

70

80

90

100

110

120

130

140

150

160

2 3 4 5

Wire length (mm)

Fin

ger

Pit

ch (

mic

ron

s)

5 mm

6 mm

7 mm

8 mm

9 mm

Die Size


Maximum #IO vs. Finger Pitch

maximum #IO vs substrate finger pitchfor 200 mil bond length

0

200

400

600

800

1000

1200

55 75 95 115 135 155 175

"effective" finger pitch on substrate

max

imu

m #

IO

60 um

50 um

70 um

15.2 mm13.1 mm

effective pad pitch

17.4 mmdie size:

5.2 mm

4.2 mm

3.4 mm

die size:


Example High-Density Wirebond Footprint

10 mm die, 864 pads, 3 mm wire length35 m minimum die pad pitch (43 m average pitch)

57 m finger pitch







CAD Tool Features Footprint creation

Patterns, orientations, shapes, power/ground rings Ability to edit bond fingers Support for multiple die sourcing

Stacked Die Basic support Constrain allowable wire-crossings Check wire clearances in three dimensions

Tolerance analysis 3D DRC

Pad sharing Manufacturing files

Ability to read industry standard files (*.LIQ and *.DIE) Wirebond diagrams Code to drive equipment

Bonders, … Support build-up technology

Stair-stepped vias


Wirebond Pad Creation in APD

Courtesy, Cadence Design Systems


Wirebond Pad Creation in Excel


Stacked Die

CAD tool supportSupport die data in multiple levelsMore complex footprint creationShared bondpadsDie-to-die connectionsCalculate clearances of bond wires based on bond

wire profiles and die placement tolerances. Examples

Cadence APDCAD Design Software


Stacked Die Examples

Advanced Packaging August, 2003Author(s) : Joel McGrath

Photo courtesy of ChipPAC Inc.


Cadence APD SiP Example


Stacked Die - CDS

Ref:CAD Design SoftwareStacked Die Manufacturing Designer Suite





Flip chip designs Design parameters Flip-chip pad design rules Substrate design rules Examples Electrical requirements


Flip Chip Design Parameters Die footprint

Pad pitch: 500 um (uBGA), 225, 200, 175, 150 ITRS Roadmap

Power and Ground: # supplies, pad placement Interferes with signal escape routing

Signal distribution: perimeter, full area array Overall Pattern: regular, irregular

Electrical requirements Stripline, microstrip Differential pairs Special high-speed lines Power requirements: current, dc drop, capacitor placements

Substrate Technology Design rules: line, space, via pad Offset vs stacked vias Stackup, number of layers


Flip Chip Pad Types

Non-Soldermask-Defined(NSMD)

(Metal-Defined)

Soldermask-Defined(SMD)

Via-in-Pad

•Pad diameter•Soldermask opening diameter•Trace width•Pad-trace minimum space







ITRS Roadmap: Flip-Chip Escape Requirements

YEAR OF PRODUCTION 2001 2002 2003 2004 2005 2006 2007 2010 2013 2016DRAM ½ PITCH (nm) 130 115 100 90 80 70 65 45 32 22MPU / ASIC ½ PITCH (nm) 150 130 107 90 80 70 65 50 35 25MPU PRINTED GATE LENGTH (nm) 90 75 65 53 45 40 35 25 18 13MPU PHYSICAL GATE LENGTH (nm) 65 53 45 37 32 28 25 18 13 9Flip Chip Pad Pitch (µm) 160 160 150 150 130 130 120 90 80 70Pad Size (µm)* 80 80 75 75 65 65 60 45 40 35

Cost-Performance 12 12 12 12 12 12 12 12 12 12 High-Performance 17 17 17 17 17 17 17 17 17 17

Cost-Performance (max) 74 74 79 79 91 91 91 132 149 170 High-Performance (max) 105 105 112 112 129 129 140 187 211 241

Line Width (µm) 34.2 34.2 32.1 32.1 27.8 27.8 25.7 19.2 17.1 15 Line Spacing (µm) 34.3 34.3 32.1 32.1 27.9 27.9 25.7 19.3 17.1 15

Line Width (µm) 21.8 21.8 20.4 20.4 17.7 17.7 16.3 12.2 10.9 9.5 Line Spacing (µm) 21.8 21.8 20.5 20.5 17.7 17.7 16.4 12.3 10.9 9.5

Line Width (µm) 11.4 11.4 10.7 10.7 9.2 9.2 8.5 6.4 5.7 5 Line Spacing (µm) 11.4 11.4 10.7 10.7 9.3 9.3 8.6 6.4 5.7 5* The pad size is assumed as 50% of pad pitch. It is usually different at different fan-out layers, e.g. from 30% to 60%

Table 81 Flip Chip Substrate Top-side Fan-out Potential Solutions

(from roadmap)

Chip Size (mm/size)

Array Size = # pads along chip edge

Wiring Substrate (Three lines replacing one depopulated pad-accessing 2.0 rows per fan-out layer)

Wiring Substrate (Five lines replacing one depopulated pad-accessing 3.0 rows per fan-out layer)

Wiring Substrate (Three lines between adjacent pads-accessing 4.0 rows per fan-out layer)


Design Rules vs. Escape DepthThree lines replacing one depopulated pad-accessing 2.0 rows per fan-out layer

w,s = (2*PP-PS)/7

Five lines replacing one depopulated pad-accessing 3.0 rows per fan-out layer

w,s = (2*PP-PS)/11

Three lines between adjacent pads-accessing 4.0 rows per fan-out layer

w,s = (PP-PS)/7

PP

PSs

w

s

PS refers to pad diameter (top layer) or via land diameter (inner layers) Depopulated pads on top layer may be designed into die footprint; on inner

layers, via pads are depopulated when flip chip pads terminate on higher layer Top layer: may also be limited by soldermask opening


Flip-Chip Escape Requirements

Flip Chip Pad Pitch (µm) 500 225 200 180Pad Size (µm)* 250 112.5 100 90

Line Width (µm) 107 48 43 39 Line Spacing (µm) 107 48 43 39

Line Width (µm) 68 31 27 25 Line Spacing (µm) 68 31 27 25

Line Width (µm) 36 16 14 13 Line Spacing (µm) 36 16 14 13* The pad size is assumed as 50% of pad pitch. It is usually different at different fan-out layers, e.g. from 30% to 60%

Table 81 Flip Chip Substrate Top-side Fan-out Potential Solutions(other examples)

Wiring Substrate (Three lines replacing one depopulated pad-accessing 2.0 rows per fan-out layer) w,s = (2*PP-PS)/7

Wiring Substrate (Five lines replacing one depopulated pad-accessing 3.0 rows per fan-out layer) w,s = (2*PP-PS)/11

Wiring Substrate (Three lines between adjacent pads-accessing 4.0 rows per fan-out layer) w,s = (PP-PS)/7


Layer-to-Layer Connections

Vertical connections Analysis above does not consider blockage caused by having

to route P/G/signal connections to lower layers P/G/signal footprint on die Layer assignment, escape strategy

Issues More than 1 power and 1 ground net in same region Stacked vs staggered vias

Stagger distance and orientation: parallel, 45°, orthogonal

Impact Tighter design rules; extra layers (vs ITRS estimates) Design difficulty and design time Electrical effectiveness of reference planes


Substrate Examples

Several suppliers capable of providing high-density substrates with lines/spaces in the range of 20 µm to 40 µm; eg:

IBM YasuSLC

Matsushita ALIVH-BAny layer IVH for bare-chipStacked vias, via-in-pad

Ibiden (LLBS) (Laser Laminate Buildup System)LLBS Technology Rev03.ppt20-25 um l/s, 90-120 um pad, stacked vias, via-in-pad

Examples using X-LAM Typical array configurations Illustrate vertical connections


IBM Yasu

Ref: SEMI-Singapore 2002


Ibiden LLBS


ALIVH-B

(Jan 2001)


XLAM Cross-section

Core

Thin Film

pad

6 passivation3.7 M3 (power)

16 eps=3.3 via3

7.5 M2

16 via2

9 M1 (ground)

25 via1

20 microns CORE1 (power)

UltraVia12SL Stripline







Examples

Example 1Regular pattern, perimeter IO, spatially separated

supplies

Example 2 Irregular pattern, perimeter IO, overlapping supplies

Example 3Area array







Electrical Requirements

Line type: stripline, microstrip Stripline offers better impedance control, but connections to lines

(from pads or other signal layers) must pass through openings in reference planes

Differential pairs Requires routing signal pairs at controlled spacing

Power requirements: current, dc drop, capacitor placements

Affects number of planes, number of vias from power pins to planes May drive escape strategy for dense designs with conflicting

demands on routing resources Critical high speed lines

Need to ensure they do not cross openings in reference planes See below


UV12SL Nearest Neighbor Crosstalk

UV12SL CrosstalkSolid M1

0%

1%

2%

3%

4%

5%

6%

7%

8%

9%

10%

11%

12%

13%

14%

0 100 200 300 400 500 600

Time(ps)

CO

UP

LIN

G(%

)

10% PULSE Solid-36um Solid-28um

Solid-20um Solid-12um

UV12SL Crosstalk"Holey" M1

0%

1%

2%

3%

4%

5%

6%

7%

8%

9%

10%

11%

12%

13%

14%

0 100 200 300 400 500 600

Time(ps)

CO

UP

LIN

G(%

)10% PULSE Holey-36um Holey-28um

Holey-20um Holey-12um


Summary/Closing

We welcome your comments/feedback Larry Smith

[email protected]: (512) 923-3964

Chi-Shih [email protected] (512) 418-8318

Date post:	15-Dec-2015
Category:	Documents
Upload:	carlos-bailor
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KGD Packaging and Test Workshop KGD Packaging and Test Workshop, Napa, CA, September 8, 2003...

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