Kinetis K70 SOM Hardwarre Architecture - Emcraft · Emcraft Systems Kinetis K70 SOM...

Kinetis K70 SOM (System-On-Module) Hardware Architecture

Version 1.04

Emcraft Systems

Kinetis K70 SOM (System-On-Module) 2/23 Version 1.04 Hardware Architecture

Table of Contents

1. Introduction ............................................................................................... 3

2. Hardware Platform .................................................................................... 3 2.1. HARDWARE PLATFORM OVERVIEW......................................................................................................3 2.2. FUNCTIONAL BLOCK DIAGRAM ............................................................................................................4 2.3. MICROCONTROLLER...........................................................................................................................4

2.3.1. Microcontroller Device.............................................................................................................................. 4 2.3.2. Microcontroller Configuration ................................................................................................................... 4

2.4. JTAG INTERFACE..............................................................................................................................4 2.5. POWER ............................................................................................................................................5

2.5.1. Power Source........................................................................................................................................... 5 2.5.2. Power Conversion and Configuration ...................................................................................................... 5 2.5.3. Power Supervising and Fault Recovery................................................................................................... 5 2.5.4. Power Modes ........................................................................................................................................... 5

2.6. SYSTEM RESET.................................................................................................................................6 2.6.1. Reset Architecture Overview ................................................................................................................... 6 2.6.2. Types of System Resets .......................................................................................................................... 6

2.7. SYSTEM CLOCKS...............................................................................................................................6 2.8. SDRAM...........................................................................................................................................7

2.8.1. SDRAM Architecture ................................................................................................................................ 7 2.8.2. SDRAM Operational Mode ...................................................................................................................... 7 2.8.3. SDRAM Low-Power Modes ..................................................................................................................... 7

2.9. NAND FLASH ...................................................................................................................................7 2.9.1. NAND Flash Architecture ......................................................................................................................... 7 2.9.2. NAND Flash Low-Power Mode ................................................................................................................ 7

2.10. SERIAL .............................................................................................................................................7 2.10.1. UART Controller....................................................................................................................................... 7 2.10.2. Serial Baud Rate ...................................................................................................................................... 7

2.11. ETHERNET ........................................................................................................................................7 2.11.1. Ethernet Controller ................................................................................................................................... 7 2.11.2. Ethernet Physical Layer ........................................................................................................................... 8 2.11.3. Ethernet Clock.......................................................................................................................................... 8 2.11.4. Ethernet Status LEDs............................................................................................................................... 8 2.11.5. Ethernet Low Power Mode....................................................................................................................... 8

2.12. WDT ...............................................................................................................................................8 2.13. RTC ................................................................................................................................................8 2.14. EXTERNAL INTERFACE........................................................................................................................9

2.14.1. Interface Connectors................................................................................................................................ 9 2.15. CONNECTORS PIN-OUT......................................................................................................................9

2.15.1. Unavailable Signals of Kinetis K70 MCU ............................................................................................... 22 3. Mechanical Specifications...................................................................... 22

3.1. K70 SOM MECHANICALS.................................................................................................................22 3.2. K70 SOM CONNECTOR MECHANICALS .............................................................................................23

4. Environment Specifications................................................................... 23 4.1. RECOMMENDED OPERATING CONDITIONS ..........................................................................................23

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1. Introduction

This document describes the hardware architecture of the Emcraft Systems K70 SOM (System-On-Module).

The K70 SOM is intended to provide a flexible platform for embedded applications that require rich connectivity, low power and flexibility of the Kinetis K70 MCU device coupled with a full-fledged Linux software execution environment running on the ARM Kinetis K70 processor core.

The K70 SOM is based on the Freescale Kinetis K70 MCU versatile, low-power, high-integration microcontroller. The uClinux kernel and applications execute on the 120/150 MHz 32-bit ARM Cortex-M4 processor core, while the integrated controllers of the Kinetis K70 MCU are used to implement various communication interfaces.

Using a miniature mezzanine form factor, the K70 SOM is specifically designed to provide the primary Kinetis K70 MCU-based intelligence on various boards targeting industrial automation, system and power management, wireless networking / sensors and other embedded applications. K70 SOM hardware and software are architected to ensure flexibility in customizing its functionality for the needs of particular products and/or customers.

2. Hardware Platform

This section defines the hardware platform of the K70 SOM.

2.1. Hardware Platform Overview

The following are the key hardware features of the K70 SOM:

• Compact mezzanine module;

• External interface using two 80-pin 0.4 mm-pitch connectors;

• Mounting hole reducing the risk of connector-to-PCB intermittence;

• Compliant with the Restriction of Hazardous Substances (RoHS) directive;

• Kinetis K70 MCU capable of running the system clock at up to 150 MHz;

• JTAG interface to Kinetis K70 MCU;

• Powered from single +3.3 V power supply;

• Low-power mode with fast wake-up times;

• On-module clocks;

• 64 MBytes LPDDR SDRAM;

• 132 MBytes NAND Flash;

• Serial console interface at UART CMOS levels;

• 802.3 Ethernet interface;

• Watchdog Timer (WDT);

• Real-Time Clock (RTC);

• All otherwise uncommitted interfaces of the Kinetis K70 MCU available on the interface connectors.

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2.2. Functional Block Diagram

The following figure is a functional block diagram of the K70 SOM:

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Figure 1: K70 SOM Functional Block Diagram

2.3. Microcontroller

2.3.1. Microcontroller Device

The architecture of the K70 SOM is built around the Freescale Kinetis K70 microcontroller that combines a 32-bit ARM Cortex-M4 processor core with a wide range of the integrated peripheral controllers

The Kinetis K70 MCU is implemented using the MAPBGA 256 package.

2.3.2. Microcontroller Configuration

The K70 SOM supports build-time selection of the following Kinetis K70 devices:

• Speed Grade:

- MK70FN1M0VMJ15 (150 MHz);

- MK70FN1M0VMJ12 (120 MHz).

Selection of any of the options above in an actual assembled unit does not affect the other sections of the hardware architecture. For those configuration options that affect software functionality, software running on the K70 SOM is expected to determine the specific microprocessor configuration at run-time and adjust its operation accordingly.

2.4. JTAG Interface

The K70 SOM provides a standard JTAG interface on the interface connectors. This interface is routed to the corresponding signals of the Kinetis K70 MCU.

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2.5. Power

2.5.1. Power Source

The K70 SOM is run from a single +3.3 V power source provided through multiple pins on the interface connectors.

2.5.2. Power Conversion and Configuration

The K70 SOM provides two options for converting the +3.3 V input power to a +1.8 V power source required by the K70 SOM circuitry, as described below. Choice of one of the two power conversion configuration options is made by a baseboard designer using a dedicated input (1.8V_EN) provided on the interface connectors.

• Cost-optimized mode. This mode makes use of an on-module LDO regulator to convert the +3.3 V power to a +1.8 V source. This option provides the lowest-cost and easy-to-implement solution but it is less efficient in terms of the power consumption characteristics of the K70 SOM.

To enable the cost-optimized mode, a baseboard must drive 1.8V_EN high or leave it floating, thus enabling the on-module +1.8 V LDO regulator. When this configuration is enabled, no additional power conversion is required on a baseboard.

• Power-optimized mode. This mode makes use of an external (off-module) switching regulator (DC/DC) converter to implement an external +1.8 V power source for the K70 SOM. This option results in a solution that reduces the power consumption of the K70 SOM by about TBD mA at the cost of using more expensive external components.

To enable the power-optimized mode, a baseboard must drive 1.8V_EN low, thus disabling the on-module +1.8 V LDO regulator. In this mode, a baseboard is responsible for providing power conversion optimized for power consumption. Specifically, the following circuitry is recommended on a baseboard in this mode: TBD - provide a snapshot of recommended baseboard schematics as well as a brief description of what this circuitry does exactly.

2.5.3. Power Supervising and Fault Recovery

The K70 SOM provides power supply fault detection and recovery using the built-in Power Management Controller (PMC) of the Kinetis K70 MCU.

2.5.4. Power Modes

The K70 SOM supports the following power modes:

• Full-power mode. This is the normal mode of operation. The main clock is running and the Cortex-M4 is active running RTOS and/or application code. All memory controllers are enabled.

Software is configured to enable only those Kinetis K70 MCU sub-systems that are used by installed device drivers; the clocks to all other sub-systems are gated off so those modules do not consume power. If the Ethernet interface is not enabled by a corresponding device driver, the Ethernet PHY is in a low power mode (refer to Section 2.11.5). If software is not using the external NAND Flash at a particular time, the NAND Flash device is automatically switched to a low power mode (refer to Section 2.9.2).

• Low-power mode. This is the mode of operation the Linux software may be configured to enter when the K70 SOM is idle from the software perspective. That is, this mode may be entered when Linux has no active processes to run and is running the so-called "idle process". When Linux finds itself in the idle state, it transitions the Kinetis K70 MCU to the Very Low Power Stop Mode, which is designated by the Kinetis K70 MCU architecture for applications that intend to put the device in the low-power state but be ready to respond to an interrupt sourced by peripherals or the RTC. In this mode, the Cortex-M4 is stopped, with all I/O, logic and memory states retained and certain asynchronous mode peripherals operating.

To put external devices into a low-power mode, the K70 SOM provides a dedicated output signal as a control for switching on-module and off-module devices to low-power

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modes. This active-low signal is implemented using a GPIO of the Kinetis K70 MCU and is available as PTC3 on the interface connectors. When switching the system to the low-power mode, software activates the low-power mode signal. Various on-module and off-module devices are expected to react to activation of that signal by switching themselves to low-power modes. Conversely, when software is switching back to full-power mode, it de-asserts the low-power mode signal indicating to on-module and off-module devices that they are expected to switch back to the full-power mode.

2.6. System Reset

2.6.1. Reset Architecture Overview

The K70 SOM implements a reset architecture that ensures that the Kinetis K70 MCU is reset as appropriate on various hardware and software events.

The K70 SOM ensures that the on-board Ethernet PHY device is reset as soon as the Kinetis K70 MCU is subjected to a reset by connecting the external reset signal to the reset input of the PHY.

Those off-module devices that require synchronizing their resets with K70 SOM resets must connect the active-low nRESET_OUT signal to the reset input of a respective device.

2.6.2. Types of System Resets

The following types of reset are implemented by the K70 SOM:

• Power-on reset. This type of reset occurs when power is initially applied to the K70 SOM or when the supply voltage drops below the power-on reset re-arm voltage level (+0.8 V to 1.5 V). As the supply voltage rises, the internal Low-Voltage Detect (LVD) system holds the K70 MCU in reset until the supply has risen above the LVD low threshold (+1.54 V to 1.66 V).

• Brown-out reset. In case the +3.3 V supply falls below a user-selectable trip voltage (+1.54 V to 1.66 V or +2.48 V to 2.64 V) the LVD system generates a reset of the K70 MCU. After the brown-out reset has occurred, the LVD system holds the K70 MCU in reset until the supply has risen above the LVD low threshold (+1.54 V to 1.66 V).

• Software reset. This type of reset is activated by software running on the K70 SOM through performing the K70 MCU software reset sequence.

• WDT reset. This type of reset is activated when the integrated WDT of the K70 MCU expires.

• Manual reset. To activate this type of reset, a baseboard drives low the nRESET_IN signal.

2.7. System Clocks

The K70 SOM provides a 12 MHz quartz crystal as a reference to the internal oscillator of the Kinetis K70 MCU.

The Kinetis K70 MCU contains integrated PLLs driven by the above oscillator from which the various clocks required by the MCU subsystems are derived. More specifically, the Kinetis K70 MCU provides the following clocks for the various MCU domains:

Clock Frequency (MHz)

Purpose

Core clock 150 120 Clocks the Cortex-M4 core

System clock 150 120 Clocks the crossbar switch and bus masters directly connected to the crossbar; also used for UART0 and UART1

Bus clock 75 60 Clocks the bus slaves and peripheral

Flash clock 25 20 Clocks the internal Flash memory

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Clock Frequency (MHz)

Purpose

DDR clock 150 120 Clocks the SDRAM controller

NFC clock 18.75 20 Clocks the NAND Flash Controller

Table 1: System Clocks

In addition to the 12 MHz crystal, the K70 SOM provides a dedicated clock reference for the Ethernet sub-section (refer to Section 2.11.3).

2.8. SDRAM

2.8.1. SDRAM Architecture

The K70 SOM provides 64 MBytes of 5 ns 16-bit LPDDR SDRAM using the Micron MT46H32M16 device. The SDRAM resides at nDDR_CS chip select of the integrated SDRAM controller of the Kinetis K70 MCU.

2.8.2. SDRAM Operational Mode

The Kinetis K70 MCU SDRAM controller operates in the Low-Power Dual Data Rate Mode. The DDR clock frequency of the SDRAM controller is 120 or 150 MHz, depending on the MCU frequency.

2.8.3. SDRAM Low-Power Modes

When not accessed, the SDRAM power consumption is only 0.3 mA.

2.9. NAND Flash

2.9.1. NAND Flash Architecture

The K70 SOM provides 132 MBytes of 70 ns 8-bit NAND Flash memory using the Micron MT29F1G08ABBDAH4 device. The NAND Flash memory resides at nNFC_CE0 chip select of the integrated NAND Flash controller of the Kinetis K70 MCU.

2.9.2. NAND Flash Low-Power Mode

When not accessed, the NAND Flash power consumption is only 1 mA.

2.10. Serial

2.10.1. UART Controller

The K70 SOM provides an UART serial interface at CMOS levels (no RS-232 buffer) using the integrated UART2 controller of the Kinetis K70 MCU on the interface connector.

This interface is intended as the console interface for the U-Boot and Linux software.

2.10.2. Serial Baud Rate

The UART controller features an internal divider that allows this serial interface to operate at standard baud rates up to 4687,5 Kbps.

2.11. Ethernet

2.11.1. Ethernet Controller

The K70 SOM provides a full-featured, configurable Ethernet interface capable of 10/100 Mbps data rates using the integrated 10/100 Mbps Ethernet MAC of the Kinetis K70 MCU.

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2.11.2. Ethernet Physical Layer

The physical layer of the Ethernet port is implemented using the Ethernet PHY device to provide a full-featured, 10/100 Mps 802.3 interface.

2.11.3. Ethernet Clock

The K70 SOM provides a 25 MHz quartz crystal as a clock reference to the KSZ8051RNLI PHY device.

The KSZ8051RNLI PHY device drives a 50 MHz clock input of the integrated Ethernet MAC interface of the Kinetis K70 MCU.

2.11.4. Ethernet Status LEDs

The K70 SOM provides two status signals for the Ethernet channel on the interface connectors for controlling off-module Ethernet LEDs. The functionality of these signals is as follows:

• LED_ACT, used to indicate link status (Link when low, No Link when high) and the RX activity when toggling;

• LED_SPD, used to indicate the 10/100 Mbit link status (100 Mbit when low, 10 Mbit when high).

On a baseboard, the status LEDs should be connected between the K70 SOM output signals and a +3.3 V plane.

2.11.5. Ethernet Low Power Mode

When not accessed, the PHY can be switched to the Power-Down mode under software control. When in the Power-Down mode, the PHY current consumption is only 2 mA, typical.

2.12. WDT

The K70 SOM provides a hardware watchdog function using the integrated WDT module of the Kinetis K70 MCU.

If software fails to refresh the WDT within the predefined period of time, the watchdog resets the system.

The WDT reset event is counted in the WDOG_RSTCNT register of the Kinetis K70 MCU. This register is reset only on a Power-on reset and can be checked by software to determine whether a watchdog reset event has occurred.

The watchdog timeout period is defined by software.

By default, the integrated WDT is clocked from the bus clock. It is possible to switch the WDT clock source to the internal LPO 1 kHz oscillator, which generates reliable timeout detection even if the main clock reference fails.

2.13. RTC

The K70 SOM supports a Real-Time Clock (RTC) functionality using the Kinetis K70 MCU Real-Time Clock.

The RTC module is clocked from the low-power 32.768 KHz oscillator of the Kinetis K70 MCU.

The Kinetis K70 RTC is powered only from the backup power supply (VBAT) via VBAT pin on the interface connectors. That allows the RTC module to function when the +3.3 V power supply has been removed (chip power-down).

During chip power-down, RTC is electrically isolated from the rest of the chip but continues to increment the time counter (if enabled) and retain the state of the RTC registers.

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2.14. External Interface

2.14.1. Interface Connectors

The external interfaces of the K70 SOM are routed through two 80-pin Hirose DF40 series 0.4 mm-pitch board-to-board connectors.

2.15. Connectors Pin-Out

The following table details the allocation of the external interface connectors pins on the P1 connector:

Pin Name Type Description Notes

Power Supply (18 pins)

2, 3, 5, 8, 9, 11, 14, 57, 75, 76

GND Power SOM ground Must be connected to GND on a baseboard.

77, 79 V3V Power +3.3 V power supply

An external +3.3 V+/ - 5% power supply must be applied to these pins.

78, 80 VCC_1V8 Power +1.8 V power supply

An external +1.8 V+/ - 5% power supply can be applied to these pins (in this case the 1V8_EN signal must be connected to GND). If no external power supply is applied to these pins, they should be left unconnected.

72 1V8_EN Input The on-module +1.8 V LDO regulator control signal

Must be left floating or driven high if the on-module LDO regulator is used. To disable the on-module LDO regulator, this signal must be connected to GND.

74 VBAT Power Kinetis K70 MCU backup power

An external backup power supply of +1.71 V to +3.6 V can be applied to this pin.

13 nRESET_IN Input/Output SOM reset input Active-low SOM hardware reset. Connected to the nRESET_OUT pin 15 on the K70 SOM. Driven low during internal K70 resets.

15 nRESET_OUT Input/Output Reset output Active-low reset from the SOM to external devices. Connected to the nRESET_IN pin 13 on the K70 SOM.

JTAG (4 pins)

20 JTAG_TCK Input JTAG clock signal to the Kinetis K70 MCU

24 JTAG_TMS Input JTAG mode select

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38 JTAG_TDO Output JTAG data output from the Kinetis K70 MCU

47 JTAG_TDI Input JTAG data input to the Kinetis K70 MCU

Analog signals (9 pins)

40 DAC0_OUT Output Kinetis K70 MCU DAC0 output

42 DAC1_OUT Output Kinetis K70 MCU DAC1 output

49 ADC1_DP0 Input Kinetis K70 ADC channel differential input


51 ADC1_DM0 Input Kinetis K70 ADC channel differential input




70 ADC1_SE16 Input Kinetis K70 ADC channel input

Ethernet (6 pins)

1 LED_ACT Output Ethernet Link/Activity status

Low – Link, High – No Link, Toggling – RX activity.

4 TD_P Output Ethernet differential positive transmit signal

6 TD_N Output Ethernet differential negative transmit signal

TD_N and TD_P signals should be routed on a baseboard with a 100 Ohm differential impedance.

7 LED_SPD Output Ethernet 10/100 Mbit link status

Low – 100 Mbit, High – 10 Mbit.

10 RD_P Input Ethernet differential positive receive signal

RD_N and RD_P signals should be routed on a baseboard with a 100 Ohm

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12 RD_N Input Ethernet differential negative receive signal

differential impedance.

Multifunctional pins (40 pins)

16 PTC3 Input/Output Kinetis K70 GPIO/ UART1 receive data input/ SPI0 chip select input/output

17 PTA4 Input/Output Kinetis K70 GPIO/ non-maskable interrupt/ EzPort chip select input/ touch sense input/output/ timer input

18 PTC4 Input/Output Kinetis K70 GPIO/ UART1 transmit data output/ SPI0 chip select input/output

19 PTB18 Input/Output Kinetis K70 GPIO/ touch sense input/output/ CAN0 transmit output/ timer input/ I2S0 transmit bit clock input/output

21 PTB19 Input/Output Kinetis K70 GPIO/ touch sense input/output/ CAN0 receive input/ timer input/ I2S0 transmit frame sync input/output

23 PTA19 Input/Output Kinetis K70 GPIO/ oscillator output/ timer input

25 PTB2 Input/Output Kinetis K70 ADC channel input/ I2C0 serial clock input/output/UART0 request to send output/ GPIO

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26 PTB3 Input/Output Kinetis K70 ADC channel input/ I2C0 serial data input/output/UART0 clear to send input/ GPIO

27 PTE18 Input/Output Kinetis K70 ADC channel input/ I2C0 serial data input/output/UART2 clear to send input/ SPI0 serial data output/ GPIO

28 PTC15 Input/Output Kinetis K70 UART4 transmit data output/ GPIO

29 PTE16 Input/Output Kinetis K70 ADC channel input/ UART2 transmit data output/ SPI0 chip select input/output/ GPIO

Used for the console interface.

30 PTE17 Input/Output Kinetis K70 ADC channel input/ UART2 receive data input/ SPI0 serial clock input/output/ GPIO

Used for the console interface.

31 PTC14 Input/Output Kinetis K70 UART4 receive data input/ GPIO

32 PTB9 Input/Output Kinetis K70 GPIO/ UART3 clear to send input/ SPI1 chip select input/output

33 PTE19 Input/Output Kinetis K70 ADC channel input/ I2C0 serial clock input/output/UART2 request to send output/ SPI0 serial data input/ GPIO

34 PTD7 Input/Output Kinetis K70 GPIO/ UART0 transmit data output/ timer input

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35 PTB8 Input/Output Kinetis K70 GPIO/ UART3 request to send output

37 PTC12 Input/Output Kinetis K70 GPIO/ UART4 request to send output

39 PTC13 Input/Output Kinetis K70 GPIO/ UART4 clear to send input

41 PTE10 Input/Output Kinetis K70 GPIO/ UART5 clear to send input/ LCD bus data output

43 PTC19 Input/Output Kinetis K70 GPIO/ UART3 clear to send input

44 PTB5 Input/Output Kinetis K70 ADC channel input/ GPIO

45 PTD0 Input/Output Kinetis K70 GPIO/ UART2 request to send output/ SPI0 chip select input/output



54 PTC0 Input/Output Kinetis K70 ADC channel input/ SPI0 chip select input/output/ GPIO

56 PTC1 Input/Output Kinetis K70 ADC channel input/UART1 request to send output/ SPI0 chip select input/output/ GPIO

58 PTC2 Input/Output Kinetis K70 ADC channel input/ UART1 clear to send input/ SPI0 chip select input/output/ GPIO

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59 PTB16 Input/Output Kinetis K70 UART0 receive data input/ SPI1 serial data output/ GPIO

60 PTE26 Input/Output Kinetis K70 ADC channel input/ UART4 clear to send input/ LCD bus data output/ GPIO

61 PTB17 Input/Output Kinetis K70 UART0 transmit data output/ SPI1 serial data input/ GPIO

63 PTB22 Input/Output Kinetis K70 SPI2 serial data output/ GPIO

64 PTE27 Input/Output Kinetis K70 ADC channel input/ UART4 request to send output/ LCD bus data output/ GPIO

65 PTB23 Input/Output Kinetis K70 SPI2 serial data input/ SPI0 chip select input/output/ GPIO

66 PTD6 Input/Output Kinetis K70 ADC channel input/UART0 receive data input/ SPI0 chip select input/output/ GPIO

67 PTB11 Input/Output Kinetis K70 ADC channel input/ UART3 transmit data output/ SPI1 serial clock input/output/ GPIO

68 PTE28 Input/Output Kinetis K70 ADC channel input/ LCD bus data output/ GPIO

69 PTB10 Input/Output Kinetis K70 ADC channel input/ UART3 receive data input/ SPI1 chip select input/output/ GPIO

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71 PTB21 Input/Output Kinetis K70 ADC channel input/ SPI2 serial clock input/output/ GPIO

73 PTB20 Input/Output Kinetis K70 ADC channel input/ SPI2 chip select input/output/ GPIO

Not Connected (3 pins)

22 E_RMII_MDC Input/Output Kinetis K70 ADC channel input/ I2C0 serial clock input/output/ RMII and MII MDIO input/output/ GPIO

36 E_RMII_MDIO Input/Output Kinetis K70 ADC channel input/ I2C0 serial data input/output/ RMII and MII MDC output/ GPIO

62 E_ACD1_DP1 Input/Output Kinetis K70 ADC channel differential input

Connection of these pins to the Kinetis K70 MCU requires installation of the jumper connected to GND for lower EMI.

Table 2: K70 SOM P1 Connector

The following table details the allocation of the external interface connectors pins on the P2 connector:


Power Supply (10 pins)

1, 6, 7, 12, 20, 24, 28, 52

GND Power SOM ground Must be connected to GND on a baseboard.

9 USB_PWR Power Kinetis K70 MCU internal voltage regulator input

VBUS voltage from the USB interface must be applied to this pin.

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80 PTE8 Output Low-power mode control signal

Active-low, enables low-power mode of external devices. If the low-power mode control signal is not needed, this pin can be used as Kinetis K70 GPIO/ ADC channel input / UART5 transmit data output/ LCD bus data output.

Multifunctional pins (TBD pins)

2 RMII_TXD1/TMP0 Input/Output Kinetis K70 tamper input/output/ RTC wake-up output (GPIO/ RMII_TXD1 output)

Option in parentheses requires installation/ removal of a jumper resistor on the K70 SOM.

3 USB0D_P Input/Output Kinetis K70 USB transceiver D+ data signal

4 RMII_TXD0/TMP1 Input/Output Kinetis K70 tamper input/output/ (GPIO/ RMII_TXD0 output)


5 USB0D_N Input/Output Kinetis K70 USB transceiver D- data signal

8 RMII_RXD1/TMP3 Input/Output Kinetis K70 tamper input/output/ (GPIO/ RMII/MII_RXD1 input/ CAN0 transmit output)


10 RMII_RXD0/TMP4 Input/Output Kinetis K70 tamper input/output/ (GPIO/ RMII/MII_RXD0 input/ CAN0 receive input)


11 PTC18 Input/Output Kinetis K70 GPIO/ UART3 request to send output

13 PTB4 Input/Output Kinetis K70 GPIO/ ADC channel input/ LCD bus contrast output

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14 RMII_TXEN/TMP2 Input/Output Kinetis K70 tamper input/output/ (GPIO/ RMII_REF_CLK input/ external clock input)


15 PTF0 Input/Output Kinetis K70 GPIO/ ADC channel input/ CAN0 transmit output/ LCD bus clock output

16 RMII_RXER/TMP5 Input/Output Kinetis K70 tamper input/output/ (GPIO/ RMII_RXER input)


17 PTF1 Input/Output Kinetis K70 GPIO/ ADC channel input/ CAN0 receive input/ LCD bus DE output

18 RMII_CRSDV/TMP6 Input/Output Kinetis K70 tamper input/output/ (GPIO/ RMII_CRS_DV input)


19 PTF2 Input/Output Kinetis K70 GPIO/ ADC channel input/ I2C1 serial clock input/output LCD bus sync output

21 PTF3 Input/Output Kinetis K70 GPIO/ ADC channel input/ I2C1 serial data input/output LCD bus sync output

23 PTF4 Input/Output Kinetis K70 GPIO/ ADC channel input/ LCD bus data output


26 ULPI_CLK/PTA6 Input/Output Kinetis K70 GPIO/ ADC channel input/ ULPI clock input


29 PTF7 Input/Output Kinetis K70 GPIO/ ADC channel input/ UART3 receive data input/ LCD bus data output

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30 ULPI_DATA7/PTA29 Input/Output Kinetis K70 GPIO/ ADC channel input/ ULPI data input/output

31 PTF8 Input/Output Kinetis K70 GPIO/ UART3 transmit data output/ LCD bus data output


33 PTF9 Input/Output Kinetis K70 GPIO/ UART3 request to send output/ LCD bus data output


35 PTF10 Input/Output Kinetis K70 GPIO/ UART3 clear to send input/ LCD bus data output



38 ULPI_DATA3/PTA25 Input/Output Kinetis K70 GPIO/ULPI data input/output

39 PTF12 Input/Output Kinetis K70 GPIO/ UART2 clear to send input/ LCD bus data output

40 ULPI_DATA2/PTA24 Input/Output Kinetis K70 GPIO/ULPI data input/output

41 PTF21 Input/Output Kinetis K70 GPIO/ ADC channel input/ UART5 request to send output/ LCD bus data output


43 PTF22 Input/Output Kinetis K70 GPIO/ ADC channel input/ I2C0 serial clock input/output/ UART5 clear to send input/ LCD bus data output


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45 PTF23 Input/Output Kinetis K70 GPIO/ ADC channel input/ I2C0 serial data input/output/ LCD bus data output

46 ULPI_DIR/PTA7 Input/Output Kinetis K70 GPIO/ ADC channel input/ ULPI direction control input

47 PTF24 Input/Output Kinetis K70 GPIO/ ADC channel input/ CAN1 receive input LCD bus data output

48 ULPI_NXT/PTA8 Input/Output Kinetis K70 GPIO/ ADC channel input/ ULPI next data input

49 PTF25 Input/Output Kinetis K70 GPIO/ ADC channel input/ CAN1 transmit output/ LCD bus data output

50 ULPI_STP/PTA9 Input/Output Kinetis K70 GPIO/ ADC channel input/ ULPI_STP output



54 PTD15 Input/Output Kinetis K70 GPIO/ SPI2 chip select input/output/ SDHC DAT7 input/output/ LCD bus sync output

55 PTF13 Input/Output Kinetis K70 GPIO/ UART2 receive data input/ LCD bus data output

56 PTD14 Input/Output Kinetis K70 GPIO/ SPI2 serial data input/ SDHC DAT6 input/output/ LCD bus sync output

57 PTF14 Input/Output Kinetis K70 GPIO/ UART2 transmit data output/ LCD bus data output

58 PTD13 Input/Output Kinetis K70 GPIO/ SPI2 serial data output/ SDHC DAT5 input/output/ LCD bus DE output


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60 PTD12 Input/Output Kinetis K70 GPIO/ SPI2 serial clock input/output/ SDHC DAT4 input/output/ LCD bus clock output

61 PTF16 Input/Output Kinetis K70 GPIO/ SPI2 chip select input/output/ UART0 clear to send input/ LCD bus data output

62 PTE4 Input/Output Kinetis K70 GPIO/ UART3 transmit data output/ SPI1 chip select input/output/ SDHC DAT3 input/output/ LCD bus data output

63 PTF17 Input/Output Kinetis K70 GPIO/ SPI2 serial clock input/output/ UART0 receive input/ LCD bus data output

64 PTE5 Input/Output Kinetis K70 GPIO/ UART3 receive data input/ SPI1 chip select input/output/ SDHC DAT2 input/output/ LCD bus data output

65 PTF18 Input/Output Kinetis K70 GPIO/ SPI2 serial data out/ UART0 transmit data/ LCD bus data output

66 PTE0 Input/Output Kinetis K70 GPIO/ ADC channel input / I2C1 serial data input/output/ UART1 transmit data output/ SPI1 chip select input/output/ SDHC DAT1 input/output/ RTC clock output/ LCD bus data output

67 PTF19 Input/Output Kinetis K70 GPIO/ SPI2 serial data input/ UART5 receive data input/ LCD bus data output

68 PTE1 Input/Output Kinetis K70 GPIO/ ADC channel input / I2C1 serial clock input/output/ UART1 receive data input/ SPI1 serial data input/output/ SDHC DAT0 input/output/ LCD bus data output

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69 PTF20 Input/Output Kinetis K70 GPIO/ SPI2 chip select input/output/ UART5 transmit data output/ LCD bus data output

70 PTD11 Input/Output Kinetis K70 GPIO/ SPI2 chip select input/output/ UART5 clear to send input/ SDHC clock input/ LCD bus contrast output

71 PTD2 Input/Output Kinetis K70 GPIO/ UART2 receive data input/ SPI0 serial data output

72 PTE2 Input/Output Kinetis K70 GPIO/ ADC channel input / UART1 clear to send input/ SPI1 serial clock input/output/ SDHC clock output/ LCD bus data output

73 PTD3 Input/Output Kinetis K70 GPIO/ UART2 transmit data output/ SPI0 serial data input

74 PTE3 Input/Output Kinetis K70 GPIO/ ADC channel input / UART1 request to send output/ SPI1 serial data input/output/ SDHC commands input/output/ LCD bus data output

75 PTE11 Input/Output Kinetis K70 GPIO/ ADC channel input/ UART5 request to send output/ LCD bus data output

76 PTE6 Input/Output Kinetis K70 GPIO/ UART3 clear to send input/ SPI1 chip select input/output/ LCD bus data output

77 PTE12 Input/Output Kinetis K70 GPIO/ ADC channel input/ LCD bus data output

78 PTE7 Input/Output Kinetis K70 GPIO/ UART3 request to send output/ LCD bus data output

79 PTE9 Input/Output Kinetis K70 GPIO/ ADC channel input/ UART5 receive data input/ LCD bus data output

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Not Connected (1 pins)

22 E_RMII_CLK Input/Output Kinetis K70 external clock input/ GPIO

Connection of this pin to Kinetis K70 MCU requires installation of a jumper resistor on the K70 SOM. This pin can be left unconnected on a baseboard or connected to GND for lower EMI.

Table 3: K70 SOM P2 Connector

2.15.1. Unavailable Signals of Kinetis K70 MCU

The following signals of the Kinetis K70 MCU are not available on the interface connectors. These signals are unused and left unconnected in the K70 SOM design:


F8 PTD1 Input/Output Kinetis K70 GPIO/ ADC channel input/ SPI0 serial clock input/output/ UART2 clear to send intput/ LCD bus data output

M6 TAMPER7 Input/Output Kinetis K70 tamper input/output

P2 PGA3_DM Input Kinetis K70 ADC channel differential input

Table 4: Unavailable Signals of Kinetis K70 MCU

3. Mechanical Specifications

3.1. K70 SOM Mechanicals

The K70 SOM is implemented as a miniature 30 x 57 x 4.8 mm module.

The K70 SOM PCB thickness is 1.6+/- 0.16 mm. The maximum height of SOM components is 1.6 mm.

The K70 SOM includes a mounting hole so that the module can be mechanically secured to a baseboard, reducing the risk of connector-to-PCB intermittence that might occur during NEBS vibration and earthquake testing (or during the real events those tests simulate).

The following figure shows the location of the mounting hole and SOM connectors on the module:

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Figure 2: K70 SOM Bottom View

3.2. K70 SOM Connector Mechanicals

On a baseboard, the K70 SOM is installed into two 80-pin Hirose DF40 series 0.4mm-pitch board-to-board connectors. The exact part number of the connectors is Hirose DF40C-80DP-0.4V(51). Mechanical details of the connectors can be found in the corresponding datasheet.

The recommended mating connectors for a baseboard are the Hirose DF40HC(4.0)-80DS-0.4V connector, which provides 4 mm stacking height for the k70 SOM. The maximum height of the SOM above a baseboard for 4 mm stacking height is 7.6 mm.

4. Environment Specifications

4.1. Recommended Operating Conditions

The following table lists the recommended operating conditions of the K70 SOM:

Symbol Parameter Range

TA Ambient temperature -35 to +85 ºC

VCC3 +3.3 V power supply +3.3 V +/-5%

VCC1V8 Optional +1.8 V power supply +1.8 V +/-5%

Table 5: Recommended Operating Conditions

Date post:	30-Jul-2020
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