ktmt_on tap

5/28/2018 ktmt_on tap

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TRNG I HC BCH KHOA

KHOA KHOA HC & K THUT MY TNH

n tp cui kMn: Kin Trc My Tnh - 504002

TP. HCM 11/2013


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Ni dung

I. Single clock processor..........................................................................................................3

I.1 Single clock processor...................................................................................................3

I.2 Bi tp ..........................................................................................................................6I.3 p n/Gi .................................................................................................................7

II. Pipeline processor.............................................................................................................9

II.1 Pipeline processor .........................................................................................................9

II.2 Bi tp: ....................................................................................................................... 11

II.3 p n/gi ............................................................................................................... 12

III. Memory .......................................................................................................................... 14

III.1 Memory ...................................................................................................................... 14

III.2 Bi tp: ....................................................................................................................... 19

III.3 p n/Gi ............................................................................................................... 20


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Thc hnh kin trc my tnh n tp ktmt CS 2013

3

Cc yu t nh hng n hiu xut ca h thng.

- di ca chng trnh (instruction count)- S chu k trn 1 lnh (CPI)- Thi gian ca 1 chu k (clock cycle time)

Cc kiu format ca tp lnh trong MIPS.

- Op: opcode ca lnh-

Rs, Rt, Rd: thanh ghi- Sa: dng trong lnh shift- Immediate: i din cho s- Funct: 6 bit function

I. Single clock processorI.1 Single clock processor

- a im: mt clock mt chu k- Nhc im: mt chu k tn nhiu thi gian, mi lnh d nhanh hay chm u thc thi

trong mt chu k.- Kin trc single cycle

o Thanh PC tr n lnh ang thc thio Instruction memory: cha code thc thi, khi ny ch cho php co Registers file cha 32 thanh ghi, do cn 5 bit xc nh thanh ghi no

(25=32) xc nh chi tit thanh ghi ta tham kho bng thanh ghi di

o B m rng du: mc ch c bn l m rng du t con s 16bit 32bitso B chn (MUX): dng chn ng vo trong trng hp c nhiu ng vo v 1ng ra, hoc chn ng ra trong trng hp c 1 ng vo v nhiu ng ra. Tn hiu

select quyt nh s la chn o ALU: thc hin tnh ton.o Data memory: l vng nh cha d liu trong phn data. Ch c lnh LOAD v

STORE mi c th truy xut vo khi ny.


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Hnh 1: Kin trc single cycle processor

- Bng thanh ghi:

- Bng gi tr ca ALUopInput output 4bit

encoding

Op[6bit] funct[6bit] ALUCtrlR-type Add ADD 0000


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R-type Sub SUB 0010R-type And AND 0100R-type Or OR 0101R-type Xor XOR 0110R-type Slt SLT 1010

Addi X ADD 0000Slti X SLT 1010Andi X AND 0100Ori X OR 0101Xori X XOR 0110Lw X ADD 0000Sw X ADD 0000Beq X SUB 0010Bne X SUB 0010J X x X

- ngha ca cc tn hiu iu khin.Ta mc nh hiu tn hiu tch cc l bng 1, tn hiu khng tch cc l 0

Tn hiu ngha Gi tr = 1 Gi tr = 0RegDest Chn thanh ghi ch Rd lm thanh ghi ch Rt lm thanh ghi chRegWrite Cho php ghi kt qu ngc

vo thanh ghiCho php Khng cho php

ExtOp Dng cho phn m rng duca khi dng con s

M rng du Khng quan tm, outpukhi ny l zero

ALUSrc Chn kiu thc thi da vo kiulnh nh hnh xxx

Thanh ghi vi s Thanh ghi vi thanh ghi

Memwrite Cho php ghi vo vng datamemory(dng cho lnh store)

Cho php ghi Khng cho php ghi

MemRead Cho php c t vng datamemory(dng cho lnh load)

Cho php c Khng cho php c

MemtoReg Dng chn ng t datamemory n thanh ghi(lnh load)

Chn ng t datamemory n thanhghi(lnh load)

Chn ng t kt quALU n thanh ghi(dng cho cc lnh tnhxong kt qu v la k vo thanh ghi)

Beq, Bne Dng cho cc lnh nhy c iukin

Nu iu kin nhy thamn, PC s di 1 onn nhn

Khi iu kin khng khi PC = PC + 4 ( thlnh tip theo

J Dng cho lnh nhy khng ciu kin

Nhy n nhn cn PC ch n lnh tip theo

PCSrc Chn ngun cho PC Khi lnh nhy xy ra Khi lnh nhy ko xy raALUop Chn thnh phn tnh trong X X


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ALU (trong ALU c nhiu b,b cng, nhn, OR, AND )V c nhiu hn 2 b nn cndng nhiu hn 1 bitTham kho bng di

Ch :

Mnh s khng quan tm n RegDest,Memread, MemtoReg khi tn hiu RegWrite = 0Khi ALUSrc = 0 th ta khng quan tm n ExtopTham kho thm b tnh hiu ca lnh c th slide Main Control Signal Values silde45.

- Bng lit k ng i c tr lu nht ca cc lnh (b qua tr ca b m rng du,MUX, ADDER, dy, PC)

Kiu lnh Data pathALU

InstructionFetch

DecodeReg Read

ALU RegWrite

Load InstructionFetch

DecodeReg Read

ComputeAddress

Memory Read RegWrite

Store InstructionFetch

DecodeReg Read

ComputeAddress

MemoryWrite

Branch InstructionFetch

Reg ReadBr Target

Compare& PC Write

Jump InstructionFetch

DecodePC Write

I.2 Bi tp1) Dng li kin trc c miu t hnh 1 gii cc cu sau:

Cho bng delay ca cc khi nh sau:

I-Mem 200psAdder 100psMux 30ps

ALU 180psRegs 150psD-Mem 200psControl 100ps

a) Xc nh ng i c tr lu nht ca lnh AND, LOAD, v tnh tr ?


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b) Xc nh cc tn hiu ca khi control unit (main Unit) khi thc thi lnh BEQ $1, $2,ABC. Vi $1 = 0x00FF, $2 = 0x00FE

c) Thnh phn phn cng no khng s dng khi ta thc thi lnh SLTI, lnh J2) B qua delay ca cc khi add, mux, control.

a) Xc nh data path v thi gian ca cc kiu lnha. ALUb. LOADc. STOREd. BRANCHe. JUMP

b) Xc nh thi gian, ca single cycle v multi-cyclec) Gi s c 1 chng trnh gm 40% ALU, 20% Loads, 10% stores, 20% branches, &

10% jumpsa. Tnh CPI trong trng hp single cycle , multi cylceb. Tnh speed up

I.3 p n/Gi 1a)

- lnh ADD : I-MEM (200) REGs(150) MUX(30) ALU(180) MUX(30) REGs(150) = 740

- lnh LOAD : I-MEM (200) REGs(150) MUX(30) ALU(180) D-MEM(200)MUX(30) REGs(150) = 940

1b)

- Xt lnh BEQ $1, $2, ABC. Vi $1 = 0x00FF, $2 = 0x00FE , lnh ny c ngha l nuthanh ghi $1 m bng thanh ghi $2 th n s nhy n nhn ABCM ta thy ni dung thanh ghi $1 v $2 l khc nhau nn lnh BEQ khng thc hin nhyn nhn ABC t ta a ra tn hiu cho lnh nh sau:

Tn hiu Gi tr Gii thchRegDest X Khng quan tmRegWrite 0 Khng ghi kt qu vo thanh ghi

ExtOp X Khng quan tmALUSrc 0 Thanh ghi vi thanh ghiMemwrite 0 Khng truy xut vo vng dataMemRead X Khng quan tmMemtoReg X Khng quan tmBeq 1 Lnh BEQBne 0 Khng phi lnh BNEJ 0 Lnh branch khng phi lnh jump


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PCSrc 0 iu kin nhy khng xy ra

ALUop 0010 Tham kho bng xxx trn

1c)

- lnh SLTI dng set gi tr thanh ghi ch ln 1 nu thanh ghi em so snh nh hn 1s cho trc, ngc li n s reset gi tr thanh ghi ch xung 0 nu nu thanh ghi emso snh ln hn 1 s cho trc.V d SLTI $1, $2, 100 th thanh ghi $1 = 1 khi $2 < 100, ngc li $1 = 0 khi $2 >= 100t ta xt ng i ca lnh nh sau:Qua I-MEM (lnh no cng qua I-MEN) -> qua control unit, reg files, khng dng b mrng du, khng dng b cng cho PC, dng mux qua ALU khng dng D-MEMqua MUX , Reg files

2a)Instructionclass

Instructionmemory

Registerread

ALUOperation

Datamemory

RegisterWrite

Total

ALU 200 150 180 150 680psLoad 200 150 180 200 150 880psStore 200 150 180 200 730psBranch 200 150 180 530psJump 200 150 350ps

2b)

- Tnh thi gian ca single cycle = max ca tt c cc lnh , c th trong trng hp mylnh LOAD c gi tr ln nht ( thi gian thc thi lu nht) single cycle = 880ps

- Tnh thi gian ca multi cycle = max ca 5 bc(IF- INSTRUCTION MEMORY, ID REG FILES, EXE- ALU, MEM DATA MEMORY, WRITE BACK REG FILES)trong 1 lnh, c th trong trng hp ny bc Instruction memory tn nhiu thi giannht multi cycle = 200ps

2c)

- CPI l s chu k trn lnho CPI ca single cycle = 1o CPI ca multi cycle = 0.44 + 0.25 + 0.14+ 0.23 + 0.12 = 3.8

- Speed up = thi gian chy ca single cycle / thi gian chy ca multi cycle = (1 * 880) / (3.8 * 200) = 880/760 = 1.16Thi gian chy ca 1 chng trnh = CPI * thi gian ca mt cycle.


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II. Pipeline processorII.1 Pipeline processor

- Pipe line chia lnh thc thi ra thnh 5 bc, mi bc thc thi trong trong mt chu ko IF: ly lnh t I-MEM ln.o ID: gii m lnh l lnh g, c gi tr thanh ghi, bit c a ch cho lnh

nhy, r nhnho EX: thc thi lnh hay l tnh ton a ch cho lnh load/storeo MEM: truy xut data i vi lnh load/storeo WB: ghi ngc kt qu li thanh ghi

- Hiu sut ca pipe line vi single cycle.Ta chia lnh ra thnh k bc

o Thi gian thc thi n lnh ca single cycle = n * single cycleo

Thi gian thc thi n lnh ca pipe line = (k + n -1) * pipeline clock cycleTa gi s single cycle = k* pipeline clock cycleo Khi speedup = (n* k* pipeline clock cycle)/ ((k + n -1) * pipeline clock cycle )

Khi n ln th speedup tin n k (tc l pipeline nhanh ti a gp k ln single cycle)

Ch :

Pipeline khng rt ngn thi gian thc thi ca mt lnh, m n ch tng hiu xut lnbng cch tng thng nng ca my. Khi m cc bc ca mt lnh c thi gian thc thikhc nhau th s lm gim speed up.Thi gian fill v drain cng ng thi lm gim speed up

hin thc pipeline ngi ta dng thanh ghi la kt qu li mi bc.- Tn hiu t khi control unit ( main control)

o Tt c tn hiu iu khin c sinh ra bc ID- Mi bc dng 1 s tn hiu iu kin

o RegDst c dng trong bc IDo ExtOp, ALUSrc, ALUCtrl ,J, Beq, Bne, zero c dng trong bc EXEo MemRead, MemWrite, MemtoReg dng trong bc MEMo RegWrite dng trong bc WB

- Khi hin thc pipe line s sinh ra mt s trng hp hazard, tc l nhng trng hp mta thc thi theo ng nguyn tc ca pipe line th s gy ra sai chng trinh, c 3 loihazard

o Structural hazards: xy ra khi c s tranh chp ti nguyn phn cng, 2 lnh cngdng chung phn cng trong cng chy k

o Data hazards: xy ra khi c s ph thuc d liuo Control hazards: xy ra i vi cc lnh nhy c iu kin


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Khi hazard xy ra m ta khng x l n hoc x l khng c th s to ra delay lmgim hiu xut tnh ton.

a) Structural hazards:

V d:Gii quyt

o a tt c bc WB qua chu k th 5 ca lnho Hoc thm phn cng cho WB ( thm 1 cng c/ghi na cho register file)

b) Data HazardsS ph thuc gia cc lnh: l hin tng xy ra khi lnh sau ly kt qu ca lnh phatrc trc khi lnh pha trc a ra kt qu

- Read After Write RAW HazardI: add $s1, $s2, $s3 #thanh ghi $s1 c ghi

J: sub $s4, $s1, $s3 #thanh ghi $s1 c cKhi data hazard xu

t hin khi lnh J c $s1 m lnh I li cha tnh xong kt qu ca$1Phng php gii qut data hazard

o Chn stall vo m bo lnh trc tr kt qu v m lnh sau c th c ckt qu trong chu k k tip( phng php ny khng tn ti nguyn phncng, ch to ra delay cho chng trnh gim hiu xut)

o Dng k thut forward (phng php ny cn thm ti nguyn phn cng hinthc) + chn stall khi cn thit.

Khi xy ra hazard i vi lnh load cho d ta c dng k thut forward th cngphi tn 1 stall gii quyt chng hin thc forward ngi ta thm b mux cho vic la chn input cho ALUCc lnh khc (khc lnh load) th kt qu c cho ra bc ALU (EXE) nnkhi ta dng k thut forward s khng cn stall na.

Gi s c s ph thuc gia cc lnh nh sau

123

4o Lnh 2 ph thuc 1,o Lnh 3 ph thuc 1,o Lnh 4 ph thuc 1.

Khi dng k thut forward cho lnh

o lnh 2 th tao forward t EXE EXE (cch nhau 1 lnh)


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o lnh 3 th tao forward t MEMEXE (cch nhau 2 lnh)o lnh 4 th tao forward t WBEXE (cch nhau 3 lnh)

- Write After Read: Name DependenceI: sub $t4, $t1, $t3 # $t1 c c trcJ: add $t1, $t2, $t3 # $t1 c ghi sau

R rng l ta th

y khng c s ph thuc d liu y, ch c ph thuc tn bin. loaib s ph thuc v tn bin th ta i tn thanh ghi.

I: sub $t4, $t1, $t3J: add $t5, $t2, $t3

- Write After write: Name DependenceI: sub $t1, $t4, $t3 # $t1 c ghiJ: add $t1, $t2, $t3 # $t1 c ghi li ln na

R rng l ta thy khng c s ph thuc d liu y, ch c ph thuc tn bin. kt quch ph thuc vo lnh J sau. loai b s ph thuc v tn bin th ta i tn thanh ghi.

I: sub $t1, $t4, $t3J: add $t5, $t2, $t3

- Read After Read: khng gy ra s ph thucII.2 Bi tp:

1) Cho s v cc thng s ca b x l single clock nh hnh bn di.

Thi gian delay ca mi khi cho nh hnh bn di.


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I-Mem 200psALU 150psRegs 200psD-Mem 200ps

a) B qua tr ca khi ADD, MUX, Control. Tnh single cycle, pipeline clock?b) Tnh thi gian thc thi ca chng trnh gm 150 line code i vi single cycle v

pipeline. T tnh speed up so snh single cycle v pipeline ( khng c stall)c) Gi s chng trnh khng c stall v thng k c l c ALU 50% Beq 25% lw

15% sw10%. Tnh speed up gia multi cycle v pipeline

2) Cho on code sau:ADDI $1, $zero, 100ADDI $2, $zero, 100

ADD $3, $1, $2LW $4, L_4LW $5, L_5AND $6, $4, $5SW $6, L_KQ

a) Xc nh s ph thut gia cc lnh v thanh ghi no gy ra s ph thuc b) Chn stall gii quyt hazard trn, cn bao nhiu stall?c) Sp xp li th t cc lnh sao cho khi chy on code th t stall nht m

tnh logic ca chng trnh vn khng id) Dng k thut forward gii quyt hazard th khi chy s c bao nhiu

stall.

II.3 p n/gi 1a)

- Single cycle = thi gian gian thc thi lnh di nht (lnh load) = I-Mem Regs ALU D-Mem Regs = 200 + 200 + 150 + 200 + 200 = 950ps

- Pipeline clock = max (I-Mem, Regs, ALU, D-Mem, Regs) = 2001b)

- Thi gian thc thi 150 ca single cycle = 150 * 950 = 142500 ps- Thi gian thc thi 150 ca pipeline = (5 + 150 - 1)* 200 =30800 ps- Speed up = 142500/30800 = 4.62

1c)


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- CPI ca multi cycle = (50%* 4 + 25%*3 + 15%*5 + 10%*4) = 3.9- CPI ca pipeline khi khng c stall l = 1- Thi gian thc thi = CPI * s lnh * thi gian 1 chu k- Speed up = thi gian mutli cycle /thi gian pipeline = (3.9 * s lnh * 200)/( 1 *s lnh *

200)

2a)

ADDI $1, $zero, 100ADDI $2, $zero, 100ADD $3, $1, $2LW $4, L_4LW $5, L_5AND $6, $4, $5SW $6, L_KQ

Lnh no m cc ton hng c t mu m th

hin s ph thuc qua thanh ghi .

2b)

- 9 stall, lc chn stall vo m bo l nhng ch cn c gi tr thanh ghi (ID) phi sauchu k ghi kt qu ca thanh ghi

2c)

Mt trong nhng cch sp xp lm gim stall

LW $4, L_4LW $5, L_5ADDI $1, $zero, 100ADDI $2, $zero, 100AND $6, $4, $5ADD $3, $1, $2SW $6, L_KQCn li 3 stall

2d)

1 stall. Sinh vin v hnh hiu r hnHnh nh so snh single cycle, multi cycle, v pipe line

single cycleload add jump store 5 5 5 5 Multi cycle


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load add jump store branch

IF ID EXE MEM WB IF ID EXE WB ID IF ID IF EXE MEM ID IF ALUPipe lineIF ID EXE MEM WB

IF ID EXE MEM WB

IF ID EXE MEM WBIF ID EXE MEM WBIF ID EXE MEM WB

III. MemoryIII.1Memory

Gm cc bus c bn sau

- Address:n bit dng xc nh a ch trong ram, khng gian a ch 2n- Data: m bits dng xut/ nhp d liu, rng ca ram l mbits- OE: output enable , khi tn hiu ny tch cc tng ng vi vic c d liu t RAM- WE: write enable , khi tn hiu ny tch cc tng ng vi vic ghi d liu vo RAM

Cc im khc nhau c bn gia SRAM v DRAM

SRAM DRAM- Cu to 6 transistor

o t, nhanh- Tnh, khng cn refesh gi trnh a ch theo hng- .

- 1 transistor + 1 to R, chm hn

- ng, v t in r r in theo thigian nn cn phi refesh gi tr theo chuk

- nh a ch theo ma trn- .


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SRAM

DRAM

- Cacheo Do tc pht trin ca ALU qu nhanh so vi Memory nn to ra khong cch

kh xa gia ALU v MEM, do cn c cache lm b m gia ALU vMEM

o Thng c lm bng SRAMo Mc ch lm gim thi gian truy xut memory

- Tc v thi gian truy xut ca memory c xp theo th t sau ( ch mang tnh chttham kho)1. Registers (size < 1 KB),

o Access time < 0.5 ns2. Level 1 Cache (size 8 64 KB)

o Access time: 1 ns3. L2 Cache (512KB 8MB)

o Access time: 3 10 ns4. Main Memory (4 16 GB)

o Access time: 50 100 ns5. Disk Storage (> 200 GB)

o Access time: 5 10 ms- Temporal Locality (thi gian) mt bin, thc th c truy xut th c th n s c truy

xut ln na. thng xut hin trong nhng vng lp, hay gi hm/th tc nhiu ln


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i vi truy xut theo thi gian th xu hng l thng gi block trong cache. Nhmtruy xut ln sau

- Spatial Locality (khng gian) lnh/ data trong vng nh khi c truy xut th c th cclnh/data gn n s c truy xut. thng xut hin trong khai bo mng, thc thi tunti vi truy xut theo khng gian th xu hng l thng chun b trc block k tip.

- Block placement ( phng php t block vo cache)o Direct mapped

Mi block c xc nh mt v tr t duy nht. n l s block trong cache th block th m trong b nh (RAM) s c t

vo v tr m%n trong cacheo Full associative

Mi block c c vo v tr no m cn trng trong cache.o Set associative

Mi block c xc nh mt set duy nht. trong set c k s la chn,t block vo 1 trong k ch trng n l s set trong cache th block th m trong b nh (RAM) s c t

vo v tr m%n trong cache- v d:

Trong K- way Set associative th k block s gp thnh 1 set, v d trn k = 2.

- Block identification (xc nh block) xc nh a ch ngi ta chia a ch ra lm 3 phn (Tag, Index, block offset)31 0Tag Index Block offset

o Block offset


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Xxc nh thnh phn no trong block c truy xut. xc nh bockoffset c bao nhiu bit th ta i xc nh trong block c bao nhiu phnt

Xc nh s phn t bng cch ly (size of block)/(size of n v truyxut)

o Index: xc nh s block trong cache trong trng hp Direct mapped,

Xc nh s block bng cch ly (size of cache)/(size of block) Xc nh s set trong cache trong trng hp k-way set associative

Xc nh s set bng cch xc nh s block sau ly s block chia cho k.

Bng 0 trong trng hp full associativeo Tag

xc nh block no ang nm trong cache Tag bit = 32 index bits block offset bits ( trong kin trc 32 bits)

- Block replacement (thay th block):Khi mt block vo m khng cn ch trng t vo th cn phi thay block c bngblock mi

o Trong trng hp direct mapped, ti v mi block ch c 1 ch t nn ta khngnhc n y

o FIFO ( ci no c t vo trc th s c ly ra trc)o Ramdomo LRU ( ci no t dng nht th c thay th trc)

- Write strategy (chin lc ghi ngc li cache, memory)o Write Back: ch updata cache, khi c yu cu hay cn thay th th mi update gi

tr sau cng xung memory Cn bit valid ( xc nh block c valid hay khng) v bit modified

( xc nh block c update cha) Kh hn thc t tn la lng bng thng ca h thng

o Write Through: updata c cache v memory Cn bit valid ( xc nh block c valid hay khng) n gin d hin thc

Tn la lng bng thng ca h thng v phi update nhiu- Miss/hit

o Miss: cn truy xut m tm khng thy trong cache. Do phi a block cha ci ta mun truy xut vo cache sau truy xut n

o Hit: cn truy xut v tm thy ci mun truy xut trong cache.- Miss penaly: s chu k x l cache miss- Hit rate = hit/(hit + miss)


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- Miss rate = miss /(hit + miss) = 1 hit rate- I-Cache Miss Rate = Miss rate trong lc truy xut I-MEM- D-Cache Miss Rate = Miss rate trong lc truy xut D-MEM

V d: chng trnh c 1000 lnh trong c 25% l load/store. Bit lc c I-MEM bmiss 150, D-MEM b miss 50. Tm I-Cache Miss Rate, D-Cache Miss Rate

o I-Cache Miss Rate = s ln miss / s ln truy xut I-MEM = 150/1000 = 15%o I-Cache Miss Rate = s ln miss / s ln truy xut D-MEM = 50/(1000*25%)

=50/250 = 20%- Khi cache miss th s gy ra stall xc nh bao nhiu stall ta i tm cc thng s sau

o Memory stall cycles = Combined Misses * Miss Penalty Miss Penalty: clock cycles to process a cache miss Combined Misses = I-Cache Misses + D-Cache Misses

I-Cache Misses = I-Count I-Cache Miss Rate D-Cache Misses = LS-Count D-Cache Miss Rate

o LS-Count (Load & Store) = I-Count LS Frequencyo Memory Stall Cycles Per Instruction = Combined Misses Per Instruction Miss

Penalty Combined Misses Per Instruction = I-Cache Miss Rate + LS Frequency

D-Cache Miss RateMemory Stall Cycles Per Instruction = I-Cache Miss Rate Miss Penalty + LSFrequency D-Cache Miss Rate Miss PenaltyV d: Instruction count (I-Count) = 106 lnh, 30% lnh loads/stores, D-cachemiss rate l 5% v I-cache miss rate l 1%, cho Miss penalty l 100 chu k, tnhcombined misses per instruction and memory stall cycles

1% + 30% * 5% = 0.025 combined misses mi lnh tng ng 25misses per 1000 instructions

Memory stall cycles = 0.025 * 100 (miss penalty) = 2.5 stall cycles perinstruction

Total memory stall cycles = 106* 2.5 = 2,500,000- CPI

CPIMemoryStalls= CPIPerfectCache+ Mem Stalls per InstructionV d: cho CPI = 1.5 khi khng c stall, Cache miss rate l 2% i vi instruction v 5%i vi data. Lnh loads v stores chim 20%. Cho trc miss penalty l 100 chu k i

vi I-cache v D-cache. Tnh CPI ca h thng?Mem stalls cho mi lnh = 0.02*100 + 20%*0.05*100 =3CPIMemoryStalls = 1.5 + 3 = 4.5 cycles

- Average Memory Access Time (AMAT) thi gian truy xut b nh trung bnho AMAT = Hit time + Miss rate * Miss penalty

Do gim thi gian truy xut th Ta gim Hit time: bng cch dng b nh cache nh, n gin


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Gim Miss Rate: bng cch dng b nh cache ln, block size ln v k-way set associativity vi k ln

Gim Miss Penalty bng cch thit kt nhiu cache nhiu mcV d: tm AMAT khi bit Cache access time (Hit time) of 1 cycle = 2 ns, Miss penalty =20 clock cycles, miss rate of 0.05 per access

AMAT = 1 + 0.05 20 = 2 cycles = 4 ns

o Khi khng c cache th tra truy xut trc tip xung memory nn tn 20 chu k(miss penalty)

III.2Bi tp:1) Cho b nh cache c dung lng 256KB, block size l 4word, mi ln truy xut

1byte. Xc nh s bit ca cc trn tag, index, block offset trong cc trng hpa) Direct mappedb) Full associcativec) 2 way set associcative

2) Cho b nh cache c dung lng 1MB, block size l 256B, mi ln truy xut 1 word.Xc nh s bit ca cc trn tag, index, block offset trong cc trng hpa) Direct mappedb) Full associcativec) 4 way set associcative

3) Trong cache c 8 block, mi block l 4word. Xc nh s ln miss/ hit khi h thngtruy xut vo cc a ch theo t t sau.

0x0001002A0x000100200x0002006A0x000200660x000200220x0001002BTrong cc trng hpa) Direct mappedb) Full associcativec) 2 way set associcative

4) Cc bi tp v miss rate , cpi coi v d v lm bi tp trong slide


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III.3p n/Gi 1)- S phn t trong 1 block = (size of block)/(size of phn t truy xut) = 4 word /1 byte =

4*4 bytes/ 1 byte = 16- S khi block trong cache = size of cache / size of block = 256KB / 4 word = 28*210/4*4

= 214blocks

1a) Direct mapped: block offset 4 bits, index = 14 bits, tag = 32 4 -14 = 14 bits

1b) Full associcative: block offset 4 bits, index = 0 bits, tag = 32 4 = 28 bits

1c) 2 Ways set associative: 2 block to thnh 1 set m c 214block nn c 213sets

Block offset 4 bits, index = 13 bits, tag = 32 4 -13 = 15 bits

2)- S phn t trong 1 block = (size of block)/(size of phn t truy xut) = 256B / 4 bytes =

28bytes/ 22byte = 26- S khi block trong cache = size of cache / size of block = 1MB / 256B = 210*210/28= 212

blocks

2a) direct mapped: block offset 6 bits, index = 12 bits, tag = 32 6 -12 = 14 bits

2b) full associcative: block offset 6 bits, index = 14 bits, tag = 32 4 = 28 bits

2c) 4 ways set associative: 4 block to thnh 1 set m c 212block nn c 210sets

Block offset 6 bits, index = 13 bits, tag = 32 6 -10 = 16 bits

3)3a) Da vo ti ta tnh c c 4 bits block offset, 3 bit index. Do ta phn tch a chnh bn di

address Tag Index Blockoffset

Miss/hit

Gii thch

0x0001002A 0000 0000 0000 0001 0000 0000 0 010 1010 M First access0x00010020 0000 0000 0000 0001 0000 0000 0 010 0000 H0x0002006A 0000 0000 0000 0010 0000 0000 0 110 1010 M First access0x00020066 0000 0000 0000 0010 0000 0000 0 110 0110 H0x00020022 0000 0000 0000 0010 0000 0000 0 010 0010 M Khc tag0x0001002B 0000 0000 0000 0001 0000 0000 0 010 1011 M Khc tag

3b) Full associative


21/21


21

address Tag Blockoffset

Miss/hit

Gii thch

0x0001002A 0000 0000 0000 0001 0000 0000 0010 1010 M First access0x00010020 0000 0000 0000 0001 0000 0000 0010 0000 H0x0002006A 0000 0000 0000 0010 0000 0000 0110 1010 M First access

0x00020066 0000 0000 0000 0010 0000 0000 0110 0110 H0x00020022 0000 0000 0000 0010 0000 0000 0010 0010 M First access0x0001002B 0000 0000 0000 0001 0000 0000 0010 1011 H

3c) 2 ways set associative, c

n 2 bit index

address Tag Index Blockoffset

Miss/hit

Gii thch

0x0001002A 0000 0000 0000 0001 0000 0000 00 10 1010 M First access0x00010020 0000 0000 0000 0001 0000 0000 00 10 0000 H0x0002006A 0000 0000 0000 0010 0000 0000 01 10 1010 M First access0x00020066 0000 0000 0000 0010 0000 0000 01 10 0110 H

0x00020022 0000 0000 0000 0010 0000 0000 00 10 0010 M Khc tag0x0001002B 0000 0000 0000 0001 0000 0000 00 10 1011 M Khc tag

Date post:	18-Oct-2015
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