19
Work on this while you wait! 1001 (9) x 0011 (3)
Work on this while you wait!
1001 (9)
x 0011 (3)
More Finite State Machines: Multiplication as an Example
Lab 3 part 2!
Learning Objectives Design a Finite State Machine that controls a datapathUse Register Transfer Language to describe how state is modified each clock cycle
Step 1: Understand your problem
You try another example
1001 (9)
x 0011 (3)
1001
1001
0000
+0000 .
00011011 (27)
int shift_add_multiply(unsigned short X, unsigned short Y) {unsigned int A = (unsigned int) X;unsigned short B = Y;unsigned int P = 0;
while (B != 0) {if ((B & 1) == 1) {
P = P + A;}B = B >> 1;A = A << 1;
}return P;
}
Step 2: Understand the datapath
Identify needed state components from variables (what state is stored?)
int shift_add_multiply(…) {unsigned int A = (unsigned int) X;unsigned short B = Y;unsigned int P = 0;
return P;}
A (2N‐bit reg) END
QB (N‐bit reg)
EN
D
Q
P (2N‐bit reg) END
Q
Identify how we modify that state
while (B != 0) {if ((B & 1) == 1) {P = P + A;
}B = B >> 1;A = A << 1;
}
X Y
ALUOP
A B
A (2N‐bit reg) END
QB (N‐bit reg)
EN
D
Q
P (2N‐bit reg) END
Q
0 1 1 0<<1
>>1
Define specification for control FSMwhile (B != 0) {if ((B & 1) == 1) {P = P + A;
}B = B >> 1;A = A << 1;
}
int shift_add_multiply(…) {unsigned int A = (unsigned int) X;unsigned short B = Y;unsigned int P = 0;
while (B != 0) {if ((B & 1) == 1) {P = P + A;
}B = B >> 1;A = A << 1;
}return P;
}
Control FSM has 3 inputs and 7 outputs
B is zero (Z) B_Q[0] is 1 (B[0]) START
Load A (LA) Shift A (SA) Load B (LB) Shift B (SB) Add when 1/Zero when 0 (OP) Load P (LP) DONE
Control FSM
X Y
ALUOP
A B
=0?
A (2N‐bit reg) END
QB (N‐bit reg)
EN
D
Q
P (2N‐bit reg) END
Q
START
DONE
B_Q[0]
0 1 1 0<<1 >>1
Controland Datapath
Step 3: Design your FSM (don’t forget timing!)
int shift_add_multiply(…) {unsigned int A = (unsigned int) X;unsigned short B = Y;unsigned int P = 0;
while (B != 0) {if ((B & 1) == 1) {P = P + A;
}B = B >> 1;A = A << 1;
}return P;
}
Register transfers show source state elements, operations, and destination state elements
A = X
B = Y
P = 0
A = A << 1
B = B >> 1
P = P + A
Control FSM
X Y
ALUOP
A B
=0?
A (2N‐bit reg) END
QB (N‐bit reg)
EN
D
Q
P (2N‐bit reg) END
Q
START
DONE
B_Q[0]
0 1 1 0<<1 >>1
Start, Zero, B[0] WaitA = X, B = Y,
P = 0
DoNothing
ShiftA = A << 1, B = B >> 1
Shift‐AddA = A << 1, B = B >> 1,P = P+A
DoneDONE = 1
A B
C D
E
clk 10
X 10
Y 10
START10
A 10
B 10
P 10
STATE10
? 9 ?
? 5 ?
?
?
?
WAIT
A =
B =
Translate register transfers into control signals
Control FSM
X Y
ALUOP
A B
=0?
A (2N‐bit reg) END
QB (N‐bit reg)
EN
D
Q
P (2N‐bit reg) END
Q
START
DONE
B_Q[0]
0 1 1 0<<1 >>1
WaitA = X, B = Y,
P = 0
Wait
ShiftA = A << 1, B = B >> 1
Shift
DoNothing
DoNothing
LA LB
OP
LP
SA SB
WaitA = X, B = Y,
P = 0
DoNothing
ShiftA = A << 1, B = B >> 1
Shift‐AddA = A << 1, B = B >> 1,P = P+A
DoneDONE = 1
clk 10
X 10
Y 10
START10
A 10
B 10
P 10
STATE10
LA 10
SA 10
LB 10
SB 10
LP 10
OP 10
? 9 ?
? 5 ?
?
?
?
WAIT
1
0
1
0
1
0
9
5
18
2
36
1
72
0
0 9 45
D SA D S D SA D DONE
B[0]Z’
B[0]’Z’
B[0]Z’
B[0]’Z
