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The Nanofab Group

EE 4345 – Semiconductor Electronics

Design Project – Spring 2002

Kevin Bradford

Corey Clark 

Carlos GarciaGuillaume Gbetibouo

Eric Goebel

Fariba Pouya

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Technical Project 1.5

ANALOG BiCMOS

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Introduction

What is BiCMOS?

BiCMOS technology combines

Bipolar and CMOS transistors onto a

single integrated circuit where theadvantages of both can be utilized.

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Advantages of CMOS over Bipolar

• Power dissipation

• Noise margin

• Packing density

• The ability to integrate large comples

functions with high yields

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Advantages of Bipolar over CMOS

• Switching speed

• Currents drive per unit area

• Noise perfomance

• Analog capability

• Input/output speed

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Analog BiCMOS Complexity

• Higher performance

analog circuits• Reduced design efforts

• Faster design cycles

• Higher wafer cost

• Longer manufacturingtime

• Lower process yields

Analog BiCMOS processes are characterized by their

complexity, most needing15 masks. Some up to 30 masks.

Advantages of complexity Disadvantages of complexity

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Evolution of BiCMOS from CMOS

BiCMOS technologies have tended to evolve from CMOS

processes in order to obtain the highest CMOS

performance possible.

The bipolar processing steps have been added to the core

CMOS flow to realize the desired device characteristics.

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Fabrication Equipment

Molecular Beam Epitaxy

(MBE)

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Fabrication Equipment

Photoresist Spinner Bake-out Ovens

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Fabrication Equipment

Mask Aligner Reactive Ion Etching (RIE)

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Fabrication Equipment

Chemical Vapor Deposition

(CVD)

Plasma Quest Sputter

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Fabrication Equipment

Plasma Sputter Perkin-Elmer MBE

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Fabrication Equipment

Probe Station Scanning Electron

Microscope (SEM)

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N-well CMOS Structure

• NMOS device, built in a 15um thick P-epitaxial layer on top of 

P+substrate

•PMOS transistor, built in an implanted N-well approximately 5um deep

•P+ substrate is used to reduce latch up susceptibility by providing a lowimpedance patch through a vertical PNP device

•Polysilicon gates are used for both the PMOS and NMOS transistors

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Adding NPN Bipolar TransistorThe simplest way to add an NPN bipolar transistor to the previous CMOS

structure is by using PMOS N-well as the collector of the Bipolar device

and introducing an additional mask level for the P-base region.

• the P-base is approx 1 um deep with a doping level of about 1e17 atoms/cm^3

• the N+ source/drain ion implantation step is used for the emitter andcollector contact of the bipolar structure

• the P+ source/drain ion implantation step is used to create a P+ base

contact to minimize the base series resistance

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Contacts

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Contacts

EFn Ec 

Ev  EFi 

qfs,n 

qcs 

n-type s/c

qfm 

EFm 

metal

qfBn qVbi 

qf’nDepl reg

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Pattern Shift – NBL Shadow (1/2)

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Pattern Shift – NBL Shadow (2/2)

Stacking faults

• An extra plane of atoms

•The lack of a plane of atoms

Other Causes

• Temprature

•Pressure

•Wafer pre-leaning

•Growth precursor

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P Isolation vs. CDI

Collector Diffused IsolationP Isolation

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• Key factor in determining overall circuit performance and

density

• Collector Diffused Isolation (CDI)

 –  N-well used to form collector of NPN transistor

 –  Base and emitter consist of successive counterdoping of 

the well.

 –  CDI transistors• Saturate prematurely

• Limits low-voltage operation

• Complicates device modeling

• Causes undesired substrate injection

BiCMOS Isolation Consideration

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• System-on-a-Chip Technology

 – personal Internet access devices

 – set-top boxes

 – thin clients 

Applications of  BiCMOS Technology

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References

• Carter, Ronald. “Lecture 9 –  EE 5342” UTA 

• Cheung, Nathan “ Lecture 17 –  EE 143” UC Berkeley 

• http: //et.nmso.edu/ETCLASSES/vlsi/files/CRYSTAL.HTM

• Hastings, Alan “The Art of Analog Layout”, Prentice Hall, NewJersey, 2001

• Campbell, Stephen A. , “The Science and Engineering of 

Microelectronic Fabrication”, Oxford University Press, New York,

2001 • Alvarez, Antonio, “BiCMOS Technology and Applications”, Prentice

Hall, New Jersey, 2001