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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 1
EE247
Lecture 14• Administrative issues
Midterm exam postponed to Thurs. Nov. 5tho You can only bring one 8x11 paper with your
own written notes (please do not photocopy)o No books, class or any other kind of
handouts/notes, calculators, computers, PDA,cell phones....
o Midterm includes material covered to end of lecture 14
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 2
EE247Lecture 14• D/A converters
– D/A converters: Various Architectures (continued)• Charge scaling DACs (continued)• R-2R type DACs• Current based DACs
– Static performance of D/As• Component matching• Systematic & random errors
– Practical aspects of current-switched DACs – Segmented current-switched DACs – DAC dynamic non-idealities – DAC design considerations
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 3
Summary of Last Lecture
• Data Converters – Data converter testing (continued)
• Dynamic tests (continued) – Relationship between: DNL & SNR, INL & SFDR – Effective number of bits (ENOB)
– D/A converters: Various Architectures• Resistor string DACs• Serial charge redistribution DACs• Charge scaling DACs
• R-2R type DACs• Current based DACs
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 4
Charge Scaling DACUtilizing Split Array
• Split array reduce the total area of the capacitors required for highresolution DACs – E.g. 10bit regular binary array requires 1024 unit Cs while split array
(5&5) needs 64 unit Cs – Issue: Sensitive to parasitic capacitor
series
a l l L S B a r ra y C C C
a l l M S B a r ra y C =
∑
∑
C 2C 4C
Vref
Vout
reset
b5b4b3b2
+
-
8/7C
C 2C 4C
b1b0
C
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 5
Charge Scaling DAC
• Advantages: – Low power dissipation capacitor array does not dissipate DC power – Output is sample and held no need for additional S/H – INL function of capacitor ratio – Possible to trim or calibrate for improved INL – Offset cancellation almost for free
• Disadvantages: – Process needs to include good capacitive material not compatible
with standard digital process
– Requires large capacitor ratios – Not inherently monotonic (more later)
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 6
Segmented DACResistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB)
C C 2C 4C 8C 32 C
reset
b1b2b3b5
16C
b4
V out
b0
..........
SwitchNetwork
6bitresistor ladder
6-bitbinary weightedcharge redistribution DAC
• Example: 12bitDAC
– 6-bit MSB DACR- string
– 6-bit LSB DACbinary weightedcharge scaling
• Component countmuch lower compared to full R-
string
– Full R string4096 resistors – Segmented 64
R + 7 Cs (64 unitcaps)
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 7
Current Based DACs
R-2R Ladder Type• R-2R DAC basics:
– Simple R networkdivides both voltage& current by 2
R
V
V/2
2R 2R I I/2 I/2
Increase # of bits by replicating circuit
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 8
R-2R Ladder DAC
V B
2R 2R
Emitter-follower added to convert to high output impedance currentsources
2R 2R 2R 2R
R R R RV EE
I out
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 9
R-2R Ladder DAC
How Does it Work?
V B
Consider a simple 3bit R-2R DAC:
2R 2R 2R 2R R R
V EE
I out
1x Aunit 1x Aunit 2x Aunit 4x Aunit
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 10
R-2R Ladder DACHow Does it Work?
V B
Simple 3bit DAC:1- Consolidate first two stages:
2R 2R 2R 2R
R RV EE
I T I 1 I 2 I 3
Aunit Aunit 2Aunit 4Aunit
QT Q1Q2Q3 V B
2R 2R R
R RV EE
I 1+I T I 2 I 3
2Aunit 2Aunit 4Aunit
Q2Q3
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 11
R-2R Ladder DACHow Does it Work?
Simple 3bit DAC-2- Consolidate next two stages:
V B
2R 2R R
R RV EE
I 1+I T I 2 I 3
2Aunit 2Aunit 4Aunit
Q2Q3
V B
2R R
RV EE
I 2+I 1+I T I 3
4Aunit 4Aunit
Q2Q3
Tot al Tota l Total 3 2 1 3 2 1T
I I I I I I I I , I , I 2 4 8
= + + → = = =
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 12
R-2R Ladder DACHow Does it Work?
V B
Consider a simple 3bit R-2R DAC:
2R 2R 2R 2R
R RV
EE
I I 2I 4I
2I 4I
I out
Aunit Aunit 2Aunit 4Aunit
Ref: B. Razavi, “ Data Conversion System Design”, IEEE Press, 1995, page 84-87
In most cases need to convert output current to voltage
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 13
R-2R Ladder DAC
V B
2R 2R
Trans-resistance amplifier added to:- Convert current to voltage- Generate virtual ground @ current summing node so that outputimpedance of current sources do not cause error - Issue: error due to opamp offset
V out
R-
+
2R 2R 2R 2R
R R R RV EE
I I 2I 4I 8I 16I
2I 4I 8I 16I
RTotal
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 14
R-2R Ladder DACOpamp Offset Issueout in
os os Tota l
Tota l out inos os
Tota l
out inos os Tota l
Tota l ou t os
R1V V R
If R l a rg e,
V V
If R not l a rg e R1V V R
Problem:
Sin ce R is co de d ep en dan t V w ou ld be c od e d ep en da nt
Gives r ise to INL & DNL
⎛ ⎞+= ⎜ ⎟⎝ ⎠
=
→ ≈
=⎛ ⎞+→ = ⎜ ⎟⎝ ⎠
→
→
V out
R
-
+
RTotal
osV
OffsetModel
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 17
Current Source DAC
Unit Element
• Output resistance of current source gain error problemUse transresistance amplifier
- Current source output held @ virtual ground- Error due to current source output resistance eliminated- New issues: offset & speed of the amplifier
I ref I ref I ref I ref
……………
……………
Vout
R
-
+
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 18
Current Source DACBinary Weighted
• “Binary weighted”
• B current sources & switches (2 B-1 unit current sources but less# of switches)
• Monotonicity depends on element matching not guaranteed
4 I ref I ref
I out
2I ref 2 B-1 I ref
……………
……………
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 19
Static DAC Errors -INL / DNL
Static DAC errors mainly due to component mismatch – Systematic errors
• Contact resistance• Edge effects in capacitor arrays• Process gradients• Finite current source output resistance
– Random variations• Lithography etc…• Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSCAug. 1989, pp. 1118-28.
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 20
Current Source DACDNL/INL Due to Element Mismatch
• Simplified example: – 3-bit DAC – Assume only two of the current sources mismatched (# 4 & #5)
I ref I ref I ref I ref I ref
I ref +Δ I I ref -Δ I
Vout
-
+
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 23
Gaussian Distribution
-3 -2 -1 0 1 2 30
0.1
0.2
0.3
0.4
(x- μ ) / σ
P r o
b a
b i l i t y d e n s
i t y p
( x )
( )22
2
x2
2 2
variance
is the expected value and
1 p( x ) e2
where:
standard deviation : E( X )
μ σ
μ
πσ
σ μ σ
−−
→
=
= −
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 24
Yield
( )2 x X
2
X
P X x X
1e dx
2
X er f 2
π
+ −
−
− ≤ ≤ + =
=
⎛ ⎞
= ⎜ ⎟⎝ ⎠
∫
0
0.1
0.2
0.3
0.4
P r o
b a
b i l i t y d e n s
i t y
p ( x )
0 0.5 1 1.5 2 2.5 30
0.20.4
0.60.8
1
X/σ
38.3
68.3
95.4
P ( - X
≤ x
≤+
X )
In most cases we areinterested in finding thepercentage of components(e.g. R) falling withincertain bounds:
Integral has no analyticalsolution found by numericalmethods
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 25
Yield
X/σ P(-X ≤ x ≤ X) [%]
0.2000 15.85190.4000 31.08430.6000 45.14940.8000 57.62891.0000 68.26891.2000 76.98611.4000 83.84871.6000 89.0401
1.8000 92.81392.0000 95.4500
X/σ P(-X ≤ x ≤ X) [%]
2.2000 97.21932.4000 98.36052.6000 99.06782.8000 99.48903.0000 99.73003.2000 99.86263.4000 99.93263.6000 99.9682
3.8000 99.98554.0000 99.9937
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 26
Example• Measurements show that the offset voltage of
a batch of operational amplifiers follows aGaussian distribution with σ = 2mV and μ = 0.
• Find the fraction of opamps with |V os | < 6mV: – X/ σ = 3 99.73 % yield
• Fraction of opamps with |V os | < 400 μV: – X/ σ = 0.2 15.85 % yield
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 27
Component Mismatch
R
R
Δ
10000
100
200
300
400
N o .
o f r e s
i s t o r s
1004 1008 1012996992988 R[ ]Ω
Example: Resistors layouted outside-by-side
E.g. Let us assume in this example 1000 Rs measured& 68.5% fall within +-4OHM or +-0.4% of average
1σ for resistors 0.4%
After fabrication large # of devices measured& graphed typically if sample size large shapeis Gaussian
…….…….
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 28
Component Mismatch
1 2
1 2
2dR
R
R R R
2
dR R R
1
Areaσ
+=
= −
∝
R
R
Δ
00
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
P r o
b a
b i l i t y d e n s
i t y p
( x )
σ 2σ 3σ−σ−2σ−3σdR
RFor typical technologies & geometries1σ for resistors 0.02 to 5%
In the case of resistors σ is a function of area
Example: Two resistorslayouted out side-by-side
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 29
DNL Unit Element DAC
i i re f R I Δ =
E.g. Resistor string DAC:Assumption: No systematic error- only random error I ref
V ref
B
i
i
2 1
io
median ref med ian B
i i ref
i med iani
median
i median
imed ian median
DNL dR
R
R R I where R
2 R I
DNL
R R dR dR
R R R
σ σ
−
Δ = =
Δ =
Δ − Δ=
Δ
−= = ≈
=
∑
To first order DNL of unit element DAC is independent of resolution!Note: Similar results for other unit-element based DACs
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 30
DNL Unit Element DACExample:If σ dR/R = 0.4%, whatDNL spec goes intothe DAC datasheet sothat 99.9% of allconverters meet the
spec?
E.g. Resistor string DAC:
i
i
DNL dR
R
σ σ =
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 31
YieldX/σ P(-X ≤ x ≤ X) [%]
0.2000 15.85190.4000 31.08430.6000 45.14940.8000 57.62891.0000 68.26891.2000 76.98611.4000 83.84871.6000 89.0401
1.8000 92.81392.0000 95.4500
X/σ P(-X ≤ x ≤ X) [%]
2.2000 97.21932.4000 98.36052.6000 99.06782.8000 99.48903.0000 99.73003.2000 99.86263.4000 99.93263.6000 99.9682
3.8000 99.98554.0000 99.9937
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 32
DNL Unit Element DACExample:If σ dR/R = 0.4%, what DNL specgoes into the datasheet so that99.9% of all converters meetthe spec?
Answer:From table: for 99.9%
X/σ = 3.3σ
DNL= σ
dR/R= 0.4%
3.3 σ DNL = 3.3x0.4%=1.3%
DNL= +/- 0.013 LSB
E.g. Resistor string DAC:
i
i
DNL dR
R
σ σ =
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 33
DAC INL Analysis
B
A
N=2 B-1n
n
N
O u
t p u
t [ L S B ]
Input [LSB]
E
Ideal Variance A=n+E n n .σ ε
2
B=N-n-E N-n ( N-n) .σ ε 2
E = A-n r =n/N N=A+B= A-r(A+B)= (1-r). A - r.B Variance of E:
σ E2 =(1-r) 2 .σ Α
2 + r 2 .σ B2
= N.r .(1-r). σ ε2 = n .(1- n/N). σ ε
2
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 34
DAC INL
• Error is maximum at mid-scale ( N/2):
• INL depends on both DAC resolution & element matching σ ε
• While σ DNL = σ ε is to first order independent of DAC resolution and isonly a function of element matching
Ref: Kuboki et al, TCAS, 6/1982
2 2 E
2 E
2 2 E
B INL
B
n1n
N d
T o find max. var iance : 0dn
N n N / 2
4
12 1
2wi th N 2 1
ε
ε
ε
σ σ
σ
σ σ
σ σ
⎛ ⎞−= ×⎜ ⎟
⎝ ⎠
=
→ = → = ×
= −
= −0.5 1
0
(2 B-1)0.5 /2
0n/N
σ INL / σ ε
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 35
Untrimmed DAC INL
max
max
max
max
1% B 8.6bits
0.5% B 10.6bits
0.2% B 13.3bits
0.1% B 15.3bits
ε
ε
ε
ε
σ
σ
σ
σ
= → =
= → =
= → =
= → =
Example:
Assume the following requirementfor a DAC:
σ INL = 0.1 LSB
Find maximum resolution for:
Note: In most cases, a number of systematic errors preventsachievement of above results
B INL
INL2
1 2 12
B 2 2log
ε
ε
σ σ
σ σ
⎡ ⎤
⎢ ⎥⎣ ⎦
≅ −
≅ +
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 36
Simulation Exampleσ ε = 1%B = 12Random #generator used inMatLab
Computed INL:σ INL
max = 0.32 LSB(midscale)
Why is theresults not asexpected per our derivation?
500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
bin
D N L [ L S B ]
12 Bit converter DNL and INL
-0.04 / +0.03 LSB
500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
bin
I N L
L S B ] -0.2 / +0.8 LSB
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 37
INL & DNL for Binary Weighted DAC
• INL same as for unitelement DAC
• DNL depends on transition –Example:
0 to 1 σ DNL2 = σ (d Ι/Ι)
2
1 to 2 σ DNL2 = 3 σ (d Ι/Ι)
2
• Consider MSB transition:0111 … 1000 …
4 I ref I ref
I out
2I ref 2 B-1 I ref
……………
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 38
DAC DNLExample: 4bit DAC
0000 0001 0010 0011 0100 0101 0110 0111 1000
DigitalInput
AnalogOutput [I ref ]
8
7
6
5
4
3
2
1
0
4I ref I ref
I out
2I ref 8I ref
I 8 I 4 I 2 I 1
I 2on ,I 1on
I 2
on ,I 1
off
I 1on
• DNL depends on transition
– Example:
0 to 1 σ DNL2 = σ (d Ι ref /Ι ref )
2
1 to 2 σ DNL2 = 3 σ (d Ι ref /Ι ref )
2
I 4 on ,I 2off ,I 1off
.....
. . . . .
I 8off , I 4 on ,I 2on ,I 1on
I 8on , I 4 off ,I 2off ,I 1off
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 39
Binary Weighted DAC DNL
( ) ( )
DNLma x B
INL DNLma x ma x
2 B 1 2 B 1 2 DNL
B 2
B / 2
1 12 1
2 2
2 1 2
0111.. . 1000. ..
2
2
ε
ε ε
ε
ε
σ σ σ
σ
σ σ
σ σ σ
− −
=
≅ − ≅
= − +
≅
1442443 14243
• Worst-case transitionoccurs at mid-scale:
• Example:B = 12, σ ε = 1%
σ DNL = 0.64 LSB
σ INL = 0.32 LSB
2 4 6 8 10 12 140
5
10
15
DAC Output [LSB]
σ D N L
2 / σ
ε 2
DNL for a 4-Bit DAC
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 40
MOS Current Source VariationsDue to Device Matching Effectsd1 d2
d
d d1 d2
d d
W d th L
W GS d th L
I I I
2
dI I I
I I
dI d 2 dV
I V V
+=
−=
×= +
−
I d1 I d2
• Current matching depends on:- Device W/L ratio matching
Larger device area less mismatch effect- Current mismatch due to threshold voltage variations:
Larger gate-overdrive less threshold voltage mismatch effect
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 41
Current-Switched DACs in CMOS
W d th L
W d GS th L
dI d 2dV
I V V = +
−
I out
I ref
……
Switch Array
• Advantages:Can be very fastReasonable area for resolution < 9-10bits
• Disadvantages:Accuracy depends on device W/L & V th matching
256 128 64 ………..…..1
Example: 8bit Binary Weighted
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 42
Unit Element versus Binary Weighted DAC
Unit Element DAC Binary Weighted DAC
Number of switched elements:
Key point: Significant difference in performance and complexity!
B22 2 DNL INL
B 122 INL
S B
σ σ σ ε
σ σ ε
≅ =
−≅
=
DNL
B 122 INL
BS 2
σ σ ε
σ σ ε
=
−≅
=
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 43
Unit Element versus Binary Weighted DAC
Example: B=10
B2
DNL
1
B
INL 2 1
S 2 1 24
6
0
ε
ε ε
σ σ
σ σ σ −
=
≅ =
= =
Significant difference in performance and complexity!
B2
B2
DNL
1 INL
2 3
2 16
S B 10
2ε
ε ε
ε σ σ
σ σ
σ
σ −
≅ =
≅ =
= =
Unit Element DAC Binary Weighted DAC
Number of switched elements:
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 44
“Another” Random Run … Now (by chance) worstDNL is mid-scale.
Close to statistical result!500 1000 1500 2000 2500 3000 3500 4000-2
-1
0
1
2
bin
D N L [ L S B ]
DNL and INL of 12 Bit converter
-1 / +0.1 LSB,
500 1000 1500 2000 2500 3000 3500 4000-1
0
1
2
bin
I N L [ L S B ]
-0.8 / +0.8 LSB
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 45
10Bit DAC DNL/INL ComparisonPlots: 100 Simulation Runs Overlaid
Ref: C. Linand K. Bult,"A 10-b,500-MSample/sCMOS DACin 0.6mm2," IEEE Journal of Solid-StateCircuits, vol.33, pp. 1948- 1958,December 1998.
Note: σε =2%
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 46
10Bit DAC DNL/INL ComparisonPlots: RMS for 100 Simulation Runs
Ref: C. Linand K. Bult,"A 10-b,500-MSample/sCMOS DACin 0.6mm2," IEEE Journal of Solid-StateCircuits, vol.33, pp. 1948- 1958,December 1998.
Note: σε =2%
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 47
DAC INL/DNL Summary• DAC choice of architecture has significant impact on
DNL
• INL is independent of DAC architecture and requireselement matching commensurate with overall DACprecision
• Results assume uncorrelated random elementvariations
• Systematic errors and correlations are usually alsoimportant and may affect final DAC performance
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/Dconverters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 48
Segmented DACCombination of Unit-Element & Binary-Weighted
• Objective:Compromise between unit-element and binary-weighted DAC
• Approach:B1 MSB bits unit elementsB2 LSB bits binary weighted
• INL: unaffected same as either architecture• DNL: Worst case occurs when LSB DAC turns off and one more MSB DAC
element turns on Same as binary weighted DAC with (B 2+1) # of bits• Number of switched elements: (2 B1-1) + B 2
Unit Element Binary Weighted
V Analog
MSB (B1 bits) (B2 bits) LSB
… …
BTotal = B 1+B2
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 49
ComparisonExample:
B = 12, B 1 = 5, B 2 = 7 B1 = 6, B 2 = 6
Assuming: σ ε = 1%
( ) B 122
B2
DNL INL
1 INL
B12
2 2
2
S 2 1 B
ε
ε
σ σ σ
σ σ
+
−
≅ =
≅
= − +
409563+6=6931+7=38
12
0.010.1130.16 0.64
0.320.320.320.32
Unit element (12+0)Segmented (6+6)Segmented (5+7)Binary weighted(0+12)
# of switchedelements
σ DNL[LSB]σ INL[LSB]DAC Architecture(B1+B2)
MSB LSB
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 50
Practical AspectsCurrent-Switched DACs
Binary Thermometer 000 0000000001 0000001010 0000011011 0000111100 0001111101 0011111110 0111111111 1111111
• Unit element DACs ensure monotonicity byturning on equal-weighted current sources insuccession
• Typically current switching performed bydifferential pairs
• For each diff pair, only one of the devices areon switch device mismatch not an issue
• Issue: While binary weighted DAC can use theincoming binary digital word directly, unitelement requires a decoder
N to (2 N-1) decoder
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 53
Segmented Current-Switched DACCont’d
• MSB Decoder Domino logicExample: D4,5,6,7=1 OUT=1
• Register Latched NAND gate:CTRL=1 OUT=INB
Register
Domino Logic
IN
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 54
Segmented Current-Switched DACReference Current Considerations• I ref is referenced
to V DD
Problem:Referencecurrentvaries withsupply
voltage
+
-
I ref =(V DD-V ref ) / R
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 55
Segmented Current-Switched DACReference Current Considerations
• I ref isreferenced toV ss GND
+-
I ref =(V ref -V ss ) / R0
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 56
Segmented Current-Switched DACConsiderations• Example:
– 2bit MSB Unitelement DAC & 3bit
binary weighted DAC
• To ensure monotonicityat the MSB LSBtransition: First OFFMSB current source isrouted to LSB currentgenerator
MSB
LSB
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 57
DAC Dynamic Non-Idealities
• Finite settling time – Linear settling issues: (e.g. RC time constants) – Slew limited settling
• Spurious signal coupling – Coupling of clock/control signals to the output via
switches
• Timing error related glitches – Control signal timing skew
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 58
Dynamic DAC Error: Timing Glitch
• Consider binary weightedDAC transition 011 100
• DAC output depends ontiming
• Plot shows situation wherethe control signals for LSB &MSB
– LSB/MSBs on time – LSB early, MSB late – LSB late, MSB early
1 1.5 2 2.5 30
5
10
I d e a
l
1 1.5 2 2.5 30
5
10
E a r l y
1 1.5 2 2.5 30
5
10
Time
L a
t e
DAC Output
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 59
Glitch Energy• Glitch energy (worst case) proportional to: dt x 2 B-1
• dt error in timing & 2 B-1 associated with half of the switches changingstate
• LSB energy proportional to: T=1/f s
• Need dt x 2 B-1 << T or dt << 2-B+1 T
• Examples:
Timing accuracy for data converters much more critical compared to digitalcircuitry
<< 488<< 1.5<< 0.5
121612
120
1000
dt [ps]B f s [MHz]
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 60
DAC Dynamic Errors• To suppress effect of non-idealities:
– Retiming of current source control signals• Each current source has its own clocked latch
incorporated in the current cell• Minimization of latch clock skew by careful
layout ensuring simultaneous change of bits
– To minimize control and clock feed throughto the output via G-D & G-S of the switches• Use of low-swing digital circuitry
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 61
DAC Implementation Examples• Untrimmed segmented
– T. Miki et al, “An 80-MHz 8-bit CMOS D/A Converter,” JSSCDecember 1986, pp. 983
– A. Van den Bosch et al, “A 1-GSample/s Nyquist Current-SteeringCMOS D/A Converter,” JSSC March 2001, pp. 315
• Current copiers: – D. W. J. Groeneveld et al, “A Self-Calibration Technique for
Monolithic High-Resolution D/A Converters,” JSSC December 1989, pp. 1517
• Dynamic element matching: – R. J. van de Plassche, “Dynamic Element Matching for High-
Accuracy Monolithic D/A Converters,” JSSC December 1976, pp.795
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 62
2μ tech ., 5Vsupply6+2 segmented8x8 array
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 63
Two sources of systematic error:- Finite current source output resistance- Voltage drop due to finite ground bus resistance
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 64
Current-Switched DACs in CMOS
I out
Example: 5 unit element current sources
V DD
I 1 I 2 I 3 I 4
Rx4I Rx3I Rx2I
M 1 M 2 M 3 M 4 I 5M 5
Rx I
Assumptions: RxI small compared to transistor gate-overdriveTo simplify analysis: Initially, all device currents assumed to be equal to I
( )
M 2 M1
M 3 M1
M4 M1
M 5 M1
M 2
M1
GS GS
GS GS
GS GS
GS GS
2GS th2
2
2 1GS th
V V 4RI
V V 7RI
V V 9RI
V V 10RI
V V I k
4R I 1 I I
V V
⎛ ⎞
⎜ ⎟⎜ ⎟⎝ ⎠
= −
= −
= −
= −
−=
−=−
V G
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 65
Current-Switched DACs in CMOS
I out
Desirable to have g m small
Example: 5 unit element current sources
V DD
I 1 I 2 I 3 I 4
Rx4I Rx3I Rx2I
M 1 M 2 M 3 M 4 I 5M 5
Rx I
( )
( )
( )
( )
( )
M2
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
M1
22
GS th2 1GS th
1m
GS th2
m2 1 1 m
2m
3 1 1 m
2m
4 1 1 m
2m
5 1 1 m
4R I 1V V I k I
V V 2I
g V V
4R g I I I 1 4Rg 12
7R g I I I 1 7Rg 12
9R g I I I 1 9Rg 12
10Rg I I I 1 10Rg 1
2
⎛ ⎞−−= = ⎜ ⎟
−⎝ ⎠
=−
⎛ ⎞→ = ≈ −−⎜ ⎟
⎝ ⎠
⎛ ⎞→ = ≈ −−⎜ ⎟
⎝ ⎠
⎛ ⎞→ = ≈ −−⎜ ⎟
⎝ ⎠
⎛ ⎞→ = ≈ −−⎜ ⎟
⎝ ⎠
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 66
Current-Switched DACs in CMOSExample: INL of 3-Bit unit element DAC
Input
I N L [ L S B ]
Example: 7 unit element current source DAC- assume g m R=1/100
• If switching of current sources arranged sequentially (1-2-3-4-5-6-7) INL= +0.25LSB
• If switching of current sources symmetrical (4-3-5-2-6-1-7 ) INL = +0.09, -0.058LSB INL reduced by a factor of 2.6
-0.1
0
0.1
0.2
0.3
1 2 3 4 5 6 70
Sequential currentsource switching
Symmetrical currentsource switching
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EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 67
Current-Switched DACs in CMOSExample: DNL of 7 unit element DAC
Input
D N L [ L S B ]
Example: 7 unit element current source DAC- assume g m R=1/100
• If switching of current sources arranged sequentially (1-2-3-4-5-6-7) DNLmax= + 0.15LSB
• If switching of current sources symmetrical (4-3-5-2-6-1-7 ) DNLmax = + 0.15LSB DNLmax unchanged
-0.2
-0.1
0
0.1
0.2
1 2 3 4 5 6 7
Sequential currentsource switching
Symmetrical currentsource switching
EECS 247 Lecture 14: Data Converters- DAC Design © 2009 Page 68
Two sources of systematic error:- Finite current source output resistance- Voltage drop due to finite ground bus resistance