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L16 Kvs Sequential Circuits Full

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    :

    Sequential Circuit Design -1p op atc

    r. . . r vas avaDept. of Electrical Engineering

    IIT Kanpur

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    Digital Circuits

    Combinational Circuits Sequential Circuits

    CC

    X

    Y

    W

    CC

    Output is determined by

    Storageelements

    current values of inputs only. Output is determined in generalby current values of inputs and

    well. 2

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    NOR SR Latch

    QR

    1; 0 Set StateQ Q= =0 0

    1

    0; 1 Re et StateQ Q s= =1

    S 0

    1 0 1 0

    S R Q Q State

    SET

    3

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    NOR SR LatchReset

    QR

    1; 0 Set StateQ Q= =10

    0; 1 Re et StateQ Q s= =1S

    Set

    1 0 1 0

    S R Q Q State

    SET

    0 1 0 1 RESET

    4

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    HOLD State

    Q0

    QS 0

    1

    0

    1 0 1 0 SET

    0 1 0 1 RESET0 0 HOLDQ Q

    5

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    QR 1 0

    Both the outputs are well defined and 0.

    QS

    1 0The first problem is that we do not getcomplementary output.

    A more serious problem occurs when we switch the latch to the hold state by

    changing RS from 11 00 . Suppose the inputs do not change*

    QR

    QR

    QR1 0 0 1 0 1

    0S S S0

    Q = 1 6

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    QR

    QR Q

    R1 0 0 1 0 1

    QS

    QS

    QS1 0 1

    0 0 0

    Q = 1

    R R R1 0 1 0 0 0

    uppose e npu s c ange as =

    QS QS QS1 0 0 0

    Q = 0

    So although output is well defined when we apply RS = 11, it becomes

    unpredictable once we switch the latch to hold state by applying RS = 00. Thatis why RS = 11 is not used as an input combination.

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    The error can occur also due to unequal gate delays.

    Q1 Q1 QR

    1 10

    QS 21 0 QS 20 0 QS 20 0

    = -

    On the other hand suppose that gate-2 is faster.

    QR

    11 0 QR 1

    0 0Q

    R1

    0 0

    2 2 10

    S 0 S 0 S 0

    Q = 0 Again the output is unpredictable in general 8

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    NAND LatchS

    QR

    S R Q Q State

    0 1 1 0 SET

    1 1 HOLDQ Q

    0 0 1 1 INVALID

    9

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    RS NAND Latch with Enable

    SQ

    Q

    0

    1

    S Enable StateS R Q Q

    Q

    EN

    0

    1

    Hold

    Set

    x x

    1 0 1 0

    Q Q

    QR

    1 1

    1

    Hold

    Invalid

    Q Q

    1 1

    0 0

    0 0

    10

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    D latch

    QS QSD

    ENEN0

    1

    0

    Enable StateS R Q Q

    0 Holdx x Q Q QD1

    1

    Set

    Reset

    1 0 1 0

    0 1 0 1 QEN

    1

    1

    oInvalid

    1 1

    0 0

    If EN = 1 then Q = D otherwise the latch is in Hold state 11

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    Problem with Latchzn

    1

    QD

    clk

    yn

    1

    Circuits are designed with the idea there would be single change in outputor memory s a e n s ng e c oc cyc e.

    clk

    yz

    12

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    Edge Triggered Latch or Flip-flop

    QD

    clk

    Clock

    D

    Positive edge triggered flipflop 13

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    Negative Edge Triggered Latch or Flip-flop

    QD

    clk

    Clock

    D

    14

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    Master-Slave D Flip-flop

    QDDD

    EN QEN

    slavemaster

    clk

    Clock

    D

    Master

    QD

    clk

    Slave How do convert this into a positive edge triggered D flip-flop?15

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    Positive edge triggered D Flip-flop

    0

    25 Q

    S 01

    0

    clk

    0 1

    Q3

    6

    R 1

    1

    4D0 1

    16

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    Positive edge triggered D Flip-flop

    1

    25 Q

    S 0

    1

    clk

    0 1

    Q3

    6

    R 1 0

    4D1 0

    17

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    Positive edge triggered D Flip-flop

    1

    25 Q

    S10

    clk

    1

    Q3

    6

    R 0

    4D1 00 1

    A change in input has no effect if it occurs after the clock edge 18

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    JK Flip-flop

    0 0 0 0

    0 0 1 0 )()()1( t QK t Q J t Q +=+0 1 0 1

    0 1 1 1

    1 0 0 1

    1 0 1 0JK fl ip flop is refinement of RS flipflop where indeterminate state of RS

    19

    1 1 0 1

    1 1 1 0

    flip flop is defined in JK Flip Flop.

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    Toggle or T Flip-flop

    0 0 0

    0 1 1t T t =+

    1 0 1

    1 1 0

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    Characteristic tableGiven a input and the present state of the flip-flop, what is the next state of

    Q(t+1)Inputs D

    -

    D Flip-flop

    clk 0 01 1

    -

    Dt Q =+ )1(Characteristic equation:

    QJ

    Q(t+1)Inputs

    J K

    0 0 Q(t)

    clk

    K

    1 0 1

    1 1 Q t

    )()()1( t QK t Q J t Q +=+Characteristic equation: 21

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    Toggle or T Flip-flop

    Q

    clk

    T npu s

    0 Q(t)

    1 Q t

    1 t T t =+Characteristic equation:

    Excitation TableWhat in uts are re uired to effect a articular state chan e

    Inputs

    Q(t+1)Q(t) TQ T Q(t+1)Excitation Table

    0 0

    0 1

    0

    10 0 00 1 1

    1 1 01 1 0 22

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    Excitation Table

    J K Q t+1

    Inputs

    Q t+1Q t J KQ

    clk

    J Q(t)0 00 1

    1 0

    0

    1

    0 0

    0 1

    0 X

    1 X

    K 1 1 Q(t) 1 0

    1 1 X 0

    X 1

    Characterist ic Table

    xc a on a eQ J K Q(t+1)

    0 0 0 00 0 1 0

    0 1 0 1

    1 0 0 1

    1 0 1 0

    1 1 0 1

    1 1 1 0 23

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    Excitation Table

    QD

    clk

    Q(t+1)D

    0 0

    1 1

    Characterist ic Table

    Inputs

    Q D Q(t+1)

    0 0 0

    0 0

    Q(t+1)Q(t) D

    0

    0 1 1

    1 0 0

    1 0

    1 1

    10

    1

    1 1 1

    Excitation Table24

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    Convert a D FF to JK FF

    J K Q Q(t+1) D

    clk

    QD

    CCJ

    0 0

    0 1

    0 X

    1 X

    0

    1K

    1 0X 1 0

    1 1

    1 1

    = . .26

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    Convert a D FF to JK FF

    . . Q J K D Q(t+1)0 0 0 0 0

    0 0 1

    0 1 0

    1 1

    1 0 0

    1 1

    1 1 0

    1 1 1

    Q(t+1)Inputs J K

    1 1

    0 0

    00 1

    1 0 1

    1 1 Q(t)

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